IRFS9N60A, SiHFS9N60A
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Power MOSFET
FEATURES
D
• Low gate charge Qg results in simple drive
requirement
D2PAK (TO-263)
Available
• Improved gate, avalanche and dynamic dV/dt
ruggedness
G
Available
• Fully characterized capacitance and avalanche
voltage and current
G D
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
600
VGS = 10 V
APPLICATIONS
0.75
Qg max. (nC)
49
• Switch mode power supply (SMPS)
Qgs (nC)
13
• Uninterruptible power supply
Qgd (nC)
20
• High speed power switching
Configuration
Single
APPLICABLE OFF LINE SMPS TOPOLOGIES
• Active clamped forward
• Main switch
ORDERING INFORMATION
Package
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
Lead (Pb)-free and Halogen-free
SiHFS9N60A-GE3
SiHFS9N60ATRR-GE3 a
SiHFS9N60ATRL-GE3 a
Lead (Pb)-free
IRFS9N60APbF
IRFS9N60ATRRPbF a
IRFS9N60ATRLPbF a
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
600
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
UNIT
V
9.2
5.8
A
IDM
37
1.3
W/°C
Single Pulse Avalanche Energy b
EAS
290
mJ
Repetitive Avalanche Current a
IAR
9.2
A
Repetitive Avalanche Energy a
EAR
17
mJ
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dt c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature) d
for 10 s
PD
170
W
dV/dt
5.0
V/ns
TJ, Tstg
-55 to +150
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 6.8 mH, Rg = 25 , IAS = 9.2 A (see fig. 12)
c. ISD 9.2 A, dI/dt 50 A/μs, VDD VDS, TJ 150 °C
d. 1.6 mm from case
S21-0943-Rev. E, 20-Sep-2021
Document Number: 91287
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
0.75
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
V/°C
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = 250 μA
600
-
-
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.66
-
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 600 V, VGS = 0 V
-
-
25
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
μA
-
-
0.75
gfs
VDS = 25 V, ID = 3.1 A
5.5
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1400
-
-
180
-
-
7.1
-
-
1957
-
RDS(on)
ID = 5.5 A b
VGS = 10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VDS = 1.0 V, f = 1.0 MHz
VGS = 0 V
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
VDS = 480 V, f = 1.0 MHz
-
49
-
VDS = 0 V to 480 V c
-
96
-
-
-
49
-
-
13
ID = 9.2 A, VDS = 400 V
see fig. 6 and 13 b
Gate-Drain Charge
Qgd
-
-
20
Turn-On Delay Time
td(on)
-
13
-
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VDD = 300 V, ID = 9.2 A
Rg = 9.1 , RD = 35.5
see fig. 10 b
-
25
-
-
30
-
-
22
-
f = 1 MHz, open drain
0.5
-
3.2
-
-
9.2
-
-
37
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current a
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 9.2 A, VGS = 0 V b
TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μs b
-
-
1.5
V
-
530
800
ns
-
3.0
4.4
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS
S21-0943-Rev. E, 20-Sep-2021
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IRFS9N60A, SiHFS9N60A
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.7V
I D , Drain-to-Source Current (A)
10
1
4.7V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
100
1
10
TJ = 150 ° C
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
9.0
VDS , Drain-to-Source Voltage (V)
VGS , Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.7V
TOP
I D , Drain-to-Source Current (A)
10
0.1
4.0
100
10
4.7V
20µs PULSE WIDTH
TJ = 150 ° C
1
1
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
S21-0943-Rev. E, 20-Sep-2021
100
r DS(on), Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TOP
10.0
ID = 9.2A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91287
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IRFS9N60A, SiHFS9N60A
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2400
100
ISD , Reverse Drain Current (A)
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
2000
C, Capacitance (pF)
Vishay Siliconix
iss
1600
oss
1200
800
rss
400
0
A
1
10
100
1000
10
TJ = 150 ° C
1
TJ = 25 ° C
V GS = 0 V
0.1
0.2
0.5
VDS , Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
1.0
1.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
1000
ID = 9.2A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 480V
VDS = 300V
VDS = 120V
16
100
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
20
0.7
VSD ,Source-to-Drain Voltage (V)
12
8
10us
10
100us
1ms
1
10ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
20
30
40
50
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0943-Rev. E, 20-Sep-2021
0.1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 1 - Maximum Safe Operating Area
Document Number: 91287
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IRFS9N60A, SiHFS9N60A
www.vishay.com
Vishay Siliconix
RD
VDS
10.0
VGS
8.0
ID , Drain Current (A)
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
6.0
Fig. 10a - Switching Time Test Circuit
4.0
VDS
90 %
2.0
0.0
25
50
75
100
125
10 %
VGS
150
TC , Case Temperature ( ° C)
td(on)
Fig. 8 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.01
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
Rg
D.U.T
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
S21-0943-Rev. E, 20-Sep-2021
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91287
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IRFS9N60A, SiHFS9N60A
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EAS , Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
600
TOP
500
BOTTOM
ID
4.1A
5.8A
9.2A
400
300
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0943-Rev. E, 20-Sep-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91287
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Peak Diode Recovery dv/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
3
+
2
-
-
4
+
1
Rg
•
•
•
•
1 Driver gate drive
Period
P.W.
+
V
- DD
dv/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
D=
P.W.
Period
V GS = 10 V a
2
D.U.T. ISD waveform
Reverse
recovery
current
3 D.U.T. VDS
Body diode forward
current
di/dt
waveform
Diode recovery
dv/dt
Re-applied
voltage
V DD
Body diode forward drop
4 Inductor current
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91287.
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Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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