IRLD120PBF

IRLD120 www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • Dynamic dV/dt rating HVMDIP • Repetitive avalanche rated • For automatic insertion G • End stackable • Logic-level gate drive S G • RDS(on) specified at VGS = 4 V and 5 V S D • 175 °C operating temperature N-Channel MOSFET • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 PRODUCT SUMMARY VDS (V) DESCRIPTION 100 RDS(on) (Ω) VGS = 5.0 V Qg (Max.) (nC) Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. 0.27 12 Qgs (nC) 3.0 Qgd (nC) 7.1 Configuration The 4 pin DIP package is a low cost machine-insertable case style which can be stacked in multiple combinations on standard 0.1" pin centers. The dual drain serves as a thermal link to the mounting surface for power dissipation levels up to 1 W. Single ORDERING INFORMATION Package HVMDIP Lead (Pb)-free IRLD120PbF ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 100 Gate-source voltage VGS ± 10 VGS at 5 V Continuous drain current TA = 25 °C TA = 100 °C Pulsed drain current a ID IDM Linear derating factor UNIT V 1.3 0.94 A 10 0.0083 W/°C Single pulse avalanche energy b EAS 690 mJ Repetitive avalanche current a IAR 1.3 A EAR 0.13 mJ PD 1.3 W dV/dt 5.5 V/ns TJ, Tstg - 55 to + 175 Repetitive avalanche energy a Maximum power dissipation TA = 25 °C Peak diode recovery dv/dt c Operating junction and storage temperature range Soldering rRecommendations (peak temperature) d For 10 s 300d °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 25 V, starting TJ = 25 °C, L = 153 mH, Rg = 25 Ω, IAS = 2.6 A (see fig. 12) c. ISD ≤ 9.2 A, dI/dt ≤ 110 A/μs, VDD ≤ VDS, TJ ≤ 175 °C d. 1.6 mm from case S21-0886-Rev. D, 30-Aug-2021 Document Number: 91310 1 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLD120 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient SYMBOL TYP. MAX. UNIT RthJA - 120 °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 100 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C VGS(th) VDS = VGS, ID = 250 μA 1.0 - 2.0 V Gate-Source Leakage IGSS VGS = ± 10 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 150 °C - - 250 Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VGS = 5.0 V ID = 0.78 Ab - - 0.27 VGS = 4.0 V ID = 0.65 Ab - - 0.38 1.9 - - - 490 - - 150 - - 30 - - - 12 - - 3.0 VDS = 50 V, ID = 0.78 Ab μA Ω S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 5.0 V ID = 9.2 A, VDS = 80 V, see fig. 6 and 13b Gate-Drain Charge Qgd - - 7.1 Turn-On Delay Time td(on) - 9.8 - Rise Time Turn-Off Delay Time Fall Time tr td(off) LD Internal Source Inductance LS nC - 64 - - 21 - - 27 - - 4.0 - - 6.0 - - - 1.3 S - - 10 TJ = 25 °C, IS = 1.3 A, VGS = 0 Vb - - 2.5 - 130 140 ns - 0.83 1.0 μC VDD = 50 V, ID = 9.2 A, Rg = 9.0 Ω, RD = 5.2 Ω, see fig. 10b tf Internal Drain Inductance pF Between lead, 6 mm (0.25") from package and center of die contact D ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % S21-0886-Rev. D, 30-Aug-2021 Document Number: 91310 2 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLD120 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 20 μs PULSE WIDTH TA = 25 °C Fig. 1 - Typical Output Characteristics, TA = 25 °C Fig. 3 - Typical Transfer Characteristics 20 μs PULSE WIDTH TA = 175 °C Fig. 2 - Typical Output Characteristics, TA = 175 °C S21-0886-Rev. D, 30-Aug-2021 Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91310 3 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLD120 www.vishay.com Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage TA = 25 °C TJ = 175 °C SINGLE PULSE Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area S21-0886-Rev. D, 30-Aug-2021 Document Number: 91310 4 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLD120 www.vishay.com Vishay Siliconix VDS VGS RD D.U.T. ID, Drain Current (A) Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % TA, Ambient Temperature (°C) 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Thermal Response (ZthJA) Fig. 9 - Maximum Drain Current vs. Ambient Temperature t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient S21-0886-Rev. D, 30-Aug-2021 Document Number: 91310 5 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLD120 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T Rg + - I AS V DD VDS 5V 0.01 W tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S21-0886-Rev. D, 30-Aug-2021 Fig. 13b - Gate Charge Test Circuit Document Number: 91310 6 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLD120 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91310. S21-0886-Rev. D, 30-Aug-2021 Document Number: 91310 7 For technical questions, contact: hvmos.techsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix HVM DIP (High voltage) 0.248 [6.29] 0.240 [6.10] 0.043 [1.09] 0.035 [0.89] 0.197 [5.00] 0.189 [4.80] 0.133 [3.37] 0.125 [3.18] 0.180 [4.57] 0.160 [4.06] 0.094 [2.38] 0.086 [2.18] A L 0.160 [4.06] 0.140 [3.56] 0° to 15° 2x 0.017 [0.43] 0.013 [0.33] 0.045 [1.14] 2 x 0.035 [0.89] E min. 0.024 [0.60] 4x 0.020 [0.51] 0.100 [2.54] typ. E max. INCHES MILLIMETERS DIM. MIN. MAX. MIN. A 0.310 0.330 7.87 MAX. 8.38 E 0.300 0.425 7.62 10.79 L 0.270 0.290 6.86 7.36 ECN: X10-0386-Rev. B, 06-Sep-10 DWG: 5974 Note 1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions. Document Number: 91361 Revision: 06-Sep-10 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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