IRLR120TRPBF

IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 100 RDS(on) () VGS = 5.0 V 0.27 Qg (Max.) (nC) 12 Qgs (nC) 3.0 Qgd (nC) 7.1 Configuration Single D DPAK (TO-252) IPAK (TO-251) DESCRIPTION D D Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRLU, SiHLU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. G G Dynamic dV/dt Rating Repetitive Avalanche Rated Surface Mount (IRLR120, SiHLR120) Straight Lead (IRLU120, SiHLU120) Available in Tape and Reel Logic-Level Gate Drive RDS(on) Specified at VGS = 4 V and 5 V Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 S G D S S N-Channel MOSFET ORDERING INFORMATION Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) Lead (Pb)-free and Halogen-free SiHLR120-GE3 SiHLR120TRL-GE3 SiHLR120TR-GE3 SiHLR120TRR-GE3 SiHLU120-GE3 IRLR120PbF IRLR120TRLPbFa IRLR120TRPbFa IRLR120TRRPbFa IRLU120PbF SiHLR120-E3 SiHLR120TL-E3a SiHLR120T-E3a SiHLR120TR-E3a SiHLU120-E3 Lead (Pb)-free Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 100 Gate-Source Voltage VGS ± 10 VGS at 5.0 V Continuous Drain Current TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM UNIT V 7.7 4.9 A 31 Linear Derating Factor 0.33 Linear Derating Factor (PCB Mount)e 0.020 W/°C Single Pulse Avalanche Energyb EAS 210 Repetitive Avalanche Currenta IAR 7.7 A Repetitive Avalanche Energya EAR 4.2 mJ Maximum Power Dissipation Maximum Power Dissipation (PCB TC = 25 °C Mount)e TA = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)d for 10 s PD 42 2.5 dV/dt 5.5 TJ, Tstg - 55 to + 150 260 mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 5.3 mH, Rg = 25 , IAS = 7.7 A (see fig. 12). c. ISD  9.2 A, dI/dt  110 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S13-0167-Rev. D, 04-Feb-13 Document Number: 91324 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 3.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 100 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.13 - V/°C VGS(th) VDS = VGS, ID = 250 μA 1.0 - 2.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VGS = ± 10 V - - ± 100 VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 125 °C - - 250 IGSS IDSS RDS(on) gfs VGS = 5.0 V ID = 4.6 Ab - - 0.27 VGS = 4.0 V ID = 3.9 Ab - - 0.38 4.4 - - - 490 - VDS = 50 V, ID = 4.6 Ab μA  S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 150 - - 30 - - - 12 - - 3.0 Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 7.1 Turn-On Delay Time td(on) - 9.8 - tr - 64 - - 21 - - 27 - - 4.5 - - 7.5 - - - 7.7 - - 31 Rise Time Turn-Off Delay Time Fall Time td(off) VGS = 5.0 V ID = 9.2 A, VDS = 80 V, see fig. 6 and 13b VDD = 50 V, ID = 9.2 A, Rg = 9.0 , RD = 5.2 , see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contactc pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 7.7 A, VGS = 0 S Vb TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μsb - - 2.5 V - 110 140 ns - 0.80 1.0 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. S13-0167-Rev. D, 04-Feb-13 Document Number: 91324 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C S13-0167-Rev. D, 04-Feb-13 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91324 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S13-0167-Rev. D, 04-Feb-13 Vishay Siliconix Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91324 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Vishay Siliconix VDS VGS RD D.U.T. Rg + - VDD 5.0 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S13-0167-Rev. D, 04-Feb-13 Document Number: 91324 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T Rg + - I AS V DD VDS 5.0 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S13-0167-Rev. D, 04-Feb-13 Fig. 13b - Gate Charge Test Circuit Document Number: 91324 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLR120, IRLU120, SiHLR120, SiHLU120 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91324. S13-0167-Rev. D, 04-Feb-13 Document Number: 91324 7 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-252AA Case Outline E MILLIMETERS A C2 e b2 D1 e1 E1 L gage plane height (0.5 mm) L4 b L5 H D L3 b3 C A1 INCHES DIM. MIN. MAX. MIN. MAX. A 2.18 2.38 0.086 0.094 A1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 b3 4.95 5.46 0.195 0.215 0.024 C 0.46 0.61 0.018 C2 0.46 0.89 0.018 0.035 D 5.97 6.22 0.235 0.245 D1 4.10 - 0.161 - E 6.35 6.73 0.250 0.265 E1 4.32 - 0.170 - H 9.40 10.41 0.370 0.410 e 2.28 BSC e1 0.090 BSC 4.56 BSC 0.180 BSC L 1.40 1.78 0.055 0.070 L3 0.89 1.27 0.035 0.050 L4 - 1.02 - 0.040 L5 1.01 1.52 0.040 0.060 ECN: T13-0359-Rev. O, 03-Jun-13 DWG: 5347 Notes • Dimension L3 is for reference only. • Xi’an, Mingxin, and GEM SH actual photo. Revision: 03-Jun-13 Document Number: 71197 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 3 E1 E Thermal PAD 4 b4 θ2 4 A 0.010 0.25 M C A B L2 4 c2 A θ1 B D D1 A C 3 Seating plane 5 C L1 L3 (Datum A) C L B B A A1 3 x b2 View A - A 2xe c 3xb 0.010 0.25 M C A B Plating 5 b1, b3 Base metal Lead tip c1 (c) 5 (b, b2) Section B - B and C - C MILLIMETERS DIM. MIN. MAX. INCHES MIN. MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 4.32 - 0.170 - b 0.64 0.89 0.025 0.035 E1 b1 0.65 0.79 0.026 0.031 e b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 2.29 BSC 2.29 BSC c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 Revision: 15-Sep-08 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000