SI5486DU-T1-E3

Si5486DU Vishay Siliconix N-Channel 20-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 20 RDS(on) () ID (A)a 0.015 at VGS = 4.5 V 12 0.017 at VGS = 2.5 V 12 0.021 at VGS = 1.8 V 12 • TrenchFET® Power MOSFET • New Thermally Enhanced PowerPAK® ChipFET® Package - Small Footprint Area - Low On-Resistance - Thin 0.8 mm Profile • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 Qg (Typ.) 21 nC PowerPAK ChipFET Single APPLICATIONS • Load Switch, PA Switch, and for Portable Applications • Point-of-Load 1 2 D 3 D D 8 G D 7 D 4 D D S 6 Marking Code S 5 AG G XXX Lot Traceability and Date Code Bottom View Part # Code S Ordering Information: Si5486DU-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C) TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C ID TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C Maximum Power Dissipation TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range Continuous Source-Drain Diode Current Unit V 12a 12a 11.6b, c 9.3b, c 40 IDM Pulsed Drain Current Soldering Recommendations (Peak Limit 20 ±8 Symbol VDS VGS A 12a 2.6b, c 31 20 IS PD W 3.1b, c 2b, c - 55 to 150 260 TJ, Tstg Temperature)d, e °C THERMAL RESISTANCE RATINGS t5s Symbol RthJA Typical 34 Maximum 40 Steady State RthJC 3 4 Parameter Maximum Junction-to-Ambientb, f Maximum Junction-to-Case (Drain) Unit °C/W Notes: a. Package limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 90 °C/W. Document Number: 73783 S13-0194-Rev. C, 28-Jan-13 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5486DU Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = 250 µA 20 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS/TJ VDS Temperature Coefficient VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage ID = 250 µA VGS(th) VDS = VGS , ID = 250 µA Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 8 V Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Drain-Source On-State Resistance a RDS(on) Forward Transconductancea gfs V 21 mV/°C - 3.4 0.4 1 V ± 100 nA VDS = 20 V, VGS = 0 V 1 VDS = 20 V, VGS = 0 V, TJ = 55 °C 10 VDS 5 V, VGS = 4.5 V µA A 40 VGS 4.5 V, ID = 7.7 A 0.012 0.015 VGS 2.5 V, ID = 7.3 A 0.014 0.017 VGS 1.8 V, ID = 4.8 A 0.017 0.021 VDS = 10 V, ID = 7.7 A 46  S b Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge 36 54 Qg 21 32 Gate-Source Charge Qgs 3.3 Gate-Drain Charge Qgd 2100 VDS = 10 V, VGS = 0 V, f = 1 MHz VDS = 10 V, VGS = 8 V, ID = 9.3 A Rg Gate Resistance VDS = 10 V, VGS = 4.5 V, ID = 9.3 A tr Rise Time f = 1 MHz Fall Time Turn-On Delay Time 25 75 tf 15 25 td(on) 7 15 td(off) Turn-Off Delay Time VDD = 10 V, RL = 1.1  ID  9.3 A, VGEN = 4.5 V, Rg = 1  VDD = 10 V, RL = 1.1  ID  9.3 A, VGEN = 10 V, Rg = 1  tf Fall Time 15 15 tr Rise Time nC  5 10 50 td(off) Turn-Off Delay Time pF 3.1 td(on) Turn-on Delay Time 310 180 15 25 55 85 10 15 ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C 12 40 IS = 9.1 A, VGS = 0 V IF = 9.3 A, dI/dt = 100 A/µs, TJ = 25 °C A 0.8 1.2 V 30 60 ns 17 30 nC 12 18 ns Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 For technical questions, contact: pmostechsupport@vishay.com Document Number: 73783 S13-0194-Rev. C, 28-Jan-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5486DU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 40 20 VGS = 5 thru 2 V 16 I D - Drain Current (A) I D - Drain Current (A) 32 24 16 VGS = 1.5 V 12 TC = - 55 °C 8 8 TC = 125 °C TC = 25 °C 4 VGS = 1 V 0 0.0 0.4 0.8 1.2 1.6 0 0.0 2.0 0.3 VDS - Drain-to-Source Voltage (V) Output Characteristics 1.2 1.5 3000 2500 0.022 C - Capacitance (pF) Ciss 0.019 VGS = 1.8 V 0.016 VGS = 2.5 V 2000 1500 1000 VGS = 4.5 V 0.013 Coss 500 0.010 Crss 0 0 8 16 24 32 40 0 4 ID - Drain Current (A) 8 12 16 20 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 1.6 8 RDS(on) - On-Resistance (Normalized) ID = 9.3 A VGS - Gate-to-Source Voltage (V) 0.9 Transfer Characteristics 0.025 R DS(on) - On-Resistance (mΩ) 0.6 VGS - Gate-to-Source Voltage (V) 6 VDS = 10 V VDS = 16 V 4 2 0 0 8 16 24 Qg - Total Gate Charge (nC) Gate Charge Document Number: 73783 S13-0194-Rev. C, 28-Jan-13 32 40 VGS = 4.5, 2.5 V, 1.8 V ID = 7.7 A 1.4 1.2 1.0 0.8 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature For technical questions, contact: pmostechsupport@vishay.com www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5486DU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) I S - Source Current (A) TJ = 150 °C TJ = 25 °C 10 1 0.0 0.040 R DS(on) - Drain-to-Source On-Resistance (mΩ) 40 ID = 7.7 A 0.035 0.030 0.025 TA = 125 °C 0.020 0.015 TA = 25 °C 0.010 0.2 0.4 0.6 0.8 1.0 1.2 0 1 VSD - Source-to-Drain Voltage (V) 2 3 4 5 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.9 50 0.8 40 ID = 250 µA 0.6 Power (W) VGS(th) (V) 0.7 0.5 0.4 30 20 0.3 10 0.2 0.1 - 50 - 25 0 25 50 75 100 125 0 0.001 150 0.01 0.1 1 10 100 1000 Time (s) TJ - Temperature (°C) Threshold Voltage Single Pulse Power, Junction-to-Ambient 100 Limited by RDS(on)* 100 µs I D - Drain Current (A) 10 1 ms 10 ms 1 100 ms TA = 25 °C Single Pulse 1s 10 s 0.1 DC BVDSS Limited 0.01 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient www.vishay.com 4 For technical questions, contact: pmostechsupport@vishay.com Document Number: 73783 S13-0194-Rev. C, 28-Jan-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5486DU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 35 40 30 Power Dissipation (W) I D - Drain Current (A) 32 24 16 Package Limited 25 20 15 10 8 5 0 0 0 25 50 75 100 TC - Case Temperature (°C) Current Derating* 125 150 25 50 75 100 125 150 TC - Case Temperature (°C) Power Derating * The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 73783 S13-0194-Rev. C, 28-Jan-13 For technical questions, contact: pmostechsupport@vishay.com www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si5486DU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 PDM 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 75 °C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) 10 100 1000 Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.05 0.02 0.1 10-4 Single Pulse 10-3 10-2 Square Wave Pulse Duration (s) 10-1 1 Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73783. www.vishay.com 6 For technical questions, contact: pmostechsupport@vishay.com Document Number: 73783 S13-0194-Rev. C, 28-Jan-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® ChipFET® Case Outline D (7) (6) (5) (1) (2) (3) (4) E (8) Pin #1 indicator Side view of single e b H D1 D(2) D2 K D(3) L G(4) K1 D2 SI(1) GI(2) S2(3) D1(8) D1(7) D2(6) Detail Z G2(4) K2 L D(1) A1 C A Z Side view of dual E1 E2 E3 H D3 D(8) D(7) D(6) S(5) K3 Backside view of dual pad Backside view of single pad DIM. D2(5) MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.85 0.028 0.030 0.033 A1 0 - 0.05 0 - 0.002 b 0.25 0.30 0.35 0.010 0.012 0.014 C 0.15 0.20 0.25 0.006 0.008 0.010 D 2.92 3.00 3.08 0.115 0.118 0.121 D1 1.75 1.87 2.00 0.069 0.074 0.079 D2 1.07 1.20 1.32 0.042 0.047 0.052 D3 0.20 0.25 0.30 0.008 0.010 0.012 E 1.82 1.90 1.98 0.072 0.075 0.078 E1 1.38 1.50 1.63 0.054 0.059 0.064 E2 0.92 1.05 1.17 0.036 0.041 0.046 E3 0.45 0.50 0.55 0.018 0.020 0.022 e 0.65 BSC 0.026 BSC H 0.15 0.20 0.25 0.006 0.008 0.010 K 0.25 - - 0.010 - - K1 0.30 - - 0.012 - - K2 0.20 - - 0.008 - - K3 0.20 - - 0.008 - - L 0.30 0.35 0.40 0.012 0.014 0.016 C14-0630-Rev. E, 21-Jul-14 DWG: 5940 Note • Millimeters will govern Document Number: 73203 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 21-Jul-14 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Single 0.225 (0.009) 0.350 (0.014) 0.650 (0.026) 0.200 (0.008) 0.300 (0.012) 0.300 (0.012) 0.100 (0.004) 1.500 (0.059) 1.900 (0.075) 0.250 (0.010) 0.500 (0.020) 0.350 (0.014) 0.350 (0.014) 1.870 (0.074) 0.305 (0.012) 2.575 (0.101) Recommended Minimum Pads Dimensions in mm/(Inches) Return to Index APPLICATION NOTE Document Number: 69948 Revision: 21-Jan-08 www.vishay.com 9 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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