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SI9243AEY-T1-E3

SI9243AEY-T1-E3

  • 厂商:

    TFUNK(威世)

  • 封装:

    SOIC8

  • 描述:

    IC TRANSCEIVER HALF 1/2 8SOIC

  • 数据手册
  • 价格&库存
SI9243AEY-T1-E3 数据手册
Product is End of Life 12/2014 Si9243A Vishay Siliconix Single-Ended Bus Transceiver DESCRIPTION FEATURES The Si9243AEY is a monolithic bus transceiver designed to provide bidirectional serial communication in automotive diagnostic applications. • Operating Power Supply Range 6 V ≤ VBAT ≤ 36 V • Reverse Battery Protection Down to VBAT ≥ - 24 V • Standby Mode With Very Low Current Consumption IBAT(SB) = 1 µA at VDD = 0.5 V • Low Quiescent Current in OFF Condition IBAT = 120 µA and IDD ≤ 10 A • ISO 9141 Compatible • Overtemperature Shutdown Function For K Output • Defined K Output OFF for Open GND • Defined Receive Output Status for Open K Input • Defined K Output OFF for TX Input Open • Open Drain Fault Output • 2 kV ESD • Typical Transmit Speeds of 200 kBaud The device incorporates protection against overvoltages and short circuits to VBAT. The transceiver pin is protected and can be driven beyond the VBAT voltage. The RX output is capable of driving CMOS or 1 x LSTTL load. The Si9243AEY is built on the Vishay Siliconix BiC/DMOS process. This process supports bipolar transistors, CMOS, and DMOS. An epitaxial layer prevents latchup. The Si9243AEY is available in a 8-pin SO package and operates over the automotive temperature range (- 40 °C to 125 °C). The Si9243AEY is available in both standard and lead (Pb)-free packages. PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM GND VDD VBAT VDD RXL VDD RXK + L - L + K - K + VBAT/2 VDD K TX Document Number: 70788 S11-0975-Rev. F, 16-May-11 Logic and Fault Detect Circuitry (See State Diagram and Truth Table) www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9243A Vishay Siliconix OUTPUT TABLE AND STATE DIAGRAMS Over Temp Power On A=1 INPUTS A=0 Over Temp . TX Short Circuit Power On B=1 B=0 TX Note: Over Temp is an internal condition, not meant to be a logic signal. STATE VARIABLE OUTPUT TABLE RXK RXL TX L A B K 0 0 1 1 0 0 0 Comments 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 1 1 0 X L 0 1 HiZ K L Over Temp 0 L 1 0 HiZ K L Short Circuit 1 1 1 1 1 1 1 Receive Mode 1 0 1 1 0 0 0 X = "1" or "0" HiZ = High Impedance State ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit Voltages Referenced to Ground Voltage On VBAT Voltage K, L Voltage Difference V(VBAT, K, L) Voltage On Any Pin (Except VBAT , K, L) or Max. Current Voltage on VDD K Pin Only, Short Circuit Duration (to VBAT or GND) - 24 to 45 - 16 to (VBAT + 1) 55 - 0.3 V to (VDD + 0.3 V) or 10 mA 7 V Continuous Operating Temperature (TA) - 40 to 125 Junction and Storage Temperature - 55 to 150 Thermal Impedance (ΘJA) V 125 °C °C/W Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Limit Unit Voltages Referenced to Ground VDD 4.5 to 5.5 VBAT 6 to 36 K, L 6 to 36 Digital Inputs www.vishay.com 2 V 0 to VDD Document Number: 70788 S11-0975-Rev. F, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9243A Vishay Siliconix SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VDD = 4.5 V to 5.5 V VBAT = 6 V to 36 V Limits - 40 to 125 °C Temp.a Transmitter and Logic Levels TX Input Low Voltage VILT Full TX Input High Voltage VIHT Full TX Input Capacitanced TX Input Pull-up Resistance CINT RTX Min.b Typ.c 1.5 Full V 3.5 Full VDD = 5.5 V, TX = 1.5 V, 3.5 V Unit Max.b 10 20 10 pF 40 kΩ K Transmit VOLK K Output Low Voltage VOHK K Output High Voltage K Rise, Fall Times tr, tf K Output Sink Resistance Rsi K Output Capacitanced Receiver L and K Input High Voltage CO L and K Input Hysteresisc, d L and K Input Currents RL = 510 Ω ± 5 %, VBAT = 6 to 18 Full 0.2 VBAT RL = 1 kΩ ± 5 %, VBAT = 16 to 36 Full 0.2 VBAT RL = 510 Ω ± 5 %, VBAT = 4.5 Full RL = 510 Ω ± 5 %, VBAT = 4.5 to 18 Full 0.95 VBAT RL = 1 kΩ ± 5 %, VBAT = 16 to 36 Full 0.95 VBAT See Test Circuit TX = 0 V 1.2 V Full 9.6 µs Full 110 Ω Full 20 pF VIH Full VHYS Full IIH RXL and RXK Output Low Voltage VOLR RXL and RXK Pull-up Resistance RRX TX = 4 0.65 VBAT V 0.05 VBAT VIH= VBAT Full 20 µA VILK, VILL = 0.35 VBAT IOLR = 1 mA Full 0.4 V 20 kΩ Full 5 RL = 510 Ω ± 5 %, VBAT = 6 V to 18 V CL = 10 nF, See Test Circuit Full 3 10 RL = 1 kΩ ± 5 %, VBAT = 16 V to 36 V CL = 4.7 nF, See Test Circuit Full 3 10 RL = 510 Ω ± 5 %, VBAT = 6 V to 18 V CL = 10 nF, See Test Circuit Full 3 10 RL = 1 kΩ ± 5 %, VBAT = 16 V to 36 V CL = 4.7 nF, See Test Circuit Full 3 10 IBAT(on) TX = 0 V, VBAT ≤ 16 V Full 1.2 3 Bat Supply Current Off IBAT(off) VIHT ≤ VTX, VIHK ≤ VK, VIHL≤ VL VBAT ≤ 12 V Full 120 220 Bat Supply Current Standby IBAT(SB) VDD ≤ 0.5 V, VBAT ≤ 12 V Full
SI9243AEY-T1-E3 价格&库存

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