SIHB33N60EF-GE3

SiHB33N60EF www.vishay.com Vishay Siliconix EF Series Power MOSFET with Fast Body Diode FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Fast body diode MOSFET using E series technology • Reduced trr, Qrr, and IRRM • Low figure-of-merit (FOM): Ron x Qg • Low input capacitance (Ciss) • Reduced switching and conduction losses • Ultra low gate charge (Qg) • Avalanche energy rated (UIS) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 650 RDS(on) max. at 25 °C () VGS = 10 V 0.098 Qg (Max.) (nC) 155 Qgs (nC) 22 Qgd (nC) 43 Configuration Single D D2PAK (TO-263) APPLICATIONS • Telecommunications - Server and telecom power supplies • Lighting - High-intensity discharge (HID) - Light emitting diodes (LEDs) • Consumer and computing - ATX power supplies • Industrial - Welding - Battery chargers • Renewable energy - Solar (PV inverters) • Switch mode power suppliers (SMPS) • Applications using the following topologies - LLC - Phase shifted bridge (ZVS) - 3-level inverter - AC/DC bridge G G D S S N-Channel MOSFET ORDERING INFORMATION Package D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHB33N60EF-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current (Typical) a ID IDM Linear Derating Factor Single Pulse Avalanche Energy b Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dt d Soldering Recommendations (Peak Temperature) c for 10 s UNIT V 33 21 A 100 2.2 W/°C EAS 691 mJ PD 278 W TJ, Tstg -55 to +150 °C dV/dt 70 50 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 7 A. c. 1.6 mm from case. d. ISD  ID, dI/dt = 900 A/μs, starting TJ = 25 °C. S17-0295-Rev. C, 27-Feb-17 Document Number: 91593 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB33N60EF www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 0.45 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance a VDS VGS = 0 V, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.72 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA μA IGSS IDSS RDS(on) gfs VGS = ± 30 V - - ±1 VDS = 480 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 500 - 0.085 0.098  - 12 - S VGS = 10 V ID = 16.5 A VDS = 30 V, ID = 16.5 A μA Dynamic Input Capacitance Ciss VGS = 0 V, - 3454 - Output Capacitance Coss VDS = 100 V, - 154 - Reverse Transfer Capacitance Crss f = 1 MHz - 8 - Effective Output Capacitance, Energy Related b Co(er) - 121 - Effective Output Capacitance, Time Related c Co(tr) - 437 - - 103 155 - 22 - - 43 - - 28 56 pF VGS = 0 V, VDS = 0 V to 480 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 16.5 A, VDS = 480 V nC VDD = 480 V, ID = 16.5 A Rg = 9.1 , VGS = 10 V - 43 86 - 161 242 - 48 96 f = 1 MHz, open drain 0.2 0.5 1.0 - - 33 S - 100 - TJ = 25 °C, IS = 16.5 A, VGS = 0 V - 0.9 1.2 V - 162 324 ns - 1.0 2.0 μC - 13 - A ns  Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IF = IS = 16.5 A, dI/dt = 100 A/μs, VR = 400 V Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS. c. Coss(tr) is a fixed capacitance that gives the charging time as Coss while VDS is rising from 0 % to 80 % VDS. S17-0295-Rev. C, 27-Feb-17 Document Number: 91593 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB33N60EF www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 120 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 80 ID = 16.5 A RDS(on), Drain-to-Source On-Resistance (Normalized) ID, Drain-to-Source Current (A) 100 TJ = 25 °C 60 40 20 2.5 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 0 5 10 15 20 25 - 60 - 40 - 20 30 80 40 60 80 100 120 140 160 10 000 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V TJ = 150 °C Ciss VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd 1000 C, Capacitance (pF) ID, Drain-to-Source Current (A) 20 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 60 0 TJ, Junction Temperature (°C) VDS, Drain-to-Source Voltage (V) 40 20 Coss 100 Crss 10 0 1 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 30 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 25 120 5000 80 60 TJ = 150 °C 15 Eoss Coss 500 10 Eoss (μJ) 20 Coss (pF) ID, Drain-to-Source Current (A) 100 40 5 20 VDS = 26.4 V 50 0 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S17-0295-Rev. C, 27-Feb-17 25 0 0 100 200 300 VDS 400 500 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 91593 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB33N60EF www.vishay.com Vishay Siliconix 40 VDS = 480 V VDS = 300 V VDS = 120 V 20 30 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 20 10 4 0 0 0 40 80 120 160 Qg, Total Gate Charge (nC) 200 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 750 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 100 TJ = 150 °C 10 TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-Drain Voltage (V) 1.4 1.6 Fig. 8 - Typical Source-Drain Diode Forward Voltage Operation in this Area Limited by RDS(on) ID, Drain Current (A) 100 725 700 675 650 625 600 575 ID = 250 μA 550 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature IDM Typical 10 Limited by RDS(on)* 100 μs 1 1 ms TC = 25 °C TJ = 150 °C Single Pulse 10 ms BVDSS Limited 0.1 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S17-0295-Rev. C, 27-Feb-17 Document Number: 91593 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB33N60EF www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS 10 % VGS QGD VG td(on) td(off) tf tr Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L Vary tp to obtain required IAS VDS 50 kΩ D.U.T RG 12 V + - IAS 0.2 µF 0.3 µF V DD + D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S17-0295-Rev. C, 27-Feb-17 Document Number: 91593 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB33N60EF www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel           Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91593. S17-0295-Rev. C, 27-Feb-17 Document Number: 91593 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000