SIHF22N60S-E3

SiHF22N60S www.vishay.com Vishay Siliconix S Series Power MOSFET FEATURES PRODUCT SUMMARY VDS at TJ max. (V) • Generation one 650 RDS(on) max. at 25 °C (Ω) VGS = 10 V • High EAR capability 0.190 Qg max. (nC) 98 • Lower figure-of-merit Ron x Qg Qgs (nC) 17 • 100 % avalanche tested 25 • Ultra low Ron Qgd (nC) Configuration Single Available • dV/dt ruggedness • Ultra low gate charge (Qg) D TO-220 FULLPAK • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. G APPLICATIONS S G D S • PFC power supply stages N-Channel MOSFET • Hard switching topologies • Solar inverters • UPS • Motor control • Lighting • Server telecom ORDERING INFORMATION Package TO-220 FULLPAK Lead (Pb)-free SiHF22N60S-E3 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current a VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current b ID 13 65 Single Pulse Avalanche Energy c EAS 690 Repetitive Avalanche Energy b EAR 25 PD 250 2 Maximum Power Dissipation Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dt e Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) d dV/dt TJ, Tstg for 10 s V 22 IDM Linear Derating Factor UNIT 37 5.3 -55 to +150 300 A W/°C mJ W V/ns °C Notes a. Limited by maximum junction temperature. b. Repetitive rating; pulse width limited by maximum junction temperature. c. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A. d. 1.6 mm from case. e. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S15-0982-Rev. E, 27-Apr-15 Document Number: 91394 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF22N60S www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.4 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current VDS VGS = 0 V, ID = 1 mA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.70 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA μA IGSS IDSS VGS = ± 30 V - - ±1 VDS = 600 V, VGS = 0 V - - 5 VDS = 600 V, VGS = 0 V, TJ = 150 °C - - 100 μA - 0.160 0.190 Ω gfs VDS = 50 V, ID = 13 A - 9.4 - S Input Capacitance Ciss 2810 - Coss - 1480 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 25 V, f = 1.0 MHz - Output Capacitance - 33 - Effective Output Capacitance (Time Related) Coss eff. (TR)a 155 - Drain-Source On-State Resistance Forward Transconductance a RDS(on) VGS = 10 V ID = 11 A Dynamic VGS = 0 V VDS = 0 V to 480 V - 75 110 VGS = 10 V ID = 22 A, VDS = 480 V - 17 - Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - 25 - Turn-On Delay Time td(on) - 24 50 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VDD = 380 V, ID = 22 A, Rg = 9.1 Ω, VGS = 10 V - 68 100 - 77 115 - 59 90 f = 1 MHz, open drain - 0.65 - - - 22 - - 88 pF nC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 22 A, VGS = 0 V TJ = 25 °C, IF = IS, dI/dt = 100 A/μs, VR = 25 V S - - 1.2 V - 462 690 ns - 8.3 16 μC - 30 60 A Note a. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. S15-0982-Rev. E, 27-Apr-15 Document Number: 91394 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF22N60S www.vishay.com Vishay Siliconix ID, Drain Current (A) 50 VGS Top 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V 5V Bottom 4 V 40 30 20 10 TJ = 25 °C 4V 0 0 4 8 12 16 20 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 24 3.5 ID = 22 A VGS = 10 V 3 2.5 2 1.5 1 0.5 0 - 60 - 40 - 20 0 VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, TJ = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature 100 000 VGS Top 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V 5V Bottom 4 V 18 12 Capacitance (pF) ID, Drain Current (A) 30 24 Ciss 1000 Crss TJ = 150 °C 4 .0 V 10 0 4 8 12 16 20 24 1 10 Fig. 2 - Typical Output Characteristics, TJ = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 60 12.0 VGS, Gate-to-Source Voltage (V) ID, Drain Current (A) TJ = 25 °C 50 40 30 20 TJ = 150 °C 10 0 4 6 8 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S15-0982-Rev. E, 27-Apr-15 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) 2 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd • Cds shorted Crss = Cgd Coss = Cds + Cgd Coss 10 000 100 6 0 20 40 60 80 100 120 140 160 180 TJ, Junction Temperature (°C) 10 ID = 22 A 10.0 VDS = 480 V VDS = 300 V VDS = 120 V 8.0 6.0 4.0 2.0 0.0 0 10 20 30 40 50 60 70 80 90 100 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91394 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF22N60S www.vishay.com Vishay Siliconix 25 100 20 10 ID, Drain Current (A) ISD, Reverse Drain Current (A) 1000 TJ = 150 °C TJ = 25 °C 1 0.1 0.01 15 10 5 0.001 VGS = 0 V 0.0001 0.2 0.4 0.6 0.8 1 1.2 0 25 1.4 VSD, Source-to-Drain Voltage (V) 75 100 125 150 TC, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature 725 VDS, Drain-to-Source Breakdown Voltage (V) 1000 ID, Drain Current (A) 50 Operation in this area limited by RDS(on) 100 10 100 µs 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 0.1 1 10 ms 10 100 1000 700 675 650 625 600 575 550 - 60 - 40 - 20 0 10 000 VDS, Drain-to-Source Voltage (V) 20 40 60 80 100 120 140 160 180 TJ, Junction Temperature (°C) Fig. 8 - Maximum Safe Operating Area Fig. 10 - Drain-to-Source Breakdown Voltage Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 10-4 Single Pulse 10-3 10-2 0.1 1 10 Square Wave Pulse Duration (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S15-0982-Rev. E, 27-Apr-15 Document Number: 91394 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF22N60S www.vishay.com Vishay Siliconix RD VDS QG VGS VGS D.U.T. Rg QGS + - VDD QGD VG 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 12 - Switching Time Test Circuit Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS 90 % 50 kΩ 12 V 0.2 µF 0.3 µF 10 % VGS + D.U.T. td(on) - VDS td(off) tf tr VGS Fig. 13 - Switching Time Waveforms 3 mA IG ID Current sampling resistors L Vary tp to obtain required IAS VDS Fig. 17 - Gate Charge Test Circuit D.U.T Rg + - I AS V DD 10 V 0.01 Ω tp Fig. 14 - Unclamped Inductive Test Circuit VDS tp VDD VDS IAS Fig. 15 - Unclamped Inductive Waveforms S15-0982-Rev. E, 27-Apr-15 Document Number: 91394 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHF22N60S www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91394. S15-0982-Rev. E, 27-Apr-15 Document Number: 91394 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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