IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
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Vishay Siliconix
Power MOSFET
FEATURES
S
DPAK
(TO-252)
•
•
•
•
•
•
•
IPAK
(TO-251)
G
D
D
G
S
G
D S
D
P-Channel MOSFET
DESCRIPTION
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface-mount applications.
PRODUCT SUMMARY
VDS (V)
-400
RDS(on) (Ω)
VGS = -10 V
7.0
Qg (Max.) (nC)
13
Qgs (nC)
3.2
Qgd (nC)
5.0
Configuration
Advanced process technology
Fully avalanche rated
Surface-mount (IRFR9310, SiHFR9310)
Straight lead (IRFU9310, SiHFU9310)
P-channel
Available
Fast switching
Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
Single
ORDERING INFORMATION
Package
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
Lead (Pb)-free and
halogen-free
SiHFR9310-GE3
SiHFR9310TRL-GE3
SiHFR9310TR-GE3
SiHFR9310TRR-GE3
SiHFU9310-GE3
-
IRFR9310TRLPbF-BE3
-
-
-
Lead (Pb)-free
IRFR9310PbF
IRFR9310TRLPbFa
IRFR9310TRPbFa
IRFR9310TRRPbFa
IRFU9310PbF
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
400
Gate-source voltage
VGS
± 20
Continuous drain current
VGS at -10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
UNIT
V
-1.8
-1.1
A
-7.2
0.40
W/°C
Single pulse avalanche energy b
EAS
92
mJ
Repetitive avalanche current a
IAR
-1.8
A
Repetitive avalanche energy a
EAR
5.0
mJ
Maximum power dissipation
TC = 25 °C
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
For 10 s
PD
50
W
dV/dt
-24
V/ns
TJ, Tstg
-55 to +150
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 57 mH, Rg = 25 Ω, IAS = - 1.8 A (see fig. 12)
c. ISD ≤ - 1.1 A, dI/dt ≤ 450 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91284
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum junction-to-ambient
PARAMETER
RthJA
-
-
110
Maximum junction-to-ambient
(PCB mount) a
RthJA
-
-
50
Maximum junction-to-case (drain)
RthJC
-
-
2.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VDS
VGS = 0 V, ID = - 250 μA
- 400
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.41
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 μA
- 2.0
-
- 4.0
V
Gate-source leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = - 400 V, VGS = 0 V
-
-
- 100
VDS = - 320 V, VGS = 0 V, TJ = 125 °C
-
-
- 500
μA
-
-
7.0
Ω
gfs
VDS = - 50 V, ID = - 1.1 A
0.91
-
-
S
Input capacitance
Ciss
270
-
Coss
-
50
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
-
Output capacitance
-
8.0
-
-
-
13
-
-
3.2
Drain-source on-state resistance
Forward transconductance
RDS(on)
ID = - 1.1 Ab
VGS = - 10 V
Dynamic
pF
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Qgd
-
-
5.0
Turn-on delay time
td(on)
-
11
-
tr
-
10
-
-
25
-
-
24
-
-
4.5
-
-
7.5
-
-
-
- 1.9
S
-
-
- 7.6
TJ = 25 °C, IS = - 1.1 A, VGS = 0 Vb
-
-
- 4.0
V
-
170
260
ns
-
640
960
nC
Rise time
Turn-off delay time
Fall time
td(off)
VGS = - 10 V
ID = - 1.1 A, VDS = - 320 V,
see fig. 6 and 13b
VDD = - 200 V, ID = - 1.1 A,
Rg = 21 Ω, RD = 180 Ω, see fig. 10b
tf
Internal drain inductance
LD
Internal source inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contactc
D
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current a
ISM
Body diode voltage
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = -1.1 A, dI/dt = 100 A/μsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. This is applied for IPAK, LS of DPAK is measured between lead and center of die contact
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91284
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
-I D , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
TOP
1
-4.5V
20μs PULSE WIDTH
TJ = 25 °C
0.1
1
10
100
TJ = 25 ° C
TJ = 150 ° C
1
V DS = -50V
20μs PULSE WIDTH
0.1
4
-VDS , Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
2.5
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
-I D , Drain-to-Source Current (A)
TOP
1
-4.5V
0.1
20μs PULSE WIDTH
TJ = 150 °C
1
10
-VDS , Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
S21-0373-Rev. E, 19-Apr-2021
6
7
8
9
10
Fig. 2 - Typical Transfer Characteristics
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
10
5
-VGS, Gate-to-Source Voltage (V)
ID = -1.8A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = -10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 3 - Normalized On-Resistance vs. Temperature
Document Number: 91284
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
400
Ciss
300
200
Coss
100
Crss
10
-ISD , Reverse Drain Current (A)
500
Vishay Siliconix
0
1
10
TJ = 150 ° C
1
TJ = 25 ° C
0.1
1.0
100
-VDS , Drain-to-Source Voltage (V)
3.0
4.0
5.0
Fig. 6 - Typical Source-Drain Diode Forward Voltage
100
ID = -1.1A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS =-320V
VDS =-200V
VDS =-80V
16
-IID , Drain Current (A)
-VGS , Gate-to-Source Voltage (V)
2.0
-VSD ,Source-to-Drain Voltage (V)
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
20
V GS = 0 V
12
8
10
10us
100us
1
1ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
4
8
12
16
QG , Total Gate Charge (nC)
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0373-Rev. E, 19-Apr-2021
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
10
10ms
100
1000
-VDS , Drain-to-Source Voltage (V)
Fig. 7 - Maximum Safe Operating Area
Document Number: 91284
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www.vishay.com
Vishay Siliconix
RD
VDS
2.0
VGS
1.6
-ID , Drain Current (A)
D.U.T.
Rg
+VDD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1.2
Fig. 10a - Switching Time Test Circuit
0.8
td(on)
0.4
td(off) tf
tr
VGS
10 %
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
90 %
VDS
Fig. 8 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
0.01
0.01
0.00001
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 9 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91284
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
L
VDS
IAS
Rg
+ VDD
A
D.U.T.
IAS
- 20 V
tp
Driver
0.01 Ω
tp
15 V
VDS
Fig. 12b - Unclamped Inductive Waveforms
EAS , Single Pulse Avalanche Energy (mJ)
Fig. 12a - Unclamped Inductive Test Circuit
300
ID
-0.49A
-0.7A
BOTTOM -1.1A
TOP
250
200
150
100
50
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0373-Rev. E, 19-Apr-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91284
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IRFR9310, IRFU9310, SiHFR9310, SiHFU9310
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
• dV/dt controlled by Rg
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Note
• Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
Fig. 10 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91284.
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91284
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
TO-252AA Case Outline
VERSION 1: FACILITY CODE = Y
E
A
C2
H
D
D1
L3
b3
e
b2
e1
L
gage plane height (0.5 mm)
L4
b
L5
E1
C
A1
MILLIMETERS
DIM.
MIN.
A
2.18
MAX.
2.38
A1
-
0.127
b
0.64
0.88
b2
0.76
1.14
b3
4.95
5.46
C
0.46
0.61
C2
0.46
0.89
D
5.97
6.22
D1
4.10
-
E
6.35
6.73
E1
4.32
-
H
9.40
10.41
e
2.28 BSC
e1
4.56 BSC
L
1.40
1.78
L3
0.89
1.27
L4
-
1.02
L5
1.01
1.52
Note
• Dimension L3 is for reference only
Revision: 16-Dec-2019
Document Number: 71197
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
VERSION 2: FACILITY CODE = N
E
e
A
b3
E1
E1/2
c2
θ
e
L4
L5
L6
H
D
L3
D1
θ
0.25
(3°)
DETAIL "B"
C A B
(3°)
DETAIL "B"
A1
C
L
(L1)
b1
SEATING
C
PLANE
θ
L2
GAUGE
PLANE
H
C
(b)
c1
3x b
2x e
c
2x b2
MILLIMETERS
MILLIMETERS
DIM.
A
MIN.
2.18
MAX.
DIM.
MIN.
2.39
L
1.50
A1
-
0.13
L1
b
0.65
0.89
L2
MAX.
1.78
2.74 ref.
0.51 BSC
b1
0.64
0.79
L3
b2
0.76
1.13
L4
-
1.02
b3
4.95
5.46
L5
1.14
1.49
c
0.46
0.61
L6
0.65
0.85
c1
0.41
0.56
0°
10°
1
0°
15°
2
25°
35°
c2
0.46
0.60
D
5.97
6.22
D1
5.21
-
E
6.35
6.73
E1
4.32
e
H
2.29 BSC
9.94
0.89
1.27
Notes
• Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
• Heat sink side flash is max. 0.8 mm
• Radius on terminal is optional
10.34
ECN: E19-0649-Rev. Q, 16-Dec-2019
DWG: 5347
Revision: 16-Dec-2019
Document Number: 71197
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
Case Outline for TO-251AA (High Voltage)
OPTION 1:
4
E1
3
E
Thermal PAD
4
b4
θ2
4
A
0.010 0.25 M C A B
L2 4
c2
A
θ1
B
D
D1
A
C
3
Seating
plane
5
C
L1 L3
(Datum A)
C
L
B
B
A
A1
3 x b2
View A - A
2xe
c
3xb
0.010 0.25 M C A B
Plating
5
b1, b3
Base
metal
Lead tip
5
c1
(c)
(b, b2)
Section B - B and C - C
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
2.18
2.39
0.086
0.094
D1
5.21
-
0.205
-
A1
0.89
1.14
0.035
0.045
E
6.35
6.73
0.250
0.265
b
0.64
0.89
0.025
0.035
E1
4.32
-
0.170
-
2.29 BSC
MAX.
b1
0.65
0.79
0.026
0.031
e
b2
0.76
1.14
0.030
0.045
L
8.89
9.65
0.350
2.29 BSC
0.380
b3
0.76
1.04
0.030
0.041
L1
1.91
2.29
0.075
0.090
b4
4.95
5.46
0.195
0.215
L2
0.89
1.27
0.035
0.050
0.060
c
0.46
0.61
0.018
0.024
L3
1.14
1.52
0.045
c1
0.41
0.56
0.016
0.022
θ1
0'
15'
0'
15'
c2
0.46
0.86
0.018
0.034
θ2
25'
35'
25'
35'
D
5.97
6.22
0.235
0.245
ECN: E21-0605-Rev. B, 25-Oct-2021
DWG: 5968
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension are shown in inches and millimeters
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
• Thermal pad contour optional with dimensions b4, L2, E1 and D1
• Lead dimension uncontrolled in L3
• Dimension b1, b3 and c1 apply to base metal only
• Outline conforms to JEDEC® outline TO-251AA
Document Number: 91362
1
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 25-Oct-2021
Package Information
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Vishay Siliconix
OPTION 2: FACILITY CODE = N
E
A
L2
b4
c2
E1
D2
θ1
CL
L4
θ1
D
D1
Ø 1.00
x 0.10 deep
C
B
B
L
L3
L1
C
b2
A1
b
b1, b3
c
c
e
c1
θ2
Third angle
projection
b, b2
Section “B-B” and “C-C”
DIM.
MIN.
NOM.
MAX.
DIM.
MIN.
NOM.
A
2.180
2.285
2.390
D2
5.380
-
MAX.
-
A1
0.890
1.015
1.140
E
6.350
6.540
6.730
b
0.640
0.765
0.890
E1
4.32
-
-
b1
0.640
0.715
0.790
e
b2
0.760
0.950
1.140
L
8.890
2.29 BSC
9.270
9.650
b3
0.760
0.900
1.040
L1
1.910
2.100
2.290
b4
4.950
5.205
5.460
L2
0.890
1.080
1.270
c
0.460
-
0.610
L3
1.140
1.330
1.520
c1
0.410
-
0.560
L4
1.300
1.400
1.500
c2
0.460
-
0.610
θ1
0°
7.5°
15°
D
5.970
6.095
6.220
θ2
4°
-
-
D1
4.300
-
-
ECN: E21-0605-Rev. B, 25-Oct-2021
DWG: 5968
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• All dimension are in millimeters, angles are in degrees
• Heat sink side flash is max. 0.8 mm
Document Number: 91362
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 25-Oct-2021
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
www.vishay.com
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