VBUS03B1-SD0-G4-08

VBUS03B1-SD0 www.vishay.com Vishay Semiconductors Ultra Low Capacitance Bidirectional Symmetrical (BiSy) Single Line ESD Protection Diode in Silicon Package FEATURES 0.27 • Ultra compact CLP0603 package • Low package height < 0.3 mm • 1-line ESD protection • Working range ± 3.3 V 22543 0.6 0.3 22544 • Ultra low load capacitance CD = 0.29 pF typ. • ESD immunity acc. IEC 61000-4-2 ± 16 kV contact discharge ± 16 kV air discharge MARKING (example only) 1 • Low leakage current < 0.05 μA XY • Lead plating: Au (e4) • Lead material: Ni 22454 • Backside coating 1 = year code Open circle = month code and pin 1 XY = type code • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912     DESIGN SUPPORT TOOLS AVAILABLE 3D 3D 3D Models ORDERING INFORMATION ENVIRONMENTAL AND QUALITY CODE PART NUMBER (EXAMPLE) RoHS-COMPLIANT + LEAD (Pb)-FREE TERMINATIONS GOLD PLATED 15K PER 7" REEL (8 mm TAPE) 15K/BOX = MOQ ORDERING CODE (EXAMPLE) 4 -08 VBUS03B1-SD0-G4-08 GREEN VBUS03B1-SD0- PACKAGING CODE G PACKAGE DATA DEVICE NAME VBUS03B1-SD0 PACKAGE NAME TYPE CODE CLP0603-2L 3B WEIGHT SOLDERING CONDITIONS 0.12 mg Peak temperature max. 260 °C Reflow soldering according JEDEC® STD-020 ABSOLUTE MAXIMUM RATINGS PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current acc. IEC 61000-4-5, 8/20 μs/single shot IPPM 2.5 A Peak pulse power Pin 1 to pin 2 acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 45 W ESD immunity Operating temperature Storage temperature Rev. 1.7, 17-May-2019 Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature VESD ± 16 ± 16 kV TJ -55 to +150 °C Tstg -55 to +150 °C Document Number: 85908 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS03B1-SD0 www.vishay.com Vishay Semiconductors ESD PROTECTION FOR HIGH-SPEED SIGNAL OR DATA LINES The VBUS03B1-SD0 is a Bidirectional and Symmetrical (BiSy) ESD protection device which clamps positive and negative overvoltage transients to ground. Connected between the signal or data line and the ground the VBUS03B1-SD0 offers a high isolation (low leakage current, low capacitance) within the specified working range. Due to the short leads and small package size of the tiny CLP0603 package the line inductance is very low, so that fast transients like and ESD strike can be clamped with minimal over- or undershoots. Due to the very low capacitance the VBUS03B1-SD0 can be used for high speed data ports like HDMI, USB 3.0 or Thunderbolt. ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. Number of lines which can be protected Nchannel - Max. reverse working voltage VRWM - Reverse voltage at IR = 0.05 μA VR 3.3 - - V Reverse current at VRWM = 3.3 V IR - < 0.0009 (1) 0.05 μA at IR = 1 mA VBR 6.0 8.5 10 V at IPP = 1 A VC - 12 14 V Protection paths Reverse stand-off voltage Reverse breakdown voltage Reverse clamping voltage Capacitance Clamping voltage Dynamic resistance MAX. UNIT - 1 lines - 3.3 V at IPP = IPPM = 2.5 A VC - 15 18 V at VR = 0 V; f = 1 MHz CD - 0.29 0.4 pF at VR = 3.3 V; f = 1 MHz CD - 0.29 - pF - 20 - - 29 - - 1.14 - Transmission Line Pulse (TLP); tp = 100 ns ITLP = 8 A Transmission Line Pulse (TLP); tp = 100 ns ITLP = 16 A Transmission Line Pulse (TLP); tp = 100 ns V VC-TLP RDYN  Note (1) Defined by design. Such a low leakage current is too low for a 100 % final test verification Rev. 1.7, 17-May-2019 Document Number: 85908 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS03B1-SD0 www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Axis Title 10000 120 18 Rise time = 0.7 ns to 1 ns 16 100 14 1000 60 53 40 VC in V 12 1st line 2nd line 2nd line IESD (%) 80 100 10 8 6 27 4 20 Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 2 0 10 -10 0 0 10 20 30 40 50 60 70 80 90 100 0 t (ns) 2nd line 20557 1 2 3 4 IPP in A 22750 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Fig. 4 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Axis Title 45 10000 100 Transmission Line Pulse (TLP) tp = 100 ns (Average between 55 ns and 95 ns) 40 8 µs to 100 % 35 80 30 20 µs to 50 % 40 VC in V 60 1st line 2nd line 2nd line IPPM (%) 1000 25 20 15 100 10 20 5 0 0 10 20 30 0 40 5 10 22755 t (µs) 2nd line 20548 VC = 1.14 V/A x Ipp + 10 V 0 10 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 15 20 25 IPP in A Fig. 5 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP 10 0 9 5 8 2nd line Insertion Loss 7 VR in (V) 6 5 4 3 2 10 15 20 25 1 IL = 20 x log10 (/S11/) [dB] 0 1E-09 1E-08 1E-07 1E-06 22749 30 1E-05 1E-04 1E-03 IR in A Fig. 3 - Typical Reverse Voltage VR vs. Reverse Current IR Rev. 1.7, 17-May-2019 1 22939 10 100 1000 10000 f (MHz) 2nd 2ndline line Fig. 6 - Typical Insertion Loss (IL) vs. Frequency Document Number: 85908 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS03B1-SD0 www.vishay.com Vishay Semiconductors PACKAGE DIMENSIONS in millimeters (mils): CLP0603-2L A2 e1 Package = chip dimensions in mm [mils] b D L A1 e Millimeters nom. max. min. nom. max. A 0.25 0.28 0.30 9.84 11.02 11.81 A1 0.01 0.01 0.02 0.39 0.39 0.79 A2 0.24 0.27 0.28 9.45 10.63 11.02 b 0.22 0.25 0.28 8.66 9.84 11.02 D 0.27 0.30 0.33 10.62 11.81 12.99 E 0.57 0.60 0.63 22.44 23.62 24.80 A C E mils min. e 0.40 15.75 e1 0.25 9.84 L 0.12 0.15 0.18 4.72 5.91 7.09 22941 2 terminal leadless package (CLP) Document no.: S8-V-3906.04-023 (4) Created - Date: 22. Nov. 2010 Rev.8 - Date: 11. Nov. 2016  Footprint and soldering recommendation: please see Application Note: www.vishay.com/doc?85917 Rev. 1.7, 17-May-2019 Document Number: 85908 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS03B1-SD0 www.vishay.com Vishay Semiconductors CARRIER TAPE in millimeters: CLP0603-2L A-A 0.67±0.03 max . 2° Ø 0.2 ± 0.05 0.2 ± 0.02 + 0.3 4 ± 0.1 8 - 0.1 A 3.5 ± 0.05 Ø 1.55 ± 0.05 Section 1.75 ± 0.1 2 ± 0.05 B B A B-B 0.33 ± 0.03 Section 5° 0.37± 0.03 Cummulative tolerances of 10 sprocket holes is +/-0.2mm 22591 Document no. S8-V-3906.04-0025 (4) Created - Date: 22. Nov. 2010 ORIENTATION IN CARRIER CLP0603-2L Unreeling direction DETAIL A 50:1 Pin 1 A CLP0603 Top view 22607 Orientation in Carrier Tape (CLP0603) S8-V-3906.04-026 (4) 22.10.2010 Rev. 1.7, 17-May-2019 Document Number: 85908 5 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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