TC74VHCT9125,9126AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT9125AFK
TC74VHCT9126AFK
TC74VHCT9125AFK 5-bit Universal Schmitt Buffer with 3-State Outputs
TC74VHCT9126AFK 5-bit Universal Schmitt Buffer with 3-State Outputs
TC74VHCT9125AFK, TC74VHCT9126AFK
The TC74VHCT9125A/9126A are an ultra-high-speed 5-bit Schmitt buffer
fabricated using silicon-gate CMOS technology.
The TC74VHCT9125A/9126A combines low power consumption of CMOS
with Schottky TTL speeds.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3 V to 5 V
system.
Y1 to Y4 outputs can be put in the high-impedance state by placing a logic
Weight
HIGH on the Enable ( G ) input. The CONT input determines the logical
VSSOP14-P-0030-0.50
: 0.02 g (typ.)
inversion of data.A logic LOW on the CONT input configures the
TC74VHC9125A/9126A as an inverter; a logic HIGH on the CONT input
configures the TC74VHCT9125A/9126A as a buffer.
TC74VHCT9125A Y5 output is an inverting type, and the TC74VHCT9126A Y5 output is a non-inverting type.
All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHC9125A/9126A are
capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the
supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery
back up, etc.
Note: Output in off-state
Features
High speed: tpd = 6.6 ns (typ.) (VCC = 5 V)
Low supply current: ICC = 2 μA (max) (Ta = 25°C)
Compatible with TTL inputs
VIL = 0.5 V (max)
VIH = 2.1 V (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼
− tpHL
Input terminals are at the opposite side of Output terminals
Start of commercial production
2010-07
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Toshiba Electronic Devices & Storage Corporation
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TC74VHCT9125,9126AFK
Pin Assignment
TC74VHCT9125A
TC74VHCT9126A
CONT
1
14
VCC
CONT
1
14
VCC
A1
2
13
Y1
A1
2
13
Y1
A2
3
12
Y2
A2
3
12
Y2
A3
4
11
Y3
A3
4
11
Y3
A4
5
10
Y4
A4
5
10
Y4
A5
6
9
Y5
A5
6
9
Y5
GND
7
8
G
GND
7
8
G
(top view)
(top view)
Truth Table
Inputs
G
Outputs
CONT A1 to 4
Y1 to 4
H
X
X
Z
L
L
L
H
L
L
H
L
L
H
L
L
L
H
H
H
Inputs
Outputs
A5
Y5(9125)
Y5(9126)
L
H
L
H
L
H
X : Don’t care
Z
: High impedance
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Toshiba Electronic Devices & Storage Corporation
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TC74VHCT9125,9126AFK
Absolute Maximum Ratings (Note1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
VCC
−0.5 to 7.0
V
DC input voltage
VIN
−0.5 to 7.0
V
DC output voltage
VOUT
Input diode current
IIK
Output diode current
IOK
DC output current
IOUT
±25
mA
DC VCC/ground current
ICC
±50
mA
Power dissipation
PD
180
mW
Storage temperature
Tstg
−65 to 150
°C
−0.5 to 7.0
(Note 2)
−0.5 to VCC + 0.5
(Note 3)
−20
±20
V
mA
(Note 4)
mA
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant
change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating
conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the
operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated
failure rate, etc).
Note 2: Output in off-state
Note 3: High or low state. IOUT absolute maximum rating must be observed.
Note 4: VOUT < GND, VOUT > VCC
Operating Ranges (Note1)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
4.5 to 5.5
V
Input voltage
VIN
Output voltage
Operating temperature
0 to 5.5
VOUT
Topr
V
0 to 5.5
(Note 2)
0 to VCC
(Note 3)
−40 to 85
V
°C
Note 1: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 2: Output in off-state
Note 3: High or low state.
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TC74VHCT9125,9126AFK
Electrical Characteristics
DC Characteristics
Characteristics
Test Condition
Symbol
Ta =
−40 to 85°C
Ta = 25°C
VCC (V)
Min
Typ
Max
Min
Max
4.5
―
―
1.90
―
1.90
5.5
―
―
2.10
―
2.10
4.5
0.50
―
―
0.50
―
5.5
0.60
―
―
0.60
―
4.5
0.40
―
1.40
0.40
1.40
5.5
0.40
―
1.50
0.40
1.50
IOH = −50 μA
4.5
4.4
4.5
―
4.4
―
IOH = −8 mA
4.5
3.94
―
―
3.80
―
IOL = 50 μA
4.5
―
0.0
0.1
―
0.1
IOL = 8 mA
4.5
―
―
0.36
―
0.44
Positive threshold voltage
VP
―
Negative threshold
voltage
VN
―
Hysteresis voltage
VH
―
Unit
V
V
V
High-level output voltage
VOH
VIN
= VIH or VIL
Low-level output voltage
VOL
VIN
= VIH or VIL
3-state output off-state
current
IOZ
VIN = VIH or VIL
VOUT = VCC or GND
5.5
―
―
±0.25
―
±2.5
μA
Input leakage current
IIN
VIN = 5.5 V or GND
0 to 5.5
―
―
±0.1
―
±1.0
μA
ICC
VIN = VCC or GND
5.5
―
―
2.0
―
20.0
μA
ICCT
Per input: VIN = 3.4 V
Other input: VCC or GND
5.5
―
―
1.35
―
1.50
mA
IOPD
VOUT = 5.5 V
0
―
―
0.5
―
5.0
µA
Quiescent supply current
Output leakage current
(Power-OFF)
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Toshiba Electronic Devices & Storage Corporation
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V
V
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TC74VHCT9125,9126AFK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
VCC (V)
Ta = 25°C
Ta = −40 to 85°C
CL (pF)
Min
Typ.
Max
Min
Max
15
―
6.6
8.5
1.0
10.0
50
―
8.1
11.5
1.0
13.0
15
―
8.0
10.5
1.0
12.0
50
―
9.9
14.5
1.0
17.0
15
―
6.0
8.0
1.0
9.5
50
―
7.9
10.5
1.0
12.0
15
―
6.4
8.5
1.0
10.0
50
―
8.4
12.5
1.0
14.5
Unit
Propagation delay
time
(A1 to 4 - Y1 to 4)
tpLH
tpHL
―
Propagation delay
time
(CONT-Y1 to 4)
tpLH
tpHL
―
Propagation delay
time
(A5 – Y5)
tpLH
tpHL
3-state output enable
time
tpZL
tpZH
RL = 1 kΩ
5.0 ± 0.5
3-state output disable
time
tpLZ
tpHZ
RL = 1 kΩ
5.0 ± 0.5
50
―
6.7
11.5
1.0
13.0
ns
Output to output skew
tosLH
tosHL
5.0 ± 0.5
50
―
―
1.0
―
1.0
ns
Input capacitance
CIN
―
―
4
10
―
10
pF
COUT
―
―
9
―
―
―
pF
―
14
―
―
―
pF
Output capacitance
Power dissipation
capacitance (Note 2)
CPD
―
(Note 1)
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
ns
ns
ns
fIN = 1 MHz
ns
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC / 5 (per bit)
Noise Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
Ta = 25°C
VCC (V)
Typ.
Limit
Unit
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
5.0
0.6
0.8
V
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
5.0
−0.2
−0.8
V
Minimum high level dynamic input
voltage
VIHD
CL = 50 pF
5.0
―
2.1
V
Maximum low level dynamic input
voltage
VILD
CL = 50 pF
5.0
―
0.5
V
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Toshiba Electronic Devices & Storage Corporation
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2019-01-31
TC74VHCT9125,9126AFK
Package Dimensions
Weight: 0.02 g (typ.)
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Toshiba Electronic Devices & Storage Corporation
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2019-01-31
TC74VHCT9125,9126AFK
RESTRICTIONS ON PRODUCT USE
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