TMP89FM42UG(ZHZ)

8 Bit Microcontroller TLCS-870/C1 Series TMP89FM42 © 2009 TOSHIBA CORPORATION All Rights Reserved TMP89FM42 Considerations for Using Both Mask ROM and Flash Products ・ Flash Memory Control Registers Mask ROM products do not contain the flash memory control registers shown in the table below. Therefore, a program that accesses these registers operates differently between mask ROM and flash products. If you use a flash product to check the operation of a program written for a mask ROM product, be sure not to write instructions that access these registers in the program. Register Name Address FLSCR1 0x0FD0 FLSCR2 / FLSCRM 0x0FD1 FLSSTB 0x0FD2 SPCR 0x0FD3 Mask ROM Product Flash Product 89CM42, 89CH42 89FM42, 89FH42 Not available Available ・ Conversion Accuracy of the AD Converter The conversion accuracy of the AD converter differs between mask ROM and flash products, as shown below. When developing your application system, careful consideration must be given to these accuracy differences. (VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85 °C) Parameter Condition Non-linearity error Min Typ. − − VDD = AVDD / VAREF = 5.0 V Zero-point error Max Unit 89CM42 89FM42 89CH42 89FH42 ±4 ±3 − − ±4 ±3 Full-scale error − − ±4 ±3 Total error − − ±4 ±3 VSS = 0.0 V LSB (VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85 °C) Parameter Condition Non-linearity error Min − Typ. − VDD = AVDD / VAREF = 2.7 V Zero-point error Max Unit 89CM42 89FM42 89CH42 89FH42 ±4 ±3 − − ±4 ±3 Full-scale error − − ±4 ±3 Total error − − ±4 ±3 VSS = 0.0 V LSB (VSS = 0.0 V, 2.2 V ≤ VDD < 2.7 V, Topr = −40 to 85 °C) Parameter Condition Non-linearity error Min Typ. Max Unit 89CM42 89FM42 89CH42 89FH42 − − ±5 ±4 − − ±5 ±4 Full-scale error − − ±5 ±4 Total error − − ±5 ±4 VDD = AVDD / VAREF = 2.2 V Zero-point error VSS = 0.0 V LSB TMP89FM42 Precaution for Using the Emulation Chip (Development Tool) ・ Precaution for debugging the voltage detection circuit In debug using the RTE870/C1 In-Circuit Emulator (ICE mode) with the TMP89C900 mounted on it, no interrupt is generated when the supply voltage rises to the detection voltage. Since the #!Undefined!# may operate differently, take account of this difference when debugging programs. For detail, refer to the chapter of Voltage Detection Circuit. Revision History Date Revision 2007/10/25 1 First Release 2007/11/3 2 Contents Revised 2008/2/18 3 Contents Revised 2008/9/2 4 Contents Revised 2009/7/16 5 Contents Revised Table of Contents Considerations for Using Both Mask ROM and Flash Products TMP89FM42 1.1 1.2 1.3 1.4 Features......................................................................................................................................1 Pin Assignment..........................................................................................................................3 Block Diagram...........................................................................................................................4 Pin Names and Functions..........................................................................................................5 2. CPU Core 2.1 2.2 Configuration.............................................................................................................................9 Memory space............................................................................................................................9 2.2.1 Code area.............................................................................................................................................................................9 2.2.1.1 2.2.1.2 2.2.1.3 2.2.2 Data area............................................................................................................................................................................13 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.3 SFR RAM BOOTROM Flash System clock controller...........................................................................................................16 2.3.1 2.3.2 2.3.3 Configuration.....................................................................................................................................................................16 Control...............................................................................................................................................................................16 Functions............................................................................................................................................................................18 2.3.3.1 2.3.3.2 2.3.3.3 2.3.4 2.3.5 Warm-up counter operation when the oscillation is enabled by the hardware Warm-up counter operation when the oscillation is enabled by the software Operation mode control circuit..........................................................................................................................................23 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.6 Clock generator Clock gear Timing generator Warm-up counter...............................................................................................................................................................21 2.3.4.1 2.3.4.2 Single-clock mode Dual-clock mode STOP mode Transition of operation modes Operation Mode Control....................................................................................................................................................28 2.3.6.1 2.3.6.2 2.3.6.3 2.3.6.4 2.4 RAM BOOTROM Flash STOP mode IDLE1/2 and SLEEP1 modes IDLE0 and SLEEP0 modes SLOW mode Reset Control Circuit...............................................................................................................39 2.4.1 2.4.2 2.4.3 2.4.4 Configuration.....................................................................................................................................................................39 Control...............................................................................................................................................................................39 Functions............................................................................................................................................................................41 Reset Signal Generating Factors........................................................................................................................................43 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.5 2.4.4.6 2.4.4.7 Power-on reset External reset input (RESET pin input) Voltage detection reset Watchdog timer reset System clock reset Trimming data reset Flash standby reset i 2.4.4.8 2.4.4.9 2.5 Internal factor reset detection status register How to use the external reset input pin as a port Revision History......................................................................................................................47 3. Interrupt Control Circuit 3.1 3.2 3.3 Configuration...........................................................................................................................51 Interrupt Latches (IL25 to IL3)................................................................................................52 Interrupt Enable Register (EIR)...............................................................................................53 3.3.1 3.3.2 3.4 3.5 Interrupt master enable flag (IMF)....................................................................................................................................53 Individual interrupt enable flags (EF25 to EF4)................................................................................................................53 Maskable Interrupt Priority Change Function.........................................................................56 Interrupt Sequence...................................................................................................................58 3.5.1 3.5.2 3.5.3 Initial Setting......................................................................................................................................................................58 Interrupt acceptance processing.........................................................................................................................................58 Saving/restoring general-purpose registers........................................................................................................................59 3.5.3.1 3.5.3.2 3.5.3.3 3.5.4 3.6 Interrupt return...................................................................................................................................................................61 Software Interrupt (INTSW)....................................................................................................62 3.6.1 3.6.2 3.7 3.8 Using PUSH and POP instructions Using data transfer instructions Using a register bank to save/restore general-purpose registers Address error detection......................................................................................................................................................62 Debugging..........................................................................................................................................................................62 Undefined Instruction Interrupt (INTUNDEF).......................................................................62 Revision History......................................................................................................................63 4. External Interrupt control circuit 4.1 4.2 4.3 Configuration...........................................................................................................................65 Control.....................................................................................................................................65 Function...................................................................................................................................69 4.3.1 4.3.2 4.3.3 Low power consumption function.....................................................................................................................................70 External interrupt 0............................................................................................................................................................70 External interrupts 1/2/3....................................................................................................................................................71 4.3.3.1 4.3.3.2 4.3.3.3 4.3.4 External interrupt 4............................................................................................................................................................72 4.3.4.1 4.3.4.2 4.3.4.3 4.3.5 Interrupt request signal generating condition detection function A noise canceller pass signal monitoring function when interrupt request signals are generated Noise cancel time selection function Interrupt request signal generating condition detection function A noise canceller pass signal monitoring function when interrupt request signals are generated Noise cancel time selection function External interrupt 5............................................................................................................................................................74 5. Watchdog Timer (WDT) 5.1 5.2 5.3 Configuration...........................................................................................................................75 Control.....................................................................................................................................76 Functions..................................................................................................................................78 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 ii Setting of enabling/disabling the watchdog timer operation.............................................................................................78 Setting the clear time of the 8-bit up counter.....................................................................................................................78 Setting the overflow time of the 8-bit up counter..............................................................................................................79 Setting an overflow detection signal of the 8-bit up counter.............................................................................................79 Writing the watchdog timer control codes.........................................................................................................................80 Reading the 8-bit up counter..............................................................................................................................................80 Reading the watchdog timer status....................................................................................................................................80 6. Power-on Reset Circuit 6.1 6.2 Configuration...........................................................................................................................83 Function...................................................................................................................................83 7. Voltage Detection Circuit 7.1 7.2 7.3 Configuration...........................................................................................................................85 Control.....................................................................................................................................86 Function...................................................................................................................................87 7.3.1 7.3.2 7.3.3 7.3.4 7.4 Register Settings......................................................................................................................90 7.4.1 7.4.2 7.5 Enabling/disabling the voltage detection operation...........................................................................................................87 Selecting the voltage detection operation mode................................................................................................................87 Selecting the detection voltage level.................................................................................................................................88 Voltage detection flag and voltage detection status flag...................................................................................................88 Setting procedure when the operation mode is set to generate INTVLTD interrupt request signals................................90 Setting procedure when the operation mode is set to generate voltage detection reset signals.........................................90 Revision History......................................................................................................................92 8. I/O Ports 8.1 8.2 8.3 I/O Port Control Registers.......................................................................................................95 List of I/O Port Settings...........................................................................................................96 I/O Port Registers....................................................................................................................99 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.4 8.5 Port P0 (P03 to P00)..........................................................................................................................................................99 Port P1 (P13 to P10)........................................................................................................................................................103 Port P2 (P27 to P20)........................................................................................................................................................107 Port P4 (P47 to P40)........................................................................................................................................................111 Port P7 (P77 to P70)........................................................................................................................................................114 Port P8 (P81 to P80)........................................................................................................................................................116 Port P9 (P91 to P90)........................................................................................................................................................119 Port PB (PB7 to PB4)......................................................................................................................................................122 Serial Interface Selecting Function........................................................................................125 Revision History....................................................................................................................128 9. Special Function Registers 9.1 9.2 9.3 SFR1 (0x0000 to 0x003F).....................................................................................................129 SFR2 (0x0F00 to 0x0FFF).....................................................................................................130 SFR3 (0x0E40 to 0x0EFF)....................................................................................................132 10. Low Power Consumption Function for Peripherals 10.1 Control.................................................................................................................................136 11. Divider Output (DVO) iii 11.1 11.2 11.3 11.4 Configuration.......................................................................................................................139 Control.................................................................................................................................140 Function...............................................................................................................................141 Revision History..................................................................................................................142 12. Time Base Timer (TBT) 12.1 Time Base Timer.................................................................................................................143 12.1.1 12.1.2 12.1.3 12.2 Configuration.................................................................................................................................................................143 Control...........................................................................................................................................................................143 Functions........................................................................................................................................................................144 Revision History..................................................................................................................146 13. 16-bit Timer Counter (TCA) 13.1 13.2 13.3 13.4 Configuration.......................................................................................................................148 Control.................................................................................................................................149 Low Power Consumption Function.....................................................................................154 Timer Function....................................................................................................................155 13.4.1 Timer mode....................................................................................................................................................................155 13.4.1.1 13.4.1.2 13.4.1.3 13.4.1.4 13.4.2 External trigger timer mode...........................................................................................................................................159 13.4.2.1 13.4.2.2 13.4.2.3 13.4.2.4 13.4.3 13.5.1 13.6 Setting Operation Capture process Programmable pulse generate (PPG) mode...................................................................................................................168 13.4.6.1 13.4.6.2 13.4.6.3 13.5 Setting Operation Auto capture Register buffer configuration Pulse width measurement mode....................................................................................................................................165 13.4.5.1 13.4.5.2 13.4.5.3 13.4.6 Setting Operation Auto capture Register buffer configuration Window mode................................................................................................................................................................163 13.4.4.1 13.4.4.2 13.4.4.3 13.4.4.4 13.4.5 Setting Operation Auto capture Register buffer configuration Event counter mode.......................................................................................................................................................161 13.4.3.1 13.4.3.2 13.4.3.3 13.4.3.4 13.4.4 Setting Operation Auto capture Register buffer configuration Setting Operation Register buffer configuration Noise Canceller....................................................................................................................171 Setting............................................................................................................................................................................171 Revision History..................................................................................................................172 14. 8-bit Timer Counter (TC0) 14.1 14.2 14.2.1 14.2.2 14.2.3 iv Configuration.......................................................................................................................174 Control.................................................................................................................................175 Timer counter 00............................................................................................................................................................175 Timer counter 01............................................................................................................................................................177 Common to timer counters 00 and 01............................................................................................................................179 14.2.4 14.3 14.4 Operation modes and usable source clocks...................................................................................................................181 Low Power Consumption Function.....................................................................................182 Functions..............................................................................................................................183 14.4.1 8-bit timer mode.............................................................................................................................................................183 14.4.1.1 14.4.1.2 14.4.1.3 14.4.2 8-bit event counter mode...............................................................................................................................................186 14.4.2.1 14.4.2.2 14.4.2.3 14.4.3 Setting Operations Double buffer 16-bit programmable pulse generate (PPG) output mode.............................................................................................209 14.4.8.1 14.4.8.2 14.4.8.3 14.5 Setting Operations Double buffer 12-bit pulse width modulation (PWM) output mode.....................................................................................................203 14.4.7.1 14.4.7.2 14.4.7.3 14.4.8 Setting Operations Double buffer 16-bit event counter mode.............................................................................................................................................201 14.4.6.1 14.4.6.2 14.4.6.3 14.4.7 Setting Operation Double buffer 16-bit timer mode...........................................................................................................................................................197 14.4.5.1 14.4.5.2 14.4.5.3 14.4.6 Setting Operations Double buffer 8-bit programmable pulse generate (PPG) output mode...............................................................................................193 14.4.4.1 14.4.4.2 14.4.4.3 14.4.5 Setting Operation Double buffer 8-bit pulse width modulation (PWM) output mode.......................................................................................................188 14.4.3.1 14.4.3.2 14.4.3.3 14.4.4 Setting Operation Double buffer Setting Operations Double buffer Revision History..................................................................................................................213 15. Real Time Clock (RTC) 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.4 15.4.1 15.4.2 Configuration.......................................................................................................................215 Control.................................................................................................................................215 Function...............................................................................................................................216 Low Power Consumption Function...............................................................................................................................216 Enabling/disabling the real time clock operation..........................................................................................................216 Selecting the interrupt generation interval.....................................................................................................................216 Real Time Clock Operation.................................................................................................217 Enabling the real time clock operation..........................................................................................................................217 Disabling the real time clock operation.........................................................................................................................217 16. Asynchronous Serial Interface (UART) 16.1 16.2 16.3 16.4 16.5 16.5.1 16.5.2 16.6 16.7 Configuration.......................................................................................................................220 Control.................................................................................................................................221 Low Power Consumption Function.....................................................................................225 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed .......226 Activation of STOP, IDLE0 or SLEEP0 Mode...................................................................227 Transition of register status............................................................................................................................................227 Transition of TXD pin status.........................................................................................................................................227 Transfer Data Format...........................................................................................................228 Infrared Data Format Transfer Mode..................................................................................228 v 16.8 Transfer Baud Rate..............................................................................................................229 16.8.1 Transfer baud rate calculation method...........................................................................................................................230 16.8.1.1 16.8.1.2 Bit width adjustment using UART0CR2 Calculation of set values of UART0CR2 and UART0DR 16.9 Data Sampling Method........................................................................................................233 16.10 Received Data Noise Rejection.........................................................................................235 16.11 Transmit/Receive Operation..............................................................................................236 16.11.1 16.11.2 16.12 Data transmit operation................................................................................................................................................236 Data receive operation.................................................................................................................................................236 Status Flag.........................................................................................................................237 16.12.1 16.12.2 16.12.3 16.12.4 16.12.5 16.12.6 16.13 16.14 Parity error...................................................................................................................................................................237 Framing Error..............................................................................................................................................................238 Overrun error...............................................................................................................................................................239 Receive Data Buffer Full.............................................................................................................................................242 Transmit busy flag......................................................................................................................................................243 Transmit Buffer Full....................................................................................................................................................243 Receiving Process..............................................................................................................244 AC Properties.....................................................................................................................246 16.14.1 16.15 IrDA properties............................................................................................................................................................246 Revision History................................................................................................................247 17. Synchronous Serial Interface (SIO) 17.1 17.2 17.3 17.4 Configuration.......................................................................................................................250 Control.................................................................................................................................251 Low Power Consumption Function.....................................................................................254 Functions..............................................................................................................................255 17.4.1 17.4.2 17.4.3 17.5 Transfer format..............................................................................................................................................................255 Serial clock....................................................................................................................................................................255 Transfer edge selection..................................................................................................................................................255 Transfer Modes....................................................................................................................257 17.5.1 8-bit transmit mode........................................................................................................................................................257 17.5.1.1 17.5.1.2 17.5.1.3 17.5.1.4 17.5.1.5 17.5.2 8-bit Receive Mode........................................................................................................................................................262 17.5.2.1 17.5.2.2 17.5.2.3 17.5.2.4 17.5.3 Setting Starting the receive operation Operation on completion of reception Stopping the receive operation 8-bit transmit/receive mode...........................................................................................................................................266 17.5.3.1 17.5.3.2 17.5.3.3 17.5.3.4 17.5.3.5 17.6 17.7 Setting Starting the transmit operation Transmit buffer and shift operation Operation on completion of transmission Stopping the transmit operation Setting Starting the transmit/receive operation Transmit buffer and shift operation Operation on completion of transmission/reception Stopping the transmit/receive operation AC Characteristics...............................................................................................................271 Revision History..................................................................................................................272 18. Serial Bus Interface (SBI) 18.1 18.1.1 18.1.2 18.2 18.3 vi Communication Format.......................................................................................................274 I2C bus...........................................................................................................................................................................274 Free data format.............................................................................................................................................................275 Configuration.......................................................................................................................276 Control.................................................................................................................................277 18.4 Functions..............................................................................................................................280 18.4.1 18.4.2 18.4.3 Low Power Consumption Function...............................................................................................................................280 Selecting the slave address match detection and the GENERAL CALL detection.......................................................280 Selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode...... 280 18.4.3.1 18.4.3.2 18.4.4 Serial clock....................................................................................................................................................................282 18.4.4.1 18.4.4.2 18.4.5 18.4.6 18.4.7 18.4.8 18.4.9 18.4.10 18.4.11 18.4.12 18.4.13 18.4.14 18.4.15 18.5 Number of clocks for data transfer Output of an acknowledge signal Clock source Clock synchronization Master/slave selection....................................................................................................................................................284 Transmitter/receiver selection........................................................................................................................................284 Start/stop condition generation......................................................................................................................................284 Interrupt service request and release..............................................................................................................................285 Setting of serial bus interface mode...............................................................................................................................286 Software reset..............................................................................................................................................................286 Arbitration lost detection monitor................................................................................................................................286 Slave address match detection monitor.......................................................................................................................288 GENERAL CALL detection monitor..........................................................................................................................288 Last received bit monitor.............................................................................................................................................289 Slave address and address recognition mode specification.........................................................................................289 Data Transfer of I2C Bus.....................................................................................................290 18.5.1 18.5.2 18.5.3 Device initialization.......................................................................................................................................................290 Start condition and slave address generation.................................................................................................................290 1-word data transfer.......................................................................................................................................................291 18.5.3.1 18.5.3.2 18.5.4 18.5.5 18.6 18.7 When SBI0SR2 is "1" (Master mode) When SBI0SR2 is "0" (Slave mode) Stop condition generation..............................................................................................................................................294 Restart............................................................................................................................................................................295 AC Specifications................................................................................................................297 Revision History..................................................................................................................299 19. Key-on Wakeup (KWU) 19.1 19.2 19.3 Configuration.......................................................................................................................301 Control.................................................................................................................................302 Functions..............................................................................................................................303 20. 10-bit AD Converter (ADC) 20.1 20.2 20.3 20.3.1 20.3.2 20.3.3 20.4 20.5 20.6 20.7 20.7.1 20.7.2 20.7.3 20.8 Configuration.......................................................................................................................305 Control.................................................................................................................................306 Functions.............................................................................................................................310 Single mode...................................................................................................................................................................310 Repeat mode..................................................................................................................................................................310 AD operation disable and forced stop of AD operation................................................................................................311 Register Setting...................................................................................................................312 Starting STOP/IDLE0/SLOW Modes.................................................................................312 Analog Input Voltage and AD Conversion Result..............................................................313 Precautions about the AD Converter...................................................................................314 Analog input pin voltage range......................................................................................................................................314 Analog input pins used as input/output ports.................................................................................................................314 Noise countermeasure....................................................................................................................................................314 Revision History..................................................................................................................315 vii 21. Flash Memory 21.1 21.2 Flash Memory Control.........................................................................................................318 Functions..............................................................................................................................321 21.2.1 21.2.2 21.2.3 21.2.4 21.2.5 21.2.6 21.3 Flash memory command sequence execution and toggle control (FLSCR1 ).............................................321 Flash memory area switching (FLSCR1).....................................................................................................322 RAM area switching (SYSCR3)..................................................................................................................324 BOOTROM area switching (FLSCR1).......................................................................................................324 Flash memory standby control (FLSSTB).......................................................................................................326 Port input control register (SPCR).........................................................................................................327 Command Sequence............................................................................................................328 21.3.1 21.3.2 21.3.3 21.3.4 21.3.5 21.3.6 21.4 21.5 Byte program.................................................................................................................................................................328 Sector erase (4-kbyte partial erase)................................................................................................................................329 Chip erase (all erase)......................................................................................................................................................329 Product ID entry.............................................................................................................................................................330 Product ID exit...............................................................................................................................................................330 Security program............................................................................................................................................................330 Toggle Bit (D6)....................................................................................................................330 Access to the Flash Memory Area.......................................................................................331 21.5.1 Flash memory control in serial PROM mode................................................................................................................331 21.5.1.1 21.5.2 21.5.2.1 21.5.2.2 21.5.2.3 21.5.2.4 21.6 How to transfer and write a control program to the RAM area in RAM loader mode of the serial PROM mode Flash memory control in MCU mode............................................................................................................................334 How to write to the flash memory by transferring a control program to the RAM area How to write to the flash memory by using a support program (API) of BOOTROM How to set the security program by using a support program (API) of BOOTROM How to read data from flash memory API (Application Programming Interface)..........................................................................342 21.6.1 21.6.2 21.6.3 21.6.4 21.6.5 21.6.6 21.7 .BTWrite........................................................................................................................................................................343 .BTEraseSec...................................................................................................................................................................343 .BTEraseChip.................................................................................................................................................................343 .BTGetSP.......................................................................................................................................................................343 .BTSetSP........................................................................................................................................................................343 .BTCalcUART...............................................................................................................................................................344 Revision History..................................................................................................................346 22. Serial PROM Mode 22.1 22.2 22.3 Outline.................................................................................................................................347 Security................................................................................................................................347 Serial PROM Mode Setting.................................................................................................348 22.3.1 22.4 22.5 22.6 Serial PROM mode control pins....................................................................................................................................348 Example Connection for On-board Writing........................................................................350 Activating the Serial PROM Mode......................................................................................351 Interface Specifications.......................................................................................................352 22.6.1 22.6.2 22.7 22.8 SIO communication.......................................................................................................................................................352 UART communication...................................................................................................................................................352 Memory Mapping................................................................................................................354 Operation Commands..........................................................................................................354 22.8.1 Flash memory erase command (0xF0)...........................................................................................................................357 22.8.1.1 22.8.2 22.8.3 22.8.4 22.8.5 22.8.6 22.8.7 22.8.7.1 viii Specifying the erase area Flash memory write command (operation command: 0x30).........................................................................................360 Flash memory read command (operation command: 0x40)..........................................................................................362 RAM loader command (operation command: 0x60).....................................................................................................364 Flash memory SUM output command (operation command: 0x90).............................................................................366 Product ID code output command (operation command: 0xC0)...................................................................................367 Flash memory status output command (0xC3)..............................................................................................................369 Flash memory status code 22.8.8 22.8.9 Mask ROM emulation setting command (0xD0)..........................................................................................................372 Flash memory security setting command (0xFA)..........................................................................................................373 22.9 Error Code...........................................................................................................................374 22.10 Checksum (SUM)..............................................................................................................375 22.10.1 22.10.2 22.11 22.12 Calculation method......................................................................................................................................................375 Calculation data...........................................................................................................................................................375 Intel Hex Format (Binary).................................................................................................376 Security..............................................................................................................................377 22.12.1 Passwords.....................................................................................................................................................................377 22.12.1.1 22.12.1.2 22.12.1.3 22.12.1.4 22.12.2 Security program..........................................................................................................................................................381 22.12.2.1 22.12.2.2 22.12.3 22.12.4 22.13 22.14 How the security program functions Enabling or disabling the security program Option codes................................................................................................................................................................382 Recommended settings................................................................................................................................................384 Flowchart...........................................................................................................................385 AC Characteristics (UART)..............................................................................................386 22.14.1 22.14.2 22.14.3 22.14.4 22.14.5 22.14.6 22.14.7 22.14.8 22.14.9 22.14.10 22.15 How a password can be specified Password structure Password setting, cancellation and authentication Password values and setting range Reset timing.................................................................................................................................................................387 Flash memory erase command (0xF0).........................................................................................................................387 Flash memory write command (0x30).........................................................................................................................388 Flash memory read command (0x40)..........................................................................................................................388 RAM loader command (0x60).....................................................................................................................................389 Flash memory SUM output command (0x90).............................................................................................................389 Product ID code output command (0xC0)...................................................................................................................389 Flash memory status output command (0xC3)............................................................................................................390 Mask ROM emulation setting command (0xD0)........................................................................................................390 Flash memory security setting command (0xFA)......................................................................................................390 Revision History................................................................................................................391 23. On-chip Debug Function (OCD) 23.1 23.2 23.3 23.4 Features................................................................................................................................393 Control Pins.........................................................................................................................393 How to Connect the On-chip Debug Emulator to a Target System....................................395 Security................................................................................................................................395 24. Input/Output Circuit 24.1 Control Pins.........................................................................................................................397 25. Electrical Characteristics 25.1 25.2 25.2.1 25.2.2 25.2.3 25.3 25.4 25.5 25.6 25.7 Absolute Maximum Ratings ...............................................................................................399 Operating Conditions...........................................................................................................400 MCU mode (Flash Programming or erasing)................................................................................................................400 MCU mode (Except Flash Programming or erasing)....................................................................................................401 Serial PROM mode........................................................................................................................................................402 DC Characteristics ..............................................................................................................403 AD Conversion Characteristics ..........................................................................................406 Power-on Reset Circuit Characteristics...............................................................................407 Voltage Detecting Circuit Characteristics...........................................................................408 AC Characteristics...............................................................................................................409 ix 25.7.1 25.7.2 25.7.3 25.8 25.8.1 MCU mode (Flash programming or erasing)................................................................................................................409 MCU mode (Except Flash Programming or erasing)....................................................................................................409 Serial PROM mode........................................................................................................................................................410 Flash Characteristics ...........................................................................................................411 Write characteristics......................................................................................................................................................411 25.9 Oscillating Condition...........................................................................................................412 25.10 Handling Precaution..........................................................................................................413 25.11 Revision History................................................................................................................414 26. Package Dimensions x TMP89FM42 CMOS 8-Bit Microcontroller TMP89FM42 The TMP89FM42 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 32768 bytes of Flash Memory. It is pin-compatible with the TMP89CM42 (Mask ROM version). The TMP89FM42 can realize operations equivalent to those of the TMP89CM42 by programming the on-chip Flash Memory. ROM Product No. (Flash) TMP89FM42UG 32768 bytes RAM Package Mask MCU Emulation Chip 2048 bytes LQFP44-P-1010-0.80B TMP89CM42UG * TMP89C900XBG Note : * ; Under development 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C1 series - Instruction execution time : 100 ns (at 10 MHz) 122 μs (at 32.768 kHz) - 133 types & 732 basic instructions 2. 25 interrupt sources (External : 6 Internal : 19 , Except reset) 3. Input / Output ports (40 pins) Note : Two of above pins can not be used for the I/O port, because they should be connected with the high frequency OSC input. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. - Large current output: 8 pins (Typ. 20mA) Watchdog timer - Interrupt or reset can be selected by the program. Power-on reset circuit Voltage detection circuit Divider output function Time base timer 16-bit timer counter (TCA) : 2 ch - Timer, External trigger, Event Counter, Window, Pulse width measurement, PPG OUTPUT modes 8-bit timer counter (TC0) : 4 ch - Timer, Event Counter, PWM, PPG OUTPUT modes - Usable as a 16-bit timer, 12-bit PWM output and 16-bit PPG output by the cascade connection of two channels. Real time clock UART : 1ch UART/SIO : 1ch Note : One SIO channel can be used at the same time. I2C/SIO : 1ch Key-on wake-up : 8 ch 10-bit successive approximation type AD converter - Analog input : 8ch On-chip debug function - Break/Event This product uses the Super Flash® technology under the licence of Silicon Storage Technology, Inc. Super Flash® is registered trademark of Silicon Storage Technology, Inc. Page 1 RA000 1.1 Features TMP89FM42 - Trace - RAM monitor - Flash memory writing 18. Clock operation mode control circuit : 2 circuit Single clock mode / Dual clock mode 19. Low power consumption operation (8 mode) - STOP mode: - Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: - Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: - Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: - CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Released when the reference time set to TBT has elapsed. IDLE1 mode: - The CPU stops, and peripherals operate using high frequency clock. Release by interruputs(CPU restarts). IDLE2 mode: - CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts). SLEEP0 mode: - CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock. Released when the reference time set to TBT has elapsed. SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts). 20. Wide operation voltage: 4.3 V to 5.5 V at 10MHz /32.768 kHz 2.7 V to 5.5 V at 4.2 MHz /32.768 kHz 2.2 V to 5.5 V at 2MHz /32.768 kHz Page 2 RA000 TMP89FM42 Pin Assignment P90 (TXD1/RXD1) P77 (INT4) P76 (INT3) P75 (INT2) P74 (DVO) P47 (AIN7/KWI7) P46 (AIN6/KWI6) P45 (AIN5/KWI5) P44 (AIN4/KWI4) P43 (AIN3/KWI3) P42 (AIN2/KWI2) 1.2 P41 (AIN1/KWI1) P40 (AIN0/KWI0) VAREF/AVDD P27 P26 P25 (SCLK0) P24 (SCL0/SI0) P23 (SDA0/SO0) P22 (SCLK0) P21 (RXD0/TXD0/SI0/OCDIO) P20 (TXD0/RXD0/SO0/OCDCK) VSS (XIN) P00 (XOUT) P01 MODE VDD (XTIN) P02 (XTOUT) P03 (RESET) P10 (STOP/INT5) P11 (INT0) P12 (INT1) P13 (TXD1/RXD1) P91 (PWM02/PPG02/TC02) P80 (PWM03/PPG03/TC03) P81 (PWM00/PPG00/TC00) P70 (PWM01/PPG01/TC01) P71 (PPGA0/TCA0) P72 (PPGA1/TCA1) P73 (SO0/RXD0/TXD0) PB4 (SI0/TXD0/RXD0) PB5 (SCLK0) PB6 PB7 Figure 1-1 Pin Assignment Page 3 RA000 1.3 Block Diagram 1.3 TMP89FM42 Block Diagram Figure 1-2 Block Diagram Page 4 RA000 TMP89FM42 1.4 Pin Names and Functions The TMP89FM42 has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions (1/3) Pin Name Input/Output Functions P03 IO PORT03 XTOUT O Low frequency OSC output P02 IO PORT02 XTIN I P01 IO PORT01 XOUT O High frequency OSC output P00 IO PORT00 XIN I P13 IO INT1 I P12 IO INT0 I P11 IO INT5 I External interrupt 5 input STOP I STOP mode release input P10 RESET IO I Low frequency OSC input High frequency OSC input PORT13 External interrupt 1 input PORT12 External interrupt 0 input PORT11 PORT10 Reset signal input P27 IO PORT27 P26 IO PORT26 P25 IO PORT25 SCLK0 IO Serial clock input/output 0 P24 IO PORT24 SCL0 IO I2C bus clock input/output 0 SI0 I Serial data input 0 P23 IO PORT23 SDA0 IO I2C bus data input/output 0 SO0 O Serial data output 0 P22 IO PORT22 SCLK0 IO Serial clock input/output 0 P21 IO PORT21 RXD0 I UART data input 0 TXD0 O UART data output 0 SI0 I Serial data input 0 OCDIO IO OCD data input/output P20 IO PORT20 TXD0 O UART data output 0 RXD0 I UART data input 0 SO0 O Serial data output 0 OCDCK I OCD clock input Page 5 RA000 1.4 Pin Names and Functions TMP89FM42 Table 1-2 Pin Names and Functions (2/3) Pin Name Input/Output Functions P47 IO AIN7 I PORT47 Analog input 7 KWI7 I Key-on wake-up input 7 P46 IO AIN6 I PORT46 Analog input 6 KWI6 I Key-on wake-up input 6 P45 IO AIN5 I PORT45 Analog input 5 KWI5 I Key-on wake-up input 5 P44 IO AIN4 I PORT44 Analog input 4 KWI4 I Key-on wake-up input 4 P43 IO AIN3 I PORT43 Analog input 3 KWI3 I Key-on wake-up input 3 P42 IO AIN2 I PORT42 Analog input 2 KWI2 I Key-on wake-up input 2 P41 IO AIN1 I PORT41 Analog input 1 KWI1 I Key-on wake-up input 1 P40 IO AIN0 I PORT40 Analog input 0 KWI0 I Key-on wake-up input 0 P77 IO INT4 I PORT77 P76 IO INT3 I P75 IO INT2 I P74 IO PORT74 DVO O Divider output P73 IO PORT73 External interrupt 4 input PORT76 External interrupt 3 input PORT75 External interrupt 2 input TCA1 I TCA1 input PPGA1 O PPGA1 output P72 IO PORT72 TCA0 I TCA0 input PPGA0 O PPGA0 output P71 IO PORT71 TC01 I TC01 input PPG01 O PPG01 output PWM01 O PWM01 output Page 6 RA000 TMP89FM42 Table 1-2 Pin Names and Functions (3/3) Pin Name P70 Input/Output IO Functions PORT70 TC00 I TC00 input PPG00 O PPG00 output PWM00 O PWM00 output P81 IO PORT81 TC03 I TC03 input PPG03 O PPG03 output PWM03 O PWM03 output P80 IO PORT80 TC02 I TC02 input PPG02 O PPG02 output PWM02 O PWM02 output P91 IO PORT91 RXD1 I UART data input 1 TXD1 O UART data output 1 P90 IO PORT90 TXD1 O UART data output 1 RXD1 I UART data input 1 PB7 IO PORTB7 PB6 IO PORTB6 SCLK0 IO Serial clock input/output 0 PB5 IO PORTB5 RXD0 I UART data input 0 TXD0 O UART data output 0 SI0 I Serial data input 0 PB4 IO PORTB4 TXD0 O UART data output 0 RXD0 I UART data input 0 SO0 O Serial data output 0 MODE I Test pin for out-going test (fix to Low level). VAREF / AVDD I Analog reference voltage input pin for A/D conversion. / Analog power supply pin. VDD I VDD pin VSS I GND pin Page 7 RA000 1.4 Pin Names and Functions TMP89FM42 Page 8 RA000 TMP89FM42 2. CPU Core 2.1 Configuration The CPU core consists of a CPU, a system clock controller and a reset circuit. This chapter describes the CPU core address space, the system clock controller and the reset circuit. 2.2 Memory space The 870/C1 CPU memory space consists of a code area to be accessed as instruction operation codes and operands and a data area to be accessed as sources and destinations of transfer and calculation instructions. Both the code and data areas have independent 64-Kbyte address spaces. 2.2.1 Code area The code area stores operation codes, operands, vector tables for vector call instructions and interrupt vector tables. The RAM, the BOOTROM and the Flash are mapped in the code area. 0x0000 SWI instruction (0xFF) is fetched. 0x003F 0x0040 RAM (2048 bytes) 0x083F SWI instruction (0xFF) is fetched. RAM SWI instruction (0xFF) is fetched. 0x17FF 0x1800 (2048 bytes) SWI instruction (0xFF) is fetched. SWI instruction (0xFF) is fetched. 0x1000 0x7FFF 0x8000 SWI instruction (0xFF) is fetched. BOOTROM BOOTROM (2048 bytes) (2048 bytes) Flash Flash Flash Flash (32768 bytes) (32768 bytes) (32768 bytes) (32768 bytes) 0xFFA0 Vector table for vector call instructions Vector table for vector call instructions Vector table for vector call instructions Vector table for vector call instructions 0xFFBF (32 bytes) (32 bytes) (32 bytes) (32 bytes) Interrupt vector table Interrupt vector table Interrupt vector table Interrupt vector table (52 bytes) (52 bytes) (52 bytes) (52 bytes) Immediately after reset release When the RAM is mapped in the code area When the BOOTROM is mapped in the code area When the RAM and the BOOTROM are mapped in the code area 0xFFCC 0xFFFF Figure 2-1 Memory Map in the Code Area Note:Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Page 9 RB000 2. 2.2 CPU Core Memory space TMP89FM42 2.2.1.1 RAM The RAM is mapped in the data area immediately after reset release. By setting SYSCR3 to "1" and writing 0xD4 to SYSCR4, RAM can be mapped to 0x0040to 0x083F in the code area to execute the program. At this time, by setting SYSCR to "1" and writing 0xD4 to SYSCR4, vector table for vector call instructions and interrupt except reset can be mapped to RAM. In the serial PROM mode, the RAM is mapped to 0x0040 to 0x083F in the code area, regardless of the value of SYSCR3. The program can be executed on the RAM using the RAM loader function. Note 1: When the RAM is not mapped in the code area, the SWI instruction is fetched from 0x0040 to 0x083F. Note2: The contents of the RAM become unstable when the power is turned on and immediately after a reset is released. To execute the program by using the RAM, transfer the program to be executed in the initialization routine. System control register 3 7 6 5 4 3 2 1 0 Bit Symbol - - - - - RVCTR RAREA (RSTDIS) Read/Write R R R R R R/W R/W R/W After reset 0 0 0 0 0 0 0 0 SYSCR3 (0x0FDE) RAREA Specifies mapping of the RAM in the code area RVCTR Specifies mapping of the vector table for vector call instructions and interrupts 0: The RAM is not mapped from 0x0040 to 0x083F in the code area. 1: The RAM is mapped from 0x0040 to 0x083F in the code area. Vector table for vector call instructions Vector table for interrupt 0: 0xFFA0 to 0xFFBF in the code area 0xFFCC to 0xFFFF in the code area 1: 0x01A0 to 0x01BF in the code area 0x01CC to 0x01FD in the code area Note 1: The value of SYSCR3 is invalid until 0xD4 is written into SYSCR4. Note 2: To assign vector address areas to RAM, set SYSCR3 to "1" and SYSCR3 to "1". Note 3: Do not set SYSCR3 to "0" by using the RAM loader program. If an interrupt occurs with SYSCR3 set to "0", the BOOTROM area is referenced as a vector address and, therefore, the program will not function properly. Note 4: Bits 7 to 3 of SYSCR3 are read as "0". System control register 4 7 SYSCR4 (0x0FDF) 6 5 4 Bit Symbol Read/Write After reset SYSCR4 3 2 1 0 0 0 0 0 SYSCR4 W 0 0 Writes the SYSCR3 data control code. 0 0 0xB2 : Enables the contents of SYSCR3. 0xD4 : Enables the contents of SYSCR3 and SYSCR3 . 0x71 : Enables the contents of IRSTSR Others : Invalid Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation. Note 2: After SYSCR3 is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3) in NORMAL mode when fcgck is fc/4 (CGCR=00). Otherwise, SYSCR3 may be enabled at unexpected timing. Page 10 RB000 TMP89FM42 Note 3: After IRSTSR is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR in NORMAL mode when fcgck is fc/4 (CGCR=00). Otherwise, IRSTSR may be enabled at unexpected timing. System control status register 4 7 6 5 4 3 2 1 0 Bit Symbol - - - - - RVCTRS RAREAS (RSTDIS) Read/Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 SYSSR4 (0x0FDF) RAREAS Status of mapping of the RAM in the code area 0: The enabled SYSCR3 data is "0". 1: The enabled SYSCR3 data is "1". RVCTRS Status of mapping of the vector address in the area 0: The enabled SYSCR3 data is "0". 1: The enabled SYSCR3 data is "1". Note:Bits 7 to 3 of SYSSR4 are read as "0". Example: Program transfer (Transfer the program saved in the data area to the RAM.) TRANS_RAM: 2.2.1.2 LD HL, TRANSFER_START_ADDRESS ;Destination RAM address LD DE, PROGRAM_START_ADDRESS ;Source ROM address LD BC, BYTE_OF_PROGRAM ;Number of bytes of the program to be executed -1 LD A, (DE) ;Reading the program to be transferred LD (HL), A ;Writing the program to be transferred INC HL ;Destination address increment INC DE ;Source address increment DEC BC ;Have all the programs been transferred? J F, TRANS_RAM BOOTROM The BOOTROM is not mapped in the code area or the data area after reset release. Setting FLSCR1 to "1" and writing 0xD5 to FLSCR2 maps the BOOTROM to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Flash memory can be easily programmed by using the API (Application Programming Interface) contained in the BOOTROM. Note 1: When the BOOTROM is not mapped in the code area, an instruction is fetched from the Flash or an SWI instruction is fetched, depending on the capacity of the internal Flash. Note 2: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Page 11 RB000 2. 2.2 CPU Core Memory space TMP89FM42 Flash memory control register 1 7 FLSCR1 (0x0FD0) Bit Symbol 6 BAREA 4 (FLSMD) Read/Write After reset 5 BAREA R/W 0 1 3 Specifies mapping of the BOOTROM in the code and data areas 1 (FAREA) R/W 0 2 (ROMSEL) R/W 0 0 0 R/W 0 0 0 0: The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. 1: The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Note:The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register. Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift register can be checked by reading the register FLSCRM. Flash memory control register 2 7 FLSCR2 (0x0FD1) 6 5 4 Bit Symbol CR1EN 2.2.1.3 2 1 0 * * * * CR1EN Read/Write After reset 3 W * FLSCR1 register enable/disable control * * * 0xD5 Others Enable a change in the FLSCR1 setting Reserved Flash The Flash is mapped to 0x8000 to 0xFFFF in the code area after reset release. Page 12 RB000 TMP89FM42 2.2.2 Data area The data area stores the data to be accessed as sources and destinations of transfer and calculation instructions. The SFR, the RAM, the BOOTROM and the FLASH are mapped in the data area. 0x0000 0x003F 0x0040 0x083F 0x0E40 0x0EFF 0x0F00 0x0FFF 0x1000 SFR1 SFR1 (64 bytes) (64 bytes) RAM RAM (2048 bytes) (2048 bytes) 0xFF is read 0xFF is read SFR3 SFR3 (192 bytes) (192 bytes) SFR2 SFR2 (256 bytes) (256 bytes) BOOTROM (2048 bytes) 0x17FF 0x1800 0xFF is read 0x7FFF 0x8000 0xFF is read Flash Flash (32768 bytes) (32768 bytes) Immediately after reset release When the BOOTROM is mapped in the data area 0xFFFF Figure 2-2 Memory Map in the Data Area Note:Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. 2.2.2.1 SFR The SFR is mapped to 0x0000 to 0x003F (SFR1), 0x0F00 to 0x0FFF (SFR2) and 0x0E40 to 0x0EFF (SFR3) in the data area after reset release. Note:Don't access the reserved SFR. 2.2.2.2 RAM The RAM is mapped to 0x0040 to 0x083F in the data area after reset release. Note:The contents of the RAM become unstable when the power is turned on and immediately after a reset is released. To execute the program by using the RAM, transfer the program to be executed in the initialization routine. Page 13 RB000 2. 2.2 CPU Core Memory space TMP89FM42 Example: RAM initialization program CLR_RAM: 2.2.2.3 LD HL, RAM_TOP_ADDRESS ;Head of address of the RAM to be initialized LD A, 0x00 ;Initialization data LD BC, BYTE_OF_CLEAR_BYTES ;Number of bytes of RAM to be initialized -1 LD (HL), A ;Initialization of the RAM INC HL ;Initialization address increment DEC BC ;Have all the RAMs been initialized? J F, CLR_RAM BOOTROM The BOOTROM is not mapped in the code area or the data area after reset release. Setting FLSCR1 to "1" and writing 0xD5 to FLSCR2 maps the BOOTROM to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Flash memory can be easily programmed by using the API (Application Programming Interface) contained in the BOOTROM. Note 1: When the BOOTROM is not mapped in the data area, 0xFF is read from 0x1000 to 0x17FF. Note2: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Flash memory control register 1 7 FLSCR1 (0x0FD0) Bit Symbol 6 Read/Write After reset BAREA 5 4 (FLSMD) R/W 0 1 3 BAREA R/W 0 Specifies mapping of the BOOTROM in the code and data areas 2 1 (FAREA) R/W 0 0 0 (ROMSEL) R/W 0 0 0 0: The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. 1: The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Note:The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register. Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift register can be checked by reading the register FLSCRM. Flash memory control register 2 7 FLSCR2 (0x0FD1) 6 5 4 Bit Symbol Read/Write After reset CR1EN 2 1 0 * * * * W * FLSCR1 register enable/disable control * * * 0xD5 Others Enable a change in the FLSCR1 setting Reserved Page 14 RB000 3 CR1EN TMP89FM42 2.2.2.4 Flash The Flash is mapped to 0x8000 to 0xFFFF in the data area after reset release. Page 15 RB000 System clock controller 2.3 TMP89FM42 System clock controller 2.3.1 Configuration The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. CGCR FCGCKSEL Clock generator XIN TBTCR fc High-frequency clock oscillation circuit SYSCR1 SYSCR2 DV9CK fcgck Timing generator Clock gear (×1/4, ×1/2, ×1) Operation mode control circuit XOUT XTIN fs Low-frequency clock oscillation circuit 1/4 System clock XEN/XTEN 2.3 CPU Core STOP 2. Oscillation/stop control XTOUT INTWUC interrupt request Warm-up counter WUCCR WUCDR Figure 2-3 System Clock Controller 2.3.2 Control The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2 (SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and the clock gear control register (CGCR). System control register 1 SYSCR1 (0x0FDC) 7 6 5 4 2 1 0 Bit Symbol STOP RELM OUTEN DV9CK - - - - Read/Write R/W R/W R/W R/W R R R R After reset 0 0 0 0 1 0 0 0 STOP RELM Activates the STOP mode Selects the STOP mode release method 0: Operate the CPU and the peripheral circuits 1: Stop the CPU and the peripheral circuits (activate the STOP mode) 0: Edge-sensitive release mode (Release the STOP mode at the rising edge of the STOP mode release signal) 1: Level-sensitive release mode (Release the STOP mode at the "H" level of the STOP mode release signal) OUTEN Selects the port output state in the STOP mode 0: High impedance 1: Output hold DV9CK Selects the input clock to stage 9 of the divider 0: fcgck/29 1: fs/4 Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1". Page 16 RB000 3 TMP89FM42 Note 3: If the STOP mode is activated with SYSCR1 set at "0", the port internal input is fixed to "0". Therefore, an external interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated. Note 4: The P11 pin is also used as the STOP pin. When the STOP mode is activated, the pin reverts to high impedance state and is put in input mode, regardless of the state of SYSCR1. Note 5: Writing of the second byte data will be executed improperly if the operation is switched to the STOP state by an instruction, such as LDW, which executes 2-byte data transfer at a time. Note 6: Don't set SYSCK1 to "1" before the oscillation of the low-frequency clock oscillation circuit becomes stable. Note 7: In the SLOW1/2 or SLEEP1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of SYSCR1< DV9CK >. System control register 2 SYSCR2 (0x0FDD) 7 6 5 4 3 2 1 0 Bit Symbol - XEN XTEN SYSCK IDLE TGHALT - - Read/Write R R/W R/W R/W R/W R/W R R After reset 0 1 0 0 0 0 0 0 XEN XTEN SYSCK IDLE TGHALT Controls the high-frequency clock oscillation circuit 0: Stop oscillation 1: Continue or start oscillation Controls the low-frequency clock oscillation circuit 0: Stop oscillation 1: Continue or start oscillation 0: Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode) 1: Low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode) CPU and WDT control 0: Operate the CPU and the WDT (IDLE1/2 or SLEEP1 mode) 1: Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode) 0: Enable the clock supply from the TG to all the peripheral circuits 1: Disable the clock supply from the TG to the peripheral circuits except the TBT (Activate IDLE0 or SLEEP0 mode) Selects a system clock TG control (IDLE0 or SLEEP0 mode) Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: WDT: Watchdog timer, TG: Timing generator Note 3: Don't set both SYSCR2 and SYSCR2 to "1" simultaneously. Note 4: Writing of the second byte data will be executed improperly if the operation is switched to the IDLE state by an instruction, such as LDW, which executes 2-byte data transfer at a time. Note 5: When the IDLE1/2 or SLEEP1 mode is released, SYSCR2 is cleared to "0" automatically. Note 6: When the IDLE0 or SLEEP0 mode is released, SYSCR2 is cleared to "0" automatically. Note 7: Bits 7, 1 and 0 of SYSCR2 are read as "0". Warm-up counter control register 7 WUCCR (0x0FCD) 6 5 4 3 2 1 Bit Symbol WUCRST - - - WUCDIV WUCSEL - Read/Write W R R R R/W R/W R After reset 0 0 0 0 0 1 WUCRST WUCDIV WUCSEL Resets and stops the warm-up counter Selects the frequency division of the warm-up counter source clock Selects the warm-up counter source clock 1 0: - 1: Clear and stop the counter 00 : Source clock 01 : Source clock / 2 10 : Source clock / 22 11 : Source clock / 23 0: Select the high-frequency clock (fc) 1: Select the low-frequency clock (fs) 1 Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: WUCCR is cleared to "0" automatically, and need not be cleared to "0" after being set to "1". Note 3: Bits 7 to 4 of WUCCR are read as "0". Bit 0 is read as "1". Page 17 RB000 0 2. 2.3 CPU Core System clock controller TMP89FM42 Note 4: Before starting the warm-up counter operation, set the source clock and the frequency division rate at WUCCR and set the warm-up time at WUCDR. Warm-up counter data register 7 WUCDR (0x0FCE) 6 5 4 Bit Symbol WUCDR Read/Write R/W After reset 0 1 1 0 WUCDR 3 2 1 0 0 1 1 0 1 0 Warm-up time setting Note 1: Don't start the warm-up counter operation with WUCDR set at "0x00". Clock gear control register 7 6 5 4 3 2 Bit Symbol - - - - - - Read/Write R R R R R R After reset 0 0 0 0 0 0 CGCR (0x0FCF) FCGCKSEL Clock gear setting 00 : fcgck = fc / 4 01 : fcgck = fc / 2 10 : fcgck = fc 11 : Reserved FCGCKSEL R/W 0 0 Note 1: fcgck: Gear clock [Hz], fc: High-frequency clock [Hz] Note 2: Don't change CGCR in the SLOW mode. Note 3: Bits 7 to 2 of CGCR are read as "0". 2.3.3 Functions 2.3.3.1 Clock generator The clock generator generates the basic clock for the system clocks to be supplied to the CPU core and peripheral circuits. It contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency clock. The oscillation circuit pins are also used as ports P0. For the setting to use them as ports, refer to the chapter of I/O Ports. To use ports P00 and P01 as the high-frequency clock oscillation circuits (the XIN and XOUT pins), set P0FC0 to "1" and then set SYSCR2 to "1". To use ports P02 and P03 as the low-frequency clock oscillation circuits (the XTIN and XTOUT pins), set P0FC2 to "1" and then set SYSCR2 to "1". The high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an oscillator between the XIN and XOUT pins and between the XTIN and XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clocks are applied to the XIN/ XTIN pins and the XOUT/XTOUT pins are kept open. Page 18 RB000 TMP89FM42 Enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency clock oscillation circuit and switching the pin function to ports are controlled by the software and hardware. The software control is executed by SYSCR2, SYSCR2 and the P0 port function control register P0FC. The hardware control is executed by reset release and the operation mode control circuit when the operation is switched to the STOP mode as described in "2.3.5 Operation mode control circuit". Note:No hardware function is available for external direct monitoring of the basic clock. The oscillation frequency can be adjusted by programming the system to output pulses at a certain frequency to a port (for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring the output. An adjustment program must be created in advance for a system that requires adjustment of the oscillation frequency. To prevent the dead lock of the CPU core due to the software-controlled enabling/disabling of the oscillation, an internal factor reset is generated depending on the combination of values of the clock selected as the main system clock, SYSCR2, SYSCR2 and the P0 port function control register P0FC0. Table 2-1 Prohibited Combinations of Oscillation Enable Register Conditions P0FC0 SYSCR2 SYSCR2 SYSCR2 Don't Care 0 0 Don’t Care Don’t Care Don’t Care 0 1 The low-frequency clock (fs) is selected as the main system clock, but the low-frequency clock oscillation circuit is stopped. Don’t Care 0 Don’t Care 0 The high-frequency clock (fc) is selected as the main system clock, but the high-frequency clock oscillation circuit is stopped. 0 1 Don’t Care Don’t Care State All the oscillation circuits are stopped. The high-frequency clock oscillation circuit is allowed to oscillate, but the port is set as a general-purpose port. Note:It takes a certain period of time after SYSCR2 is changed before the main system clock is switched. If the currently operating oscillation circuit is stopped before the main system clock is switched, the internal condition becomes as shown in Table 2-1 and a system clock reset occurs. For details of clock switching, refer to "2.3.6 Operation Mode Control". High-frequency clock XIN XOUT XIN Low-frequency clock XOUT XTIN XTOUT (Open) (a) Crystal or ceramic oscillator XTIN XTOUT (Open) (b) External oscillator (c) Crystal oscillator (d) External oscillator Figure 2-4 Examples of Oscillator Connection 2.3.3.2 Clock gear The clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency clock (fc) and inputs it to the timing generator. Selects a divided clock at CGCR. Two machine cycles are needed after CGCR is changed before the gear clock (fcgck) is changed. Page 19 RB000 2. 2.3 CPU Core System clock controller TMP89FM42 The gear clock (fcgck) may be longer than the set clock width, immediately after CGCR is changed. Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the highfrequency clock (fc). Table 2-2 Gear Clock (fcgck) CGCR fcgck 00 fc / 4 01 fc / 2 10 fc 11 Reserved Note:Don't change CGCR in the SLOW mode. This may stop the gear clock (fcgck) from being changed. 2.3.3.3 Timing generator The timing generator is a circuit that generates system clocks to be supplied to the CPU core and the peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). The timing generator has the following functions: 1. Generation of the main system clock (fm) 2. Generation of clocks for the timer counter, the time base timer and other peripheral circuits Main system clock fm Main system clock generator Machine cycle counter SYSCR2 SYSCR1 Prescaler Divider A Gear clock fcgck S Divider Y B Multiplexer A quarter of the basic clock for the low-frequency clock Timer counter, time base timer and other peripheral circuits Figure 2-5 Configuration of Timing Generator (1) Configuration of timing generator The timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and a machine cycle counter. 1. Main system clock generator This circuit selects the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs) for the main system clock (fm) to operate the CPU core. Clearing SYSCR2 to "0" selects the gear clock (fcgck). Setting it to "1" selects the clock that is a quarter of the low-frequency clock (fs). Page 20 RB000 TMP89FM42 It takes a certain period of time after SYSCR2 is changed before the main system clock is switched. If the currently operating oscillation circuit is stopped before the main system clock is switched, the internal condition becomes as shown in Table 2-1 and a system clock reset occurs. For details of clock switching, refer to "2.3.6 Operation Mode Control". 2. Prescaler and divider These circuits divide fcgck. The divided clocks are supplied to the timer counter, the time base timer and other peripheral circuits. When both SYSCR1 and SYSCR2 are "0", the input clock to stage 9 of the divider becomes the output of stage 8 of the divider. When SYSCR1 or SYSCR2 is "1", the input clock to stage 9 of the divider becomes fs/4. When SYSCR2 is "1", the outputs of stages 1 to 8 of the divider and prescaler are stopped. The prescaler and divider are cleared to "0" at a reset and at the end of the warm-up operation that follows the release of STOP mode. 3. Machine cycle Instruction execution is synchronized with the main system clock (fm). The minimum instruction execution unit is called a "machine cycle". One machine cycle corresponds to one main system clock. There are a total of 11 different types of instructions for the TLCS-870/C1 Series: 10 types ranging from 1-cycle instructions, which require one machine cycle for execution, to 10-cycle instructions, which require 10 machine cycles for execution, and 13-cycle instructions, which require 13 machine cycles for execution. 2.3.4 Warm-up counter The warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs), and it consists of a source clock selection circuit, a 3-stage frequency division circuit and a 14-stage counter. The warm-up counter is used to secure the time after a power-on reset is released before the supply voltage becomes stable and secure the time after the STOP mode is released or the operation mode is changed before the oscillation by the oscillation circuit becomes stable. WUCCR WUCSEL WUCDIV SYSCR2 WUCRST SYSCR1 XEN XTEN STOP INTWUC interrupt Warm-up counter controller Enable/disable counting up S Clock for high-frequency clock oscillation circuit (fc) Clock for low-frequency clock oscillation circuit (fs) A Z B 1 2 3 S D CZ B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Comparator 0 1 2 3 4 5 6 7 WUCDR Figure 2-6 Warm-up Counter Circuit Page 21 RB000 Enable CPU operation 2. 2.3 CPU Core System clock controller 2.3.4.1 TMP89FM42 Warm-up counter operation when the oscillation is enabled by the hardware (1) When a power-on reset is released or a reset is released The warm-up counter serves to secure the time after a power-on reset is released before the supply voltage becomes stable and the time after a reset is released before the oscillation by the high-frequency clock oscillation circuit becomes stable. When the power is turned on and the supply voltage exceeds the power-on reset release voltage, the warm-up counter reset signal is released. At this time, the CPU and the peripheral circuits are held in the reset state. A reset signal initializes WUCCR to "0" and WUCCR to "11", which selects the high-frequency clock (fc) as the input clock to the warm-up counter. When a reset is released for the warm-up counter, the high-frequency clock (fc) is input to the warmup counter, and the 14-stage counter starts counting the high-frequency clock (fc). When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and a reset is released for the CPU and the peripheral circuits. WUCDR is initialized to 0x66 after reset release, which makes the warm-up time 0x66 × 29/fc[s]. Note:The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. (2) When the STOP mode is released The warm-up counter serves to secure the time after the oscillation is enabled by the hardware before the oscillation becomes stable at the release of the STOP mode. The high-frequency clock (fc) or the low-frequency clock (fs), which generates the main system clock when the STOP mode is activated, is selected as the input clock for frequency division circuit, regardless of WUCCR. Before the STOP mode is activated, select the division rate of the input clock to the warm-up counter at WUCCR and set the warm-up time at WUCDR. When the STOP mode is released, the 14-stage counter starts counting the input clock selected in the frequency division circuit. When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and the operation is restarted by an instruction that follows the STOP mode activation instruction. Clock that generates the main system clock when the STOP mode is activated fc fs WUCCR WUCCR Counter input clock Warm-up time 00 fc 26 / fc to 255 x 26 / fc 01 fc / 2 27 / fc to 255 x 27 / fc 10 fc / 22 28 / fc to 255 x 28 / fc 11 fc / 2 29 / fc to 255 x 29 / fc 00 fs 26 / fs to 255 x 26 / fs 01 fs / 2 27 / fs to 255 x 27 / fs 10 2 fs / 2 28 / fs to 255 x 28 / fs 11 fs / 23 29 / fs to 255 x 29 / fs Don’t Care Don't Care 3 Note 1: When the operation is switched to the STOP mode during the warm-up for the oscillation enabled by the software, the warm-up counter holds the value at the time, and restarts counting after the STOP mode is released. In this case, the warm-up time at the release of the STOP mode becomes insufficient. Don't switch the operation to the STOP mode during the warm-up for the oscillation enabled by the software. Page 22 RB000 TMP89FM42 Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for the oscillation start property of the oscillator. 2.3.4.2 Warm-up counter operation when the oscillation is enabled by the software The warm-up counter serves to secure the time after the oscillation is enabled by the software before the oscillation becomes stable, at a mode change from NORMAL1 to NORMAL2 or from SLOW1 to SLOW2. Select the input clock to the frequency division circuit at WUCCR. Select the input clock to the 14-stage counter at WUCCR. After the warm-up time is set at WUCDR, setting SYSCR2 or SYSCR2 to "1" allows the stopped oscillation circuit to start oscillation and the 14-stage counter to start counting the selected input clock. When the upper 8 bits of the counter become equal to WUCDR, an INTWUC interrupt occurs, counting is stopped and the counter is cleared. Set WUCCR to "1" to discontinue the warm-up operation. By setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and WUCCR is cleared to "0". SYSCR2 and SYSCR2 hold the values when WUCCR is set to "1". To restart the warm-up operation, SYSCR2 or SYSCR2 must be cleared to "0". Note:The warm-up counter starts counting when SYSCR2 or SYSCR2 is changed from "0" to "1". The counter will not start counting by writing "1" to SYSCR2 or SYSCR2 when it is in the state of "1". WUCCR WUCCR Counter input clock Warm-up time 00 fc 26 / fc to 255 x 26 / fc 01 fc / 2 27 / fc to 255 x 27 / fc 10 fc / 22 28 / fc to 255 x 28 / fc 11 fc / 23 29 / fc to 255 x 29 / fc 00 fs 26 / fs to 255 x 26 / fs 01 fs / 2 27 / fs to 255 x 27 / fs 10 fs / 2 28 / fs to 255 x 28 / fs 11 fs / 2 29 / fs to 255 x 29 / fs 0 1 2 3 Note:The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for the oscillation start property of the oscillator. 2.3.5 Operation mode control circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock (fm). There are three operating modes: the single-clock mode, the dual-clock mode and the STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-7 shows the operating mode transition diagram. Page 23 RB000 2. 2.3 CPU Core System clock controller 2.3.5.1 TMP89FM42 Single-clock mode Only the gear clock (fcgck) is used for the operation in the single-clock mode. The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time is 1/fcgck [s]. The gear clock (fcgck) is generated from the high-frequency clock (fc). In the single-clock mode, the low-frequency clock generation circuit pins P02 (XTIN) and P03 (XTOUT) can be used as the I/O ports. (1) NORMAL1 mode In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck). The NORMAL1 mode becomes active after reset release. (2) IDLE1 mode In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck). The IDLE1 mode is activated by setting SYSCR2 to "1" in the NORMAL1 mode. When the IDLE1 mode is activated, the CPU and the watchdog timer stop. When the interrupt latch enabled by the interrupt enable register EFR becomes "1", the IDLE1 mode is released to the NORMAL1 mode. When the IMF (interrupt master enable flag) is "1" (interrupts enabled), the operation returns normal after the interrupt processing is completed. When the IMF is "0" (interrupts disabled), the operation is restarted by the instruction that follows the IDLE1 mode activation instruction. (3) IDLE0 mode In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time base timer. In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or become the same as the states when a reset is released. For operations of the peripheral circuits in the IDLE0 mode, refer to the section of each peripheral circuit. The IDLE0 mode is activated by setting SYSCR2 to "1" in the NORMAL1 mode. When the IDLE0 mode is activated, the CPU stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. When the falling edge of the source clock selected at TBTCR is detected, the IDLE0 mode is released, the timing generator starts the clock supply to all the peripheral circuits and the NORMAL1 mode is restored. Note that the IDLE0 mode is activated and restarted, regardless of the setting of TBTCR. When the IDLE0 mode is activated with TBTCR set at "1", the INTTBT interrupt latch is set after the NORMAL mode is restored. When the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is "1", the operation returns normal after the interrupt processing is completed. Page 24 RB000 TMP89FM42 When the IMF is "0" or when the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is "0", the operation is restarted by the instruction that follows the IDLE0 mode activation instruction. 2.3.5.2 Dual-clock mode The gear clock (fcgck) and the low-frequency clock (fs) are used for the operation in the dual-clock mode. The main system clock (fm) is generated from the gear clock (fcgck) in the NORMAL2 or IDLE2 mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the SLOW1/2 or SLEEP0/1 mode. Therefore, the machine cycle time is 1/fcgck [s] in the NORMAL2 or IDLE2 mode and is 4/fs [s] in the SLOW1/2 or SLEEP0/1 mode. P02 (XTIN) and P03 (XTOUT) are used as the low-frequency clock oscillation circuit pins. (These pins cannot be used as I/O ports in the dual-clock mode.) The operation of the TLCS-870/C1 Series becomes the single-clock mode after reset release. To operate it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program. (1) NORMAL2 mode In this mode, the CPU core operates using the gear clock (fcgck), and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). (2) SLOW2 mode In this mode, the CPU core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). In the SLOW mode, some peripheral circuits become the same as the states when a reset is released. For operations of the peripheral circuits in the SLOW mode, refer to the section of each peripheral circuit. Set SYSCR2 to switch the operation mode from NORMAL2 to SLOW2 or from SLOW2 to NORMAL2. In the SLOW2 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (3) SLOW1 mode In this mode, the high-frequency clock oscillation circuit stops operation and the CPU core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). This mode requires less power to operate the high-frequency clock oscillation circuit than in the SLOW2 mode. In the SLOW mode, some peripheral circuits become the same as the states when a reset is released. For operations of the peripheral circuits in the SLOW mode, refer to the section of each peripheral circuit. Set SYSCR2 to switch the operation between the SLOW1 and SLOW2 modes. In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (4) IDLE2 mode In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). Page 25 RB000 2. 2.3 CPU Core System clock controller TMP89FM42 The IDLE2 mode can be activated and released in the same way as for the IDLE1 mode. The operation returns to the NORMAL2 mode after this mode is released. (5) SLEEP1 mode In this mode, the high-frequency clock oscillation circuit stops operation, the CPU and the watchdog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). In the SLEEP1 mode, some peripheral circuits become the same as the states when a reset is released. For operations of the peripheral circuits in the SLEEP1 mode, refer to the section of each peripheral circuit. The SLEEP1 mode can be activated and released in the same way as for the IDLE1 mode. The operation returns to the SLOW1 mode after this mode is released. In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (6) SLEEP0 mode In this mode, the high-frequency clock oscillation circuit stops operation, the time base timer operates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral circuits stop. In the SLEEP0 mode, the peripheral circuits stop in the states when the SLEEP0 mode is activated or become the same as the states when a reset is released. For operations of the peripheral circuits in the SLEEP0 mode, refer to the section of each peripheral circuit. The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode. The operation returns to the SLOW1 mode after this mode is released. In the SLEEP0 mode, the CPU stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. 2.3.5.3 STOP mode In this mode, all the operations in the system, including the oscillation circuits, are stopped and the internal states in effect before the system was stopped are held with low power consumption. In the STOP mode, the peripheral circuits stop in the states when the STOP mode is activated or become the same as the states when a reset is released. For operations of the peripheral circuits in the STOP mode, refer to the section of each peripheral circuit. The STOP mode is activated by setting SYSCR1 to "1". The STOP mode is released by the STOP mode release signals. After the warm-up time has elapsed, the operation returns to the mode that was active before the STOP mode, and the operation is restarted by the instruction that follows the STOP mode activation instruction. Page 26 RB000 TMP89FM42 2.3.5.4 Transition of operation modes RESET Reset release IDLE0 mode Warm-up that follows reset release Warm-up completed SYSCR2 = ”1” (Note 2) SYSCR2 = "1" IDLE0 mode SYSCR1 = "1" NORMAL1 mode STOP mode release signal Interrupt (a) Single-clock mode SYSCR2 = "1" SYSCR2 = "0" SYSCR2 = "1" IDLE2 mode SYSCR1 = "1" NORMAL2 mode STOP mode release signal Interrupt SYSCR2 = "1" STOP SYSCR2 = "0" SLOW2 mode SYSCR2 = "1" SYSCR2 = "0" SYSCR2 = "1" SLEEP1 mode SYSCR1 = "1" SLOW1 mode Interrupt STOP mode release (Note 2) SYSCR2 = "1" signal (b) Dual-clock mode SLEEP0 mode Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2 modes are called the SLOW mode; the IDLE0, IDLE1 and IDLE2 modes are called the IDLE mode; and the SLEEP0 and SLEEP1 are called the SLEEP mode. Note 2: The mode is released by the falling edge of the source clock selected at TBTCR. Figure 2-7 Operation Mode Transition Diagram Page 27 RB000 2. 2.3 CPU Core System clock controller TMP89FM42 Table 2-3 Operation Modes and Conditions Oscillation circuit Operation mode High-frequency Low-frequency RESET NORMAL1 Single clock IDLE1 Oscillation Other peripheral circuits Reset Reset Reset Reset Reset Operate Operate Operate Operate Stop Stop Operate Stop Stop Operate with the high frequency Operate with the high / low frequency Stop Stop Operate with the low frequency Operate with the low frequency Operate with the low frequency Operate with the low frequency Stop Stop Oscillation SLOW2 Oscillation Dual clock SLOW1 Operate Machine cycle time 1 / fcgck [s] − 1 / fcgck [s] Operate Operate 4/ fs [s] Stop Stop SLEEP0 STOP 2.3.6 converter Stop NORMAL2 SLEEP1 Time base timer Stop STOP IDLE2 Watchdog timer Stop IDLE0 AD CPU core Stop Stop Stop − Operation Mode Control 2.3.6.1 STOP mode The STOP mode is controlled by system control register 1 (SYSCR1) and the STOP mode release signals. (1) Start the STOP mode The STOP mode is started by setting SYSCR1 to "1". In the STOP mode, the following states are maintained: 1. Both the high-frequency and low-frequency clock oscillation circuits stop oscillation and all internal operations are stopped. 2. The data memory, the registers and the program status word are all held in the states in effect before STOP mode was started. The port output latch is determined by the value of SYSCR1. 3. The prescaler and the divider of the timing generator are cleared to "0". 4. The program counter holds the address of the instruction 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started the STOP mode. (2) Release the STOP mode The STOP mode is released by the following STOP mode release signals. It is also released by a reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active. 1. Release by the STOP pin 2. Release by key-on wakeup 3. Release by the voltage detection circuits Page 28 RB000 TMP89FM42 Note:During the STOP period (from the start of the STOP mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after the STOP mode is released. Before starting the STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. 1. Release by the STOP pin Release the STOP mode by using the STOP pin. The STOP mode release by the STOP pin includes the level-sensitive release mode and the edge-sensitive release mode, either of which can be selected at SYSCR1. The STOP pin is also used as the P11 port and the INT5 (external interrupt input 5) pin. - Level-sensitive release mode The STOP mode is released by setting the STOP pin high. Setting SYSCR1 to "1" selects the level-sensitive release mode. This mode is used for the capacitor backup when the main power supply is cut off and the long term battery backup. Even if an instruction for starting the STOP mode is executed while the STOP pin input is high, the STOP mode does not start. Thus, to start the STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. This can be confirmed by testing the port by the software or using interrupts Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR. Example: Starting the STOP mode from NORMAL mode after testing P00 port. (Warm-up time at release of the STOP mode is about 300μs at fc= 10MHz.) SSTOPH: LD (SYSCR1), 0x40 ;Sets up the level-sensitive release mode TEST (P0PRD). 5 ;Wait until STOP pin becomes L level. J F, SSTOPH LD (WUCCR), 0x01 ;WUCCR = 00 (No division) (Note) LD (WUCDR),0x2F ;Sets the warm-up time ;300μs / 6.4μs = 46.9 → round up to 0x2F DI SET Note: ;IMF = 0 (SYSCR1).7 ;Starts the STOP mode When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR. Example: Starting the STOP mode from the SLOW mode with an INT5 interrupt (Warm-up time at release of the STOP mode is about 450ms at fs=32.768 kHz.) PINT5: TEST (P0PRD).5 ;To reject noise, the STOP mode does not start J F, SINT5 ;if the STOP pin input is high. LD (SYSCR1), 0x40 ;Sets up the level-sensitive release mode LD (WUCCR), 0x03 ;WUCCR = 00 (No division) (Note) LD (WUCDR),0xE8 ;Sets the warm-up time ;450 ms/1.953 ms = 230.4 → round up to 0xE8 DI SET SINT5: ;IMF = 0 (SYSCR1).7 ;Starts the STOP mode RETI Page 29 RB000 2. 2.3 CPU Core System clock controller Note: TMP89FM42 When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR. VIH STOP pin XOUT pin STOP mode NORMAL mode Warm-up Confirm by program that the STOP pin input is low and start the STOP mode. Note: NORMAL mode The STOP mode is released by the hardware. Always released if the STOP pin input is high. Even if the STOP pin input returns to low after the warm-up starts, the STOP mode is not restarted. Figure 2-8 Level-sensitive Release Mode (Example when the high-frequency clock oscillation circuit is selected) - Edge-sensitive release mode In this mode, the STOP mode is released at the rising edge of the STOP pin input. Setting SYSCR1 to "0" selects the edge-sensitive release mode. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, the STOP mode is started even when the STOP pin input is high Example: Starting the STOP mode from the NORMAL mode (Warm-up time at release of the STOP mode is about 200μs at fc=10 MHz.) LD (WUCCR),0x01 ;WUCCR = 00 (No division) (Note) LD (WUCDR),0x20 ;Sets the warm-up time ;200μs / 6.4μs = 31.25 → round up to 0x20 DI LD Note: ;IMF = 0 (SYSCR1) , 0x80 ;Starts the STOP mode with the edge-sensitive release mode selected When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR. VIH STOP pin XOUT pin NORMAL mode The STOP mode is started by the program. Note: STOP mode Warm-up NORMAL mode STOP mode The STOP mode is released by the hardware at the rising edge of the STOP pin input. If the rising edge is input to the STOP pin within 1 machine cycle after SYSCR1 is set to "1", the STOP mode will not be released. Figure 2-9 Edge-sensitive Release Mode (Example when the high-frequency clock oscillation circuit is selected) 2. Release by the key-on wakeup Page 30 RB000 TMP89FM42 The STOP mode is released by inputting the prescribed level to the key-on wakeup pin. The level to release the STOP mode can be selected from "H" and "L". For release by the key-on wakeup, refer to section "Key-on Wakeup". Note: If the key-on wakeup pin input becomes the opposite level to the release level after the warm-up starts, the STOP mode is not restarted. 3. Release by the voltage detection circuits The STOP mode is released by the supply voltage detection by the voltage detection circuits. If the voltage detection operation mode of the voltage detection circuits is set to "Generates a voltage detection reset signal", the STOP mode is released and a reset is applied as soon as the supply voltage becomes lower than the detection voltage. When the supply voltage becomes equal to or higher than the detection voltage of the voltage detection circuits, the reset is released and the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active. For details, refer to the section of the voltage detection circuits. Note: If the supply voltage becomes equal to or higher than the detection voltage within 1 machine cycle after SYSCR1 is set to "1", the STOP mode will not be released. (3) STOP mode release operation The STOP mode is released in the following sequence: 1. Oscillation starts. For the oscillation start operation in each mode, refer to "Table 2-4 Oscillation Start Operation at Release of the STOP Mode". 2. Warm-up is executed to secure the time required to stabilize oscillation. The internal operations remain stopped during warm-up. The warm-up time is set by the warm-up counter, depending on the oscillator characteristics. 3. After the warm-up time has elapsed, the normal operation is restarted by the instruction that follows the STOP mode start instruction. At this time, the prescaler and the divider of the timing generator are cleared to "0". Note:When the STOP mode is released with a low hold voltage, the following cautions must be observed. The supply voltage must be at the operating voltage level before releasing the STOP mode. The RESET pin input must also be "H" level, rising together with the supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if the input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-4 Oscillation Start Operation at Release of the STOP Mode Operation mode before the STOP mode is started Single-clock mode High-frequency clock Low-frequency clock NORMAL1 High-frequency clock oscillation circuit - NORMAL2 High-frequency clock oscillation circuit Low-frequency clock oscillation circuit SLOW1 - Low-frequency clock oscillation circuit Dual-clock mode Page 31 RB000 Oscillation start operation after release The high-frequency clock oscillation circuit starts oscillation. The low-frequency clock oscillation circuit stops oscillation. The high-frequency clock oscillation circuit starts oscillation. The low-frequency clock oscillation circuit starts oscillation. The high-frequency clock oscillation circuit stops oscillation. The low-frequency clock oscillation circuit starts oscillation. 2. 2.3 CPU Core System clock controller TMP89FM42 Note:When the operation returns to the NORMAL2 mode, fc is input to the frequency division circuit of the warm-up counter. 2.3.6.2 IDLE1/2 and SLEEP1 modes The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following states are maintained during these modes. 1. The CPU and the watchdog timer stop their operations. The peripheral circuits continue to operate. 2. The data memory, the registers, the program status word and the port output latches are all held in the status in effect before IDLE1/2 or SLEEP1 mode was started. 3. The program counter holds the address of the instruction 2 ahead of the instruction which starts the IDLE1/2 or SLEEP1 mode. Starting IDLE1/2 mode or SLEEP1 mode by an instruction CPU and WDT stop Yes Reset input Reset No No Interrupt request Yes No (Normal release mode) IMF = "1" Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 mode or SLEEP1 mode start instruction Figure 2-10 IDLE1/2 and SLEEP 1 Modes Page 32 RB000 TMP89FM42 (1) Start the IDLE1/2 and SLEEP1 modes After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag (EF) to "1", which releases IDLE1/2 and SLEEP1 modes. To start the IDLE1/2 or SLEEP1 mode, set SYSCR2 to "1". If the release condition is satisfied when it is attempted to start the IDLE1/2 or SLEEP1 mode, SYSCR2 remains cleared and the IDLE1/2 or SLEEP1 mode will not be started. Note 1: When a watchdog timer interrupt is generated immediately before the IDLE1/2 or SLEEP1 mode is started, the watchdog timer interrupt will be processed but the IDLE1/2 or SLEEP1 mode will not be started. Note 2: Before starting the IDLE1/2 or SLEEP1 mode, enable the interrupt request signals to be generated to release the IDLE1/2 or SLEEP1 mode and set the individual interrupt enable flag. (2) Release the IDLE1/2 and SLEEP1 modes The IDLE1/2 and SLEEP1 modes include a normal release mode and an interrupt release mode. These modes are selected at the interrupt master enable flag (IMF). After releasing IDLE1/2 or SLEEP1 mode, SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding the IDLE1/2 or SLEEP1 mode. The IDLE1/2 and SLEEP1 modes are also released by a reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. After releasing the reset, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active. ・ Normal release mode (IMF = "0") The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individual interrupt enable flag (EF) is "1". The operation is restarted by the instruction that follows the IDLE1/2 or SLEEP1 mode start instruction. Normally, the interrupt latch (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. ・ Interrupt release mode (IMF = "1") The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individual interrupt enable flag (EF) is "1". After the interrupt is processed, the operation is restarted by the instruction that follows the IDLE1/2 or SLEEP1 mode start instruction. 2.3.6.3 IDLE0 and SLEEP0 modes The IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following states are maintained during the IDLE0 and SLEEP0 modes: ・ The timing generator stops the clock supply to the peripheral circuits except the time base timer. ・ The data memory, the registers, the program status word and the port output latches are all held in the states in effect before the IDLE0 or SLEEP0 mode was started. ・ The program counter holds the address of the instruction 2 ahead of the instruction which starts the IDLE0 or SLEEP0 mode. Page 33 RB000 2. 2.3 CPU Core System clock controller TMP89FM42 Stopping peripherals by instructions Starting IDLE0 or SLEEP0 mode by an instruction CPU and WDT stop Yes Reset input Reset No No TBT source clock falling edge Yes "0" TBTCR "1" No TBT interrupt enabled (Normal release mode) Yes No IMF = "1" Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0 or SLEEP0 mode start instruction Figure 2-11 IDLE0 and SLEEP0 Modes ・ Start the IDLE0 and SLEEP0 modes Stop (disable) the peripherals such as a timer counter. To start the IDLE0 or SLEEP0 mode, set SYSCR2 to "1". ・ Release the IDLE0 and SLEEP0 modes The IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode. These modes are selected at the interrupt master enable flag (IMF), the individual interrupt enable flag (EF5) for the time base timer and TBTCR. After releasing the IDLE0 or SLEEP0 mode, SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding the IDLE0 or SLEEP0 mode. If TBTCR has been set at "1", the INTTBT interrupt latch is set. The IDLE0 and SLEEP0 modes are also released by a reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active. Page 34 RB000 TMP89FM42 (1) Normal release mode (IMF, EF5, TBTCR = "0") The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at TBTCR is detected. After the IDLE0 or SLEEP0 mode is released, the operation is restarted by the instruction that follows the IDLE0 or SLEEP0 mode start instruction. When TBTCR is "1", the time base timer interrupt latch is set. (2) Interrupt release mode (IMF, EF5, TBTCR = "1") The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at TBTCR is detected. After the release, the INTTBT interrupt processing is started. Note 1: The IDLE0 or SLEEP0 mode is released to the NORMAL1 or SLOW1 mode by the asynchronous internal clock selected at TBTCR. Therefore, the period from the start to the release of the mode may be shorter than the time specified at TBTCR. Note 2: When a watchdog timer interrupt is generated immediately before the IDLE0 or SLEEP0 mode is started, the watchdog timer interrupt will be processed but the IDLE0 or SLEEP0 mode will not be started. 2.3.6.4 SLOW mode The SLOW mode is controlled by system control register 2 (SYSCR2). (1) Switching from the NORMAL2 mode to the SLOW1 mode Set SYSCR2 to "1". When a maximum of 2/fcgck + 10/fs [s] has elapsed since SYSCR2 is set to "1", the main system clock (fm) is switched to fs/4. After switching, wait for 2 machine cycles or longer, and then clear SYSCR2 to "0" to turn off the high-frequency clock oscillator. If the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the warmup counter before implementing the procedure described above. Note 1: Be sure to follow this procedure to switch the operation from the NORMAL2 mode to the SLOW1 mode. Note 2: It is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to return to NORMAL2 mode. However, be sure to turn off the oscillation of the basic clock for the high-frequency clock when the STOP mode is started from the SLOW mode. Note 3: After switching SYSCR2, be sure to wait for 2 machine cycles or longer before clearing SYSCR2 to "0". Clearing it within 2 machine cycles causes a system clock reset. Note 4: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization, fm is stopped for a period of 10/fs or shorter. Page 35 RB000 2. 2.3 CPU Core System clock controller TMP89FM42 Quarter of the low-frequency clock (fs/4) Gear clock (fcgck) SYSCR2 Main system clock 10/fs (max.) When the rising edge of fcgck is When the rising edge of fs/4 is detected detected twice after SYSCR2 twice after fm is stopped, fm is switched to fs. is changed from 0 to 1, f is stopped for synchronization. Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4) Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the highfrequency clock) SET (SYSCR2).4 ;SYSCR2 = 1 ;(Switches the main system clock to the basic clock for the ;low-frequency clock for the SLOW2 mode) NOP ;Waits for 2 machine cycles NOP CLR (SYSCR2).6 ;SYSCR2 = 0 ;(Turns off the high-frequency clock oscillation circuit) Example 2: Switching to the SLOW1 mode after the stable oscillation of the low-frequency clock oscillation circuit is confirmed at the warm-up counter (fs=32.768kHz, warm-up time = about 100 ms) ; #### Initialize routine #### SET (P0FC).2 ;P0FC2 = 1 (Uses P02/03 as oscillators) (WUCCR), 0x02 ;WUCCR = 00 (No division) ¦ ¦ LD ;WUCCR = 1 (Selects fs as the source clock) LD (WUCDR), 0x33 ;Sets the warm-up time ;(Determines the time depending on the oscillator characteristics) ;100 ms/1.95 ms = 51.2 → round up to 0x33 SET (EIRL).4 ;Enables INTWUC interrupts SET (SYSCR2).5 ;SYSCR2 = 1 ;(Starts the low-frequency clock oscillation and starts the warm-up ;counter) ¦ ; #### Interrupt service routine of warm-up counter interrupts #### PINTWUC: SET (SYSCR2).4 ;SYSCR2 = 1 ;(Switches the main system clock to the low-frequency clock) NOP ;Waits for 2 machine cycles NOP CLR (SYSCR2).6 ;SYSCR2 = 0 ;(Turns off the high-frequency clock oscillation circuit) RETI ¦ Page 36 RB000 TMP89FM42 VINTWUC: (2) DW PINTWUC ;INTWUC vector table Switching from the SLOW1 mode to the NORMAL1 mode Set SYSCR2 to "1" to enable the high-frequency clock (fc) to oscillate. Confirm at the warmup counter that the oscillation of the basic clock for the high-frequency clock has stabilized, and then clear SYSCR2 to "0". When a maximum of 8/fs + 2.5/fcgck [s] has elapsed since SYSCR2 is cleared to "0", the main system clock (fm) is switched to fcgck. After switching, wait for 2 machine cycles or longer, and then clear SYSCR2 to "0" to turn off the low-frequency clock oscillator. The SLOW mode is also released by a reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active. Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the NORMAL1 mode. Note 2: After switching SYSCR2, be sure to wait for 2 machine cycles or longer before clearing SYSCR2 to "0". Clearing it within 2 machine cycles causes a system clock reset. Note 3: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization, fm is stopped for a period of 2.5/fcgck [s] or shorter. Note 4: When P0FC0 is "0", setting SYSCR2 to "1" causes a system clock reset. Note 5: When SYSCR2 is set at "1", writing "1" to SYSCR2 does not cause the warm-up counter to start counting the source clock. Quarter of the low-frequency clock (fs/4) Gear clock (fcgck) 2.5/fcgck(max.) SYSCR2 Main system clock When the rising edge of fs/4 is When the rising edge of fcgck is detected detected twice after SYSCR2 twice after fm is stopped, fm is switched to fcgck. is changed from 1 to 0, f is stopped for synchronization. Figure 2-13 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck) Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the high-frequency clock oscillation circuit is confirmed at the warm-up counter (fc = 10 MHz, warm-up time = 4.0 ms) ; #### Initialize routine #### SET (P0FC).2 ;P0FC2 = 1 (Uses P02/03 as oscillators) LD (WUCCR), 0x09 ;WUCCR = 10 (Divided by 2) LD (WUCDR), 0x9D ¦ ¦ ;WUCCR = 0 (Selects fc as the source clock) ;Sets the warm-up time ;(Determine the time depending on the frequency and the oscillator ;characteristics) ;4ms / 25.6us = 156.25 → round up to 0x9D Page 37 RB000 2. 2.3 CPU Core System clock controller TMP89FM42 SET (EIRL). 4 ;Enables INTWUC interrupts SET (SYSCR2) .6 ;SYSCR2 = 1 ;(Starts the oscillation of the high-frequency clock oscillation circuit) ¦ ; #### Interrupt service routine of warm-up counter interrupts #### PINTWUC: CLR (SYSCR2). 4 ;SYSCR2 = 0 ;(Switches the main system clock to the gear clock) NOP ;Waits for 2 machine cycles NOP CLR (SYSCR2). 5 ;SYSCR2 = 0 ;(Turns off the low-frequency clock oscillation circuit) RETI ¦ VINTWUC: DW PINTWUC ;INTWUC vector table Page 38 RB000 TMP89FM42 2.4 Reset Control Circuit The reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 Configuration The reset control circuit consists of the following reset signal generation circuits: 1. 2. 3. 4. 5. 6. 7. 8. External reset input (external factor) Power-on reset (internal factor) Voltage detection reset 1 (internal factor) Voltage detection reset 2 (internal factor) Watchdog timer reset (internal factor) System clock reset (internal factor) Trimming data reset (internal factor) Flash standby reset (internal factor) P10(RESET) P10 port Internal factor reset detection status register, Voltage detection circuit reset signal External reset input enable reset signal Power-on reset signal Voltage detection reset 1 signal Voltage detection reset 2 signal Warm-up counter Watchdog timer reset signal Warm-up counter reset signal System clock reset signal CPU/peripheral circuits reset signal System clock control circuit Trimming data reset signal Flash standby reset signal Figure 2-14 Reset Control Circuit 2.4.2 Control The reset control circuit is controlled by system control register 3 (SYSCR3), system control register 4 (SYSCR4), system control status register (SYSSR4) and the internal factor reset detection status register (IRSTSR). System control register 3 7 SYSCR3 (0x0FDE) 6 5 4 3 2 1 0 Bit Symbol - - - - - (RVCTR) (RAREA) RSTDIS Read/Write R R R R R R/W R/W R/W After reset 0 0 0 0 0 0 0 0 RSTDIS External reset input enable register 0: Enables the external reset input. 1: Disables the external reset input. Note 1: The enabled SYSCR3 is initialized by a power-on reset only, and cannot be initialized by an external reset input or internal factor reset. The value written in SYSCR3 is reset by a power-on reset, external reset input or internal factor reset. Note 2: The value of SYSCR3 is invalid until 0xB2 is written into SYSCR4. Page 39 RB000 2. 2.4 CPU Core Reset Control Circuit TMP89FM42 Note 3: After SYSCR3 is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3) in NORMAL1 mode when fcgck is fc/4 (CGCR=00). Otherwise, SYSCR3 may be enabled at unexpected timing. Note 4: Bits 7 to 3 of SYSCR3 are read as "0". System control register 4 7 SYSCR4 (0x0FDF) 6 5 4 Bit Symbol SYSCR4 2 1 0 0 0 0 0 SYSCR4 Read/Write After reset 3 W 0 0 0 Writes the SYSCR3 data control code. 0 0xB2 : Enables the contents of SYSCR3 0xD4 : Enables the contents of SYSCR3 and SYSCR3 0x71 : Enables the contents of IRSTSR Others : Invalid Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation. Note 2: After SYSCR3 is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3) in NORMAL mode when fcgck is fc/4 (CGCR=00). Otherwise, SYSCR3 may be enabled at unexpected timing. Note 3: After IRSTSR is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR in NORMAL mode when fcgck is fc/4 (CGCR=00). Otherwise, IRSTSR may be enabled at unexpected timing. System control status register 4 7 SYSSR4 (0x0FDF) 6 5 4 3 2 1 0 Bit Symbol - - - - - (RVCTRS) (RAREAS) RSTDISS Read/Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 RSTDISS External reset input enable status 0: The enabled SYSCR3 data is "0". 1: The enabled SYSCR3 data is "1". Note 1: The enabled SYSCR3 is initialized by a power-on reset only, and cannot be initialized by any other reset signals. The value written in SYSCR3 is reset by a power-on reset and other reset signals. Note 2: Bits 7 to 3 of SYSCR4 are read as "0". Page 40 RB000 TMP89FM42 Internal factor reset detection status register 7 6 5 4 3 2 1 0 Bit Symbol FCLR FLSRF TRMDS TRMRF LVD2RF LVD1RF SYSRF WDTRF Read/Write W R R R R R R R After reset 0 0 0 0 0 0 0 0 IRSTSR (0x0FCC) FCLR Flag initialization control 0: - 1: Clears the internal factor reset flag to "0". 0: - 1: Detects the flash standby reset. 0: - 1: Detect state of abnormal trimming data 0: - 1: Detects the trimming data reset. FLSRF Flash standby reset detection flag TRMDS Trimming data status TRMRF Trimming data reset detection flag LVD2RF Voltage detection reset 2 detection flag 0: - 1: Detects the voltage detection 2 reset. LVD1RF Voltage detection reset 1 detection flag 0: - 1: Detects the voltage detection 1 reset. 0: - 1: Detects the system clock reset. 0: - 1: Detects the watchdog timer reset. SYSRF WDTRF System clock reset detection flag Watchdog timer reset detection flag Note 1: Internal reset factor flag (IRSTSR) is initialized only by a power-on reset, an external reset input or IRSTSR . It is not initialized by an internal factor reset. Note 2: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other effects. Note 3: If SYSCR4 is set to 0x71 after IRSTSR is set to "1", internal factor reset flag is cleared to "0" and IRSTSR is automatically cleared to "0". Note 4: After IRSTSR is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR in NORMAL mode when fcgck is fc/4 (CGCR=00). Otherwise, IRSTSR may be enabled at unexpected timing. Note 5: Bit 7 of IRSTSR is read as "0". 2.4.3 Functions The power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of the clock generator. During reset, the warm-up counter circuit is reset, and the CPU and the peripheral circuits are reset. After reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the warm-up operation that follows reset release. During the warm-up operation that follows reset release, the trimming data is loaded from the non-volatile exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the poweron reset and the voltage detection circuits. When the warm-up operation that follows reset release is finished, the CPU starts execution of the program from the reset vector address stored in addresses 0xFFFE to 0xFFFF. When a reset signal is input during the warm-up operation that follows reset release, the warm-up counter circuit is reset. The reset operation is common to the power-on reset, external reset input and internal factor resets, except for the initialization of some special function registers and the initialization of the voltage detection circuits. When a reset is applied, the peripheral circuits become the states as shown in Table 2-5. Page 41 RB000 2. 2.4 CPU Core Reset Control Circuit TMP89FM42 Table 2-5 Initialization of Built-in Hardware by Reset Operation and Its Status after Release Built-in hardware Program counter (PC) Stack pointer (SP) During reset During the warm-up operation that follows reset release Immediately after the warm-up operation that follows reset release MCU mode: MCU mode: MCU mode: 0xFFFE 0xFFFE 0xFFFE Serial PROM mode: 0x1FFE Serial PROM mode: 0x1FFE Serial PROM mode: 0x1FFE 0x00FF 0x00FF 0x00FF RAM Indeterminate Indeterminate Indeterminate General-purpose registers (W, A, B, C, D, E, H, L, IX and IY) Indeterminate Indeterminate Indeterminate Register bank selector (RBS) 0 0 0 Jump status flag (JF) Indeterminate Indeterminate Indeterminate Zero flag (ZF) Indeterminate Indeterminate Indeterminate Carry flag (CF) Indeterminate Indeterminate Indeterminate Half carry flag (HF) Indeterminate Indeterminate Indeterminate Sign flag (SF) Indeterminate Indeterminate Indeterminate Overflow flag (VF) Indeterminate Indeterminate Indeterminate Interrupt master enable flag (IMF) 0 0 0 Individual interrupt enable flag (EF) 0 0 0 Interrupt latch (IL) 0 0 0 High-frequency clock oscillation circuit Oscillation enabled Oscillation enabled Oscillation enabled Low-frequency clock oscillation circuit Oscillation disabled Oscillation disabled Oscillation disabled Reset Start Stop Warm-up counter Timing generator prescaler and divider Watchdog timer Voltage detection circuit I/O port pin status Special function register 0 0 0 Disabled Disabled Enabled Disabled or enabled Disabled or enabled Disabled or enabled HiZ HiZ HiZ Refer to the SFR map. Refer to the SFR map. Refer to the SFR map. Note:The voltage detection circuits are disabled by an external reset input or power-on reset only. Page 42 RB000 TMP89FM42 2.4.4 Reset Signal Generating Factors Reset signals are generated by each factor as follows: 2.4.4.1 Power-on reset The power-on reset is an internal reset that occurs when power is turned on. During power-up, a power-on reset signal is generated while the supply voltage is below the power-on reset release voltage. When the supply voltage rises above the power-on reset release voltage, the power-on reset signal is released. During power-down, a power-on reset signal is generated when the supply voltage falls below the poweron reset detection voltage. Refer to "Power-on Reset circuit". 2.4.4.2 External reset input (RESET pin input) This is an external reset that is generated by the RESET pin input. Port P10 is also used as the RESET pin, and it is configured as the RESET pin at power-up. ・ During power-up - When the supply voltage rises rapidly When the power supply rise time (tVDD) is shorter than 5 [ms] with enough margin, the reset can be released by a power-on reset or an external reset (RESET pin input). The power-on reset logic and external reset (RESET pin input) logic are ORed. This means that the TMP89FM42 is reset when either or both of these reset sources are asserted. Therefore, the reset time is determined by the reset source with a longer reset period. If the RESET pin level changes from Low to High before the supply voltage rises above the power-on-reset release voltage (VPROFF) (or if the RESET pin level is High from the beginning), the reset time depends on the power-on reset. If the RESET pin level changes from Low to High after the supply voltage rises above VPROFF, the reset time depends on the external reset. In the former case, a warm-up period begins when the power-on reset signal is released. In the latter case, a warm-up period begins when the RESET pin level becomes High. Upon completion of the warm-up period, the CPU and peripheral circuits start operating (Figure 2-15). - When the supply voltage rises slowly When the power supply rise time (tVDD) is longer than 5 [ms], the reset must be released by using the RESET pin. In this case, hold the RESET pin Low until the supply voltage rises to the operating voltage range and oscillation is stabilized. When this state is achieved, wait at least 5 [μs] and then pull the RESET pin High. Changing the RESET pin level to High starts a warm-up period. Upon completion of the warm-up period, the CPU and peripheral circuits start operating (Figure 2-15). Page 43 RB000 2. 2.4 CPU Core Reset Control Circuit TMP89FM42 tVDD Operating voltage range VPROFF Power-on reset RESET pin CPU and peripheral circuits start operating CPU and peripheral circuits reset Warm-up period (tPWUP) When the supply voltage rises rapidly (When the reset time depends on power-on reset) tVDD Operating voltage range VPROFF Power-on reset RESET pin CPU and peripheral circuits reset CPU and peripheral circuits start operating Warm-up period (tPWUP) When the supply voltage rises rapidly (When the reset time depends on external reset) tVDD Operating voltage range VPROFF Power-on reset 5µs or more RESET pin CPU and peripheral circuits start operating CPU and peripheral circuits reset Warm-up period (tPWUP) When the supply voltage rises slowly Figure 2-15 External Reset Input (During Power-Up) Page 44 RB000 TMP89FM42 ・ When the supply voltage is within the operating voltage range When the supply voltage is within the operating voltage range and stable oscillation is achieved, holding the RESET pin Low for 5 [μs] or longer generates a reset. Then, changing the RESET pin level to High starts a warm-up period. Upon completion of the warm-up period, the CPU and peripheral circuits start operating (Figure 2-16). Operating voltage range 5µs or more RESET pin CPU and peripheral circuits reset CPU and peripheral circuits start operating Warm-up period (tPWUP) Figure 2-16 External Reset Input (When the Power Supply Is Stable) 2.4.4.3 Voltage detection reset The voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage has reached a predetermined detection voltage. Refer to "Voltage Detection Circuit". 2.4.4.4 Watchdog timer reset The watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer is detected. Refer to "Watchdog Timer". 2.4.4.5 System clock reset The system clock reset is an internal factor reset that occurs when it is detected that the oscillation enable register is set to a combination that puts the CPU into deadlock. Refer to "Clock Control Circuit". 2.4.4.6 Trimming data reset The trimming data reset is an internal factor reset that occurs when the trimming data latched in the internal circuit is broken down during operation due to noise or other factors. The trimming data is a data bit provided for adjustment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits. This bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows reset release (tPWUP) and latched into the internal circuit. If the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation that follows reset release is abnormal, IRSTSR is set to "1". Page 45 RB000 2. 2.4 CPU Core Reset Control Circuit TMP89FM42 When IRSTSR is read as "1" in the initialize routine immediately after reset release, the trimming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and activating the warm-up operation again. If IRSTSR is still set to "1" after repeated reading, the detection voltage of the voltage detection circuit and power-on reset circuit does not satisfy the characteristic specified in the electric characteristics. Design the system so that the system will not be damaged in such a case. 2.4.4.7 Flash standby reset The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash memory while it is on standby. Refer to "Flash Memory". 2.4.4.8 Internal factor reset detection status register By reading the internal factor reset detection status register IRSTSR after the release of an internal factor reset, except the power-on reset, the factor which causes a reset can be detected. The internal factor reset detection status register is initialized by an external reset input or power-on reset. Set IRSTSR to "1" and write 0x71 to SYSCR4. This enables IRSTSR and the internal factor reset detection status register is clear to "0". IRSTSR is cleared to "0" automatically after initializing the internal factor reset detection status register. Note 1: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other effects. Note 2: After IRSTSR is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR in NORMAL mode when fcgck is fc/4 (CGCR=00). Otherwise, IRSTSR may be enabled at unexpected timing. 2.4.4.9 How to use the external reset input pin as a port To use the external reset input pin as a port, keep the external reset input pin at the "H" level until the power is turned on and the warm-up operation that follows reset release is finished. After the warm-up operation that follows reset release is finished, set P1PU0 to "1" and P1CR0 to "0", and connect a pull-up resistor for a port. Then set SYSCR3 to "1" and write 0xB2 to SYSCR4. This disables the external reset function and makes the external reset input pin usable as a normal port. To use the pin as an external reset pin when it is used as a port, set P1PU0 to "1" and P1CR0 to "0" and connect the pull-up resistor to put the pin to the input mode. Then clear SYSCR3 to "0" and write 0xB2 to SYSCR4. This enables the external reset function and makes the pin usable as the external reset input pin. Note 1: If you switch the external reset input pin to a port or switch the pin used as a port to the external reset input pin, do it when the pin is stabilized at the "H" level. Switching the pin function when the "L" level is input may cause a reset. Note 2: If the external reset input is used as a port, the statement which clears SYSCR3 to "0" is not written in a program. By the abnormal execution of program, the external reset input set as a port may be changed as the external reset input at unexpected timing. Note 3: After SYSCR3 is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3) in NORMAL1 mode when fcgck is fc/4 (CGCR=00). Otherwise, SYSCR3 may be enabled at unexpected timing. Page 46 RB000 TMP89FM42 2.5 Revision History Rev RA002 Description "Table 2-3 Operation Modes and Conditions" Added AD converter condition. "(2) Release the STOP mode" Added new example program and note to Level-sensitive release mode. "Table 2-3 Operation Modes and Conditions" Revised character code error. RA003 "Table 2-3 Operation Modes and Conditions" Added AD converter condition. "(2) Release the STOP mode" Added new example program. "2.3.6 Operation Mode Control" Revised register name from VDCR2 to VDCR2. RA004 "Table 2-5 Initialization of Built-in Hardware by Reset Operation and Its Status after Release" Revised PC address of Serial PROM mode. " Internal factor reset detection status register" Revised Note. "2.4.4.2 External reset input (RESET pin input)" Revised description. "2.2.1.2 BOOTROM", "2.2.2.3 BOOTROM" Revised description. RB000 Revised P03 (XTIN) and P04 (XTOUT) to P02 (XTIN) and P03 (XTOUT). Deleted SRSS function. Page 47 RB000 2. 2.5 CPU Core Revision History TMP89FM42 Page 48 RB000 TMP89FM42 3. Interrupt Control Circuit The TMP89FM42 has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Three of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vector addresses. When a request for an interrupt is generated, its interrupt latch is set to "1", which requests the CPU to accept the interrupt. Acceptance of interrupts is enabled or disabled by software using the interrupt master enable flag (IMF) and individual enable flag (EF) for each interrupt source. If multiple maskable interrupts are generated simultaneously, the interrupts are accepted in order of descending priority. The priorities are determined by the interrupt priority change control register (ILPRS1-ILPRS6) as Levels and determined by the hardware as the basic priorities. However, there are no prioritized interrupt sources among non-maskable interrupts. Vector Address Interrupt sources Enable condition (MCU mode) RVCTR=0 RVCTR=1 enabled enabled Basic priority Internal/External (Reset) Non-maskable - 0xFFFE - 1 Internal INTSWI Non-maskable - 0xFFFC 0x01FC 2 Internal INTUNDEF Non-maskable - 0xFFFC 0x01FC 2 Internal INTWDT Non-maskable ILL 0xFFF8 0x01F8 2 Internal INTWUC IMF AND EIRL = 1 ILL 0xFFF6 0x01F6 5 Internal INTTBT IMF AND EIRL = 1 ILL 0xFFF4 0x01F4 6 Internal INTRXD0 / INTSIO0 IMF AND EIRL = 1 ILL 0xFFF2 0x01F2 7 8 Internal INTTXD0 IMF AND EIRL = 1 ILL 0xFFF0 0x01F0 External INT5 IMF AND EIRH = 1 ILH 0xFFEE 0x01EE 9 Internal INTVLTD IMF AND EIRH = 1 ILH 0xFFEC 0x01EC 10 Internal INTADC IMF AND EIRH = 1 ILH 0xFFEA 0x01EA 11 Internal INTRTC IMF AND EIRH = 1 ILH 0xFFE8 0x01E8 12 Internal INTTC00 IMF AND EIRH = 1 ILH 0xFFE6 0x01E6 13 Internal INTTC01 IMF AND EIRH = 1 ILH 0xFFE4 0x01E4 14 Internal INTTCA0 IMF AND EIRH = 1 ILH 0xFFE2 0x01E2 15 Internal INTSBI0/INTSIO0 IMF AND EIRH = 1 ILH 0xFFE0 0x01E0 16 External INT0 IMF AND EIRE = 1 ILE 0xFFDE 0x01DE 17 External INT1 IMF AND EIRE = 1 ILE 0xFFDC 0x01DC 18 External INT2 IMF AND EIRE = 1 ILE 0xFFDA 0x01DA 19 External INT3 IMF AND EIRE = 1 ILE 0xFFD8 0x01D8 20 External INT4 IMF AND EIRE = 1 ILE 0xFFD6 0x01D6 21 Internal INTTCA1 IMF AND EIRE = 1 ILE 0xFFD4 0x01D4 22 Internal INTRXD1 IMF AND EIRE = 1 ILE 0xFFD2 0x01D2 23 Internal INTTXD1 IMF AND EIRE = 1 ILE 0xFFD0 0x01D0 24 Internal INTTC02 IMF AND EIRD = 1 ILD 0xFFCE 0x01CE 25 Internal INTTC03 IMF AND EIRD = 1 ILD 0xFFCC 0x01CC 26 - - - - - - - - - - - - - - Page 49 RA003 Interrupt latch 3. Interrupt Control Circuit TMP89FM42 Note 1: To use the watchdog timer interrupt (INTWDT), clear WDCTR to "0" (It is set for the "Reset request" after reset is released). For details, see "Watchdog Timer". Note 2: Vector address areas can be changed by the SYSCR3 setting. To assign vector address areas to RAM, set SYSCR3 to "1" and SYSCR3 to "1". Note 3: 0xFFFA and 0xFFFB function not as interrupt vectors but as option codes in the serial PROM mode. For details, see "Serial PROM Mode". Note 4: Do not set SYSCR3 to "0" in the serial PROM mode. If an interrupt is generated with SYSCR3 ="0", the software refers to the vector area in the BOOTROM and the user cannot use it. Page 50 RA003 RA003 Page 51 Figure 3-1 Interrupt Control Circuit Interrupt source25 Interrupt source 20 Interrupt source 19 Interrupt source 18 Interrupt source 17 Interrupt source 16 Interrupt source 15 Interrupt source 14 Interrupt source 13 Interrupt source 12 Interrupt source 11 Interrupt source 10 Interrupt source 9 Interrupt source 8 Interrupt source 7 Interrupt source 6 Interrupt source 5 Interrupt source 4 INTWDT INTSWI INTUNDEF ILPRS1 ILPRS2 ILPRS3 ILPRS4 ILPRS6 IL4 clear signal IL4 vector read signal IL3 vector read signal Internal factor reset R S R S IL4 IL3 Q Q IL25 to IL4 reading Data bus EF25 to EF4 IL25 IL21 IL20 IL19 IL18 IL17 IL16 IL15 IL14 IL13 IL12 IL11 IL10 IL9 IL8 IL7 IL6 IL5 IL4 A 3 2 B 1 0 EN Decoder IL3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Maskable interrupt priority change circuit Address bus 25 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 IMF Q Interrupt request IDLE1/2,SLEEP1/2 Mode clear request [RETN] instruction (only when the IMF is set to “1” before interrupt acceptance) Instruction to write “1” to IMF [EI] instruction [RET1]1 instruction (only when the IMF is set to “1” before interrupt acceptance) Instruction to write “0” to IMF DI instruction Internal factor reset Interrupt accept IMF (Interrupt master enable flag) R S Vector address generation Maskable interrupts 3.1 Non-maskable interrupts Priority encoder TMP89FM42 Configuration 3. 3.2 Interrupt Control Circuit Interrupt Latches (IL25 to IL3) 3.2 TMP89FM42 Interrupt Latches (IL25 to IL3) An interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruction execution interrupt. When an interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its acceptance is enabled. The interrupt latch is cleared to "0" immediately after the interrupt is accepted. All interrupt latches are initialized to "0" during reset. The interrupt latches are located at addresses 0x0FE0, 0x0FE1, 0x0FE2, 0x0FE3 in SFR area. Each latch can be cleared to "0" individually by an instruction. However, IL2 and IL3 interrupt latches cannot be cleared by instructions. Do not use any read-modify-write instruction, such as a bit manipulation or operation instruction, because it may clear interrupt requests generated while the instruction is executed. Interrupt latches cannot be set to "1" by using an instruction. Writing "1" to an interrupt latch is equivalent to denying clearing of the interrupt latch, and not setting the interrupt latch. Since interrupt latches can be read by instructions, the status of interrupt requests can be monitored by software. Note:In the main program, before manipulating an interrupt latch (IL), be sure to clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI instruction). In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1". Example 1:Clears interrupt latches DI ;IMF ← 0 LD (ILL), 0y00111111 ;IL7 to IL6 ← 0 LD (ILH), 0y11101000 ;IL12, IL10 to IL8 ← 0 EI ;IMF ← 1 Example 2:Reads interrupt latches LD WA, (ILL) ;W ← ILH, A ← ILL Example 3:Tests interrupt latches TEST (ILL). 7 ;if IL7=1 then jump JR F, SSET ; Page 52 RA003 TMP89FM42 3.3 Interrupt Enable Register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). Non-maskable interrupts are accepted regardless of the contents of the EIR. The EIR consists of the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located at addresses 0x003A, 0x003B, 0x003C, 0x003D in the SFR area, and they can be read and written by instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.3.1 Interrupt master enable flag (IMF) The interrupt master enable flag (IMF) enables and disables the acceptance of all maskable interrupts. Clearing the IMF to "0" disables the acceptance of all maskable interrupts. Setting the IMF to "1" enables the acceptance of the interrupts that are specified by the individual interrupt enable flags. When an interrupt is accepted, the IMF is stacked and then cleared to "0", which temporarily disables the subsequent maskable interrupts. After the interrupt service routine is executed, the stacked data, which was the status before interrupt acceptance, reloaded on the IMF by return interrupt instruction [RETI]/[RETN]. The IMF is located on bit 0 in EIRL (Address: 0x03A in SFR), and can be read and written by instructions. The IMF is normally set and cleared by [EI] and [DI] instructions respectively. During reset, the IMF is initialized to "0". 3.3.2 Individual interrupt enable flags (EF25 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags are initialized to "0" and no maskable interrupts are accepted until the flags are set to "1". Note:In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF (Enable interrupt by EI instruction). In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to "1". Example:Enables interrupts individually and sets IMF DI LDW ;IMF ← 0 (EIRL), 0y1110100010100000 ;Note: IMF should not be set. EI ;IMF ← 1 Page 53 RA003 ;EF15 to EF13, EF11, EF7, EF5 ← 1 : : 3. 3.3 Interrupt Control Circuit Interrupt Enable Register (EIR) TMP89FM42 Interrupt latch (ILL) 7 ILL (0x0FE0) 6 5 4 3 2 1 0 Bit Symbol IL7 IL6 IL5 IL4 IL3 - - - Read/Write R/W R/W R/W R/W R R R R 0 0 0 After reset 0 0 0 0 0 INTTXD0 INTRXD0 / INTSIO0 INTTBT INTWUC INTWDT 7 6 5 4 3 2 1 0 Bit Symbol IL15 IL14 IL13 IL12 IL11 IL10 IL9 IL8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function INTSBI0/INTSIO0 INTTCA0 INTTC01 INTTC00 INTRTC INTADC INTVLTD INT5 Function Interrupt latch (ILH) ILH (0x0FE1) Interrupt latch (ILE) 7 6 5 4 3 2 1 0 Bit Symbol IL23 IL22 IL21 IL20 IL19 IL18 IL17 IL16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function INTTXD1 INTRXD1 INTTCA1 INT4 INT3 INT2 INT1 INT0 7 6 5 4 3 2 1 0 ILE (0x0FE2) Interrupt latch (ILD) ILD (0x0FE3) Bit Symbol - - - - - - IL25 IL24 Read/Write R R R R R R R/W R/W After reset 0 0 0 0 0 0 Function Read 0: No interrupt request 1: Interrupt request 0: No interrupt request 1: Interrupt request 0 0 INTTC03 INTTC02 Write Clears the interrupt request (Notes 2 and 3) IL25 to IL4 Interrupt latch Does not clear the interrupt request (Interrupt is not set by writing "1".) IL3 - Note 1: IL3 is a read-only register. Writing the register does not affect interrupt latch. Note 2: In the main program, before manipulating an interrupt latch (IL), be sure to clear the interrupt master enable flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI instruction). In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Note 4: When a read instruction is executed on ILL, bits 0 to 2 are read as "0". Other unused bits are read as "0". Page 54 RA003 TMP89FM42 Interrupt enable register (EIRL) 7 EIRL (0x003A) 6 5 4 3 2 0 1 Bit Symbol EF7 EF6 EF5 EF4 - - - IMF Read/Write R/W R/W R/W R/W R R R R/W 0 0 0 After reset 0 0 0 0 INTTXD0 INTRXD0 / INTSIO0 INTTBT INTWUC 7 6 5 4 3 2 1 0 Bit Symbol EF15 EF14 EF13 EF12 EF11 EF10 EF9 EF8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function INTSBI0/INTSIO0 INTTCA0 INTTC01 INTTC00 INTRTC INTADC INTVLTD INT5 Function 0 Interrupt master enable flag Interrupt enable register (EIRH) EIRH (0x003B) Interrupt enable register (EIRE) 7 6 5 4 3 2 1 0 Bit Symbol EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function INTTXD1 INTRXD1 INTTCA1 INT4 INT3 INT2 INT1 INT0 6 5 4 3 2 1 0 EIRE (0x003C) Interrupt enable register (EIRD) 7 EIRD (0x003D) Bit Symbol - - - - - - EF25 EF24 Read/Write R R R R R/W R/W R/W R/W After reset 0 0 0 0 0 0 Function EF25 to EF4 IMF 0 0 INTTC03 INTTC02 Individual interrupt enable flag 0: Disables the acceptance of each maskable interrupt. (Specified for each bit) 1: Enables the acceptance of each maskable interrupt. 0: Disables the acceptance of all maskable interrupts. 1: Enables the acceptance of all maskable interrupts. Interrupt master enable flag Note 1: Do not set the IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 2: In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF (Enable interrupt by EI instruction) In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to "1". Note 3: When a read instruction is executed on EIRL, bits 3 to 1 are read as "0". Other unused bits are read as "0". Page 55 RA003 3. 3.4 Interrupt Control Circuit Maskable Interrupt Priority Change Function 3.4 TMP89FM42 Maskable Interrupt Priority Change Function The priority of maskable interrupts (IL4 to IL25) can be changed to four levels, Levels 0 to 3, regardless of the basic priorities 5 to 26. Interrupt priorities can be changed by the interrupt priority change control register (ILPRS1 to ILPRS6). To raise the interrupt priority, set the Level to a larger number. To lower the interrupt priority, set the Level to a smaller number. When different maskable interrupts are generated simultaneously at the same level, the interrupt with higher basic priority is processed preferentially. For example, when the ILPRS1 register is set to 0xC0 and interrupts IL4 and IL7 are generated at the same time, IL7 is preferentially processed (provided that EF4 and EF7 have been enabled). After reset is released, all maskable interrupts are set to priority level 0 (the lowest priority). Note:In the main program, before manipulating the interrupt priority change control register (ILPRS1 to 6), be sure to clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction). Set the IMF to "1" as required after operating ILPRS1 to 6 (Enable interrupt by EI instruction). In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate ILPRS1 to 6 before setting the IMF to "1". Interrupt priority change control register 1 7 ILPRS1 (0x0FF0) Bit Symbol 5 IL07P Read/Write After reset 6 3 IL06P R/W 0 4 0 1 IL05P R/W 0 2 IL04P R/W 0 0 IL07P Sets the interrupt priority of IL7. 00: Level 0 (lower priority) IL06P Sets the interrupt priority of IL6. 01: Level 1 IL05P Sets the interrupt priority of IL5. 10: Level 2 IL04P Sets the interrupt priority of IL4. 11: Level 3 (higher priority) 0 R/W 0 0 0 2 1 0 Interrupt priority change control register 2 7 ILPRS2 (0x0FF1) 6 5 4 3 Bit Symbol IL11P IL10P IL09P IL08P Read/Write R/W R/W R/W R/W After reset 0 0 0 0 0 IL11P Sets the interrupt priority of IL11. 00: Level 0 (lower priority) IL10P Sets the interrupt priority of IL10. 01: Level 1 IL09P Sets the interrupt priority of IL9. 10: Level 2 IL08P Sets the interrupt priority of IL8. 11: Level 3 (higher priority) 0 0 0 2 1 0 Interrupt priority change control register 3 7 ILPRS3 (0x0FF2) 6 5 4 Bit Symbol IL15P IL14P IL13P IL12P Read/Write R/W R/W R/W R/W After reset 0 0 0 0 0 IL15P Sets the interrupt priority of IL15. 00: Level 0 (lower priority) IL14P Sets the interrupt priority of IL14. 01: Level 1 IL13P Sets the interrupt priority of IL13. 10: Level 2 IL12P Sets the interrupt priority of IL12. 11: Level 3 (higher priority) Page 56 RA003 3 0 0 0 TMP89FM42 Interrupt priority change control register 4 7 ILPRS4 (0x0FF3) Bit Symbol 6 5 IL19P Read/Write 0 3 IL18P R/W After reset 4 0 1 IL17P R/W 0 2 IL16P R/W 0 0 IL19P Sets the interrupt priority of IL19. 00: Level 0 (lower priority) IL18P Sets the interrupt priority of IL18. 01: Level 1 IL17P Sets the interrupt priority of IL17. 10: Level 2 IL16P Sets the interrupt priority of IL16. 11: Level 3 (higher priority) 0 R/W 0 0 2 1 0 Interrupt priority change control register 5 7 ILPRS5 (0x0FF4) Bit Symbol 6 5 IL23P Read/Write R/W After reset 0 4 3 IL22P IL21P R/W 0 0 R/W 0 0 IL23P Sets the interrupt priority of IL23. 00: Level 0 (lower priority) IL22P Sets the interrupt priority of IL22. 01: Level 1 IL21P Sets the interrupt priority of IL21. 10: Level 2 IL20P Sets the interrupt priority of IL20. 11: Level 3 (higher priority) 0 IL20P R/W 0 0 0 2 1 0 Interrupt priority change control register 6 7 ILPRS6 (0x0FF5) 6 5 4 Bit Symbol - - IL25P IL24P Read/Write R/W R/W R/W R/W After reset 0 0 0 0 0 - - 00: Level 0 (lower priority) - - 01: Level 1 IL25P Sets the interrupt priority of IL25. 10: Level 2 IL24P Sets the interrupt priority of IL24. 11: Level 3 (higher priority) Page 57 RA003 3 0 0 0 3. 3.5 Interrupt Control Circuit Interrupt Sequence 3.5 TMP89FM42 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). 3.5.1 Initial Setting Using an interrupt requires specifying an SP (stack pointer) for it in advance. The SP is a 16-bit register pointing at the start address of a stack. The SP is post-decremented when a subroutine call or a push instruction is executed or when an interrupt request is accepted. It is pre-incremented when a return or pop instruction is executed. Therefore, the stack becomes deeper toward lower stack location addresses. Be sure to reserve a stack area having an appropriate size based on the SP setting. The SP is initialized to 00FFH after a reset. If you need to change the SP, do so right after a reset or when the interrupt master enable flag (IMF) is “0”. Example :SP setting 3.5.2 LD SP, 023FH ; SP = 023FH LD SP, SP+04H ; SP = SP + 04H ADD SP, 0010H ; SP = SP + 0010H Interrupt acceptance processing Interrupt acceptance processing is packaged as follows. 1. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt. 2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”. 3. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. 4. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of register bank and IMF are also saved. Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Vector table address 0xFFF4 0x03 0xD203 0x0F 0xFFF5 0xD2 0xD204 0x06 Figure 3-2 Vector table address and Entry address Page 58 RA003 TMP89FM42 A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt is requested in the interrupt service routine. In order to utilize nested interrupt service, the IMF must be set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests. 3.5.3 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the general purpose registers are not. These registers must be saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the general-purpose registers. 3.5.3.1 Using PUSH and POP instructions To save only a specific register, PUSH and POP instructions are available. Example :Using PUSH and POP instructions PUSH PINTxx WA ; Save WA register WA ; Restore WA register Interrupt processing POP RETI ; RETURN Address (Example) SP A SP W b-4 SP b-3 PCL PCL PCL PCH PCH PCH PSW PSW PSW At Acceptance of an Interrupt At execution of PUSH instruction At execution of POP instruction b-2 b-1 SP b At execution of an RETI instruction Figure 3-3 Saving/restoring general-purpose registers Page 59 RA003 3. 3.5 Interrupt Control Circuit Interrupt Sequence TMP89FM42 3.5.3.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register A, (GSAVA) ; Restore A register Interrupt processing LD RETI ; RETURN Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.5.3.3 Using a register bank to save/restore general-purpose registers In non-multiple interrupt handling, the register bank function can be used to save/restore the generalpurpose registers at a time. The register bank function saves (switches) the general-purpose registers by executing a register bank manipulation instruction (such as LD RBS,1) at the beginning of an interrupt service task. It is unnecessary to re-execute the register bank manipulation instruction at the end of the interrupt service task because executing the RETI instruction makes a return automatically to the register bank that was being used by the main task according to the content of the PSW. Note:Two register banks (BANK0 and BANK1) are available. Each bank consists of 8-bit general-purpose registers (W, A, B, C, D, E, H, and L) and 16-bit general-purpose registers (IX and IY). Example :Saving/restoring registers, using an instruction for transfer with data memory (with the main task using the register bank BANK0) PINTxx: LD RBS, 1 ; Switches to the register bank BANK1 Interrupt processing RETI ; RETURN (Makes a return automatically to BANK0 that was being used by the main task when the PSW is restored) Page 60 RA003 TMP89FM42 Main task Interrupt acceptance Interrupt service task The register bank BANK0 is in use. LD (RBS),1 Switching occurs to the register bank BANK1. Interrupt return A return is made automatically to the register bank BANK0. Figure 3-5 Saving/Restoring General-purpose Registers under Interrupt Processing 3.5.4 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (register bank) are restored from tha stack. 2. Stack pointer (SP) is incremented by 3. Page 61 RA003 3. 3.6 Interrupt Control Circuit Software Interrupt (INTSW) 3.6 TMP89FM42 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is the top-priority interrupt). Use the SWI instruction only for address error detection or for debugging described below. 3.6.1 Address error detection 0xFF is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address. Code 0xFF is an SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing 0xFF to unused areas in the program memory. 3.6.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.7 Undefined Instruction Interrupt (INTUNDEF) When the CPU tries to fetch and execute an instruction that is not defined, INTUNDEF is generated and starts the interrupt processing. INTUNDEF is accepted even if another non-maskable interrupt is in process. The current process is discontinued and the INTUNDEF interrupt process starts soon after it is requested. Note:The undefined instruction interrupt (INTUNDEF) forces the CPU to jump into the interrupt vector address, as software interrupt (SWI) does. Page 62 RA003 TMP89FM42 3.8 Revision History Rev Description Revised from WDTCR1 to WDCTR RA003 Added chapter "3.5 Interrupt Sequence" "Figure 3-3 Saving/restoring general-purpose registers" Revised SP position Page 63 RA003 3. 3.8 Interrupt Control Circuit Revision History TMP89FM42 Page 64 RA003 TMP89FM42 4. External Interrupt control circuit External interrupts detects the change of the input signal and generates an interrupt request. Noise can be removed by the built-in digital noise canceller. 4.1 Configuration The external interrupt control circuit consists of a noise canceller, an edge detection circuit, a level detection circuit and an interrupt signal generation circuit. Externally input signals are input to the rising edge or falling edge or level detection circuit for each external interrupt, after noise is removed by the noise canceller. INTj pin Noise canceller Falling edge detection circuit Interrupt request signal generation circuit INTj interrupt request j=0,5 fcgck fs/4 Figure 4-1 External Interrupts 0/5 INTi pin Rising edge detection circuit Noise canceller fs/4 Z A B C DS Falling edge detection circuit Interrupt request signal generation circuit INTi interrupt request i=1 to 3 INTiES INTiLVL fcgck 1 2 3 4 EINTCRi Figure 4-2 External Interrupts 1/2/3 Rising edge detection circuit INT4 pin Noise canceller fs Z Falling edge detection circuit Level detection circuit Interrupt request signal generation circuit A B C DS INT4ES INT4LVL fcgck 1 2 3 4 EINTCR4 Figure 4-3 External Interrupt 4 4.2 Control External interrupts are controlled by the following registers: Page 65 RA000 INT4 interrupt request 4. 4.2 External Interrupt control circuit Control TMP89FM42 Low power consumption register 3 7 POFFCR3 (0x0F77) 6 5 4 3 2 1 0 Bit Symbol - - INT5EN INT4EN INT3EN INT2EN INT1EN INT0EN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 INT5EN INT4EN INT3EN INT2EN INT5 control INT4 control INT3 control INT2 control INT1EN INT1 control INT0EN INT0 control 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable Note 1: Clearing INTxEN(x=0 to 5) to "0" stops the clock supply to the external interrupts. This invalidates the data written in the control register for each external interrupt. When using the external interrupts, set INTxEN to "1" and then write data into the control register for each external interrupt. Note 2: Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. Note 3: Bits 7 and 6 of POFFSET3 are read as "0". External interrupt control register 1 7 6 5 4 Bit Symbol - - - INT1LVL INT1ES INT1NC Read/Write R R R R R/W R/W After reset 0 0 0 0 0 0 EINTCR1 (0x0FD8) INI1LVL INT1ES Noise canceller pass signal level when the interrupt request signal is generated for external interrupt 1 Selects the interrupt request generating condition for external interrupt 1 3 2 0: Initial state or signal level "L" 1: Signal level "H" Sets the noise canceller sampling interval for external interrupt 1 0 00 : An interrupt request is generated at the rising edge of the noise canceller pass signal 01 : An interrupt request is generated at the falling edge of the noise canceller pass signal 10 : An interrupt request is generated at both edges of the noise canceller pass signal 11 : Reserved 00 : fcgck [Hz] 00 : fs/4 [Hz] 01 : fcgck / 22 [Hz] 01 : fs/4 [Hz] 10 : fcgck / 23 [Hz] 10 : fs/4 [Hz] 11 : fcgck / 24 [Hz] 11 : fs/4 [Hz] NORMAL1/2, IDLE1/2 INT1NC 1 SLOW1/2, SLEEP1 Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. Page 66 RA000 TMP89FM42 Note 3: Interrupt requests may be generated when EINTCR1 is changed. Before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. Note 4: Bits 7 to 5 of EINTCR1 are read as "0". External interrupt control register 2 7 EINTCR1 (0x0FD9) 6 5 4 3 2 1 0 Bit Symbol - - - INT2LVL INT2ES INT2NC Read/Write R R R R R/W R/W After reset 0 0 0 0 0 0 INI2LVL INT2ES Noise canceller pass signal level when the interrupt request signal is generated for external interrupt 2 Selects the interrupt request generating condition for external interrupt 2 0: Initial state or signal level "L" 1: Signal level "H" 00 : An interrupt request is generated at the rising edge of the noise canceller pass signal 01 : An interrupt request is generated at the falling edge of the noise canceller pass signal 10 : An interrupt request is generated at both edges of the noise canceller pass signal 11 : Reserved NORMAL1/2, IDLE1/2 INT2NC Sets the noise canceller sampling interval for external interrupt 2 SLOW1/2, SLEEP1 00 : fcgck [Hz] 00 : fs/4 [Hz] 01 : fcgck / 22 [Hz] 01 : fs/4 [Hz] 10 : fcgck / 23 [Hz] 10 : fs/4 [Hz] 11 : fcgck / 24 [Hz] 11 : fs/4 [Hz] Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. Note 3: Interrupt requests may be generated when EINTCR2 is changed. Before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. Note 4: Bits 7 to 5 of EINTCR2 are read as "0". Page 67 RA000 4. 4.2 External Interrupt control circuit Control TMP89FM42 External interrupt control register 3 7 6 5 4 Bit Symbol - - - INT3LVL INT3ES INT3NC Read/Write R R R R R/W R/W After reset 0 0 0 0 0 0 EINTCR3 (0x0FDA) INI3LVL INT3ES Noise canceller pass signal level when the interrupt request signal is generated for external interrupt 3 Selects the interrupt request generating condition for external interrupt 3 3 2 0: Initial state or signal level "L" 1: Signal level "H" Sets the noise canceller sampling interval for external interrupt 3 0 00 : An interrupt request is generated at the rising edge of the noise canceller pass signal 01 : An interrupt request is generated at the falling edge of the noise canceller pass signal 10 : An interrupt request is generated at both edges of the noise canceller pass signal 11 : Reserved 00 : fcgck [Hz] 00 : fs/4 [Hz] 01 : fcgck / 22 [Hz] 01 : fs/4 [Hz] 10 : fcgck / 23 [Hz] 10 : fs/4 [Hz] 11 : fcgck / 24 [Hz] 11 : fs/4 [Hz] NORMAL1/2, IDLE1/2 INT3NC 1 SLOW1/2, SLEEP1 Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. Note 3: Interrupt requests may be generated when EINTCR3 is changed. Before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. Note 4: Bits 7 to 5 of EINTCR3 are read as "0". Page 68 RA000 TMP89FM42 External interrupt control register 4 7 6 5 4 Bit Symbol - - - INT4LVL INT4ES INT4NC Read/Write R R R R R/W R/W After reset 0 0 0 0 0 0 EINTCR4 (0x0FDB) INI4LVL INT4ES Noise canceller pass signal level when the interrupt request signal is generated for external interrupt 4 Selects the interrupt request generating condition for external interrupt 4 3 2 0: Initial state or signal level "L" 1: Signal level "H" Sets the noise canceller sampling interval for external interrupt 4 0 00 : An interrupt request is generated at the rising edge of the noise canceller pass signal 01 : An interrupt request is generated at the falling edge of the noise canceller pass signal 10 : An interrupt request is generated at both edges of the noise canceller pass signal 11 : An interrupt request is generated at "H" of the noise canceller pass signal 00 : fcgck [Hz] 00 : fs/4 [Hz] 01 : fcgck / 22 [Hz] 01 : fs/4 [Hz] 10 : fcgck / 23 [Hz] 10 : fs/4 [Hz] 11 : fcgck / 24 [Hz] 11 : fs/4 [Hz] NORMAL1/2, IDLE1/2 INT4NC 1 SLOW1/2, SLEEP1 Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. Note 3: Interrupt requests may be generated when EINTCR4 is changed. Before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/ fspl [s] after the operation mode is changed and clear the interrupt latch. Note 4: The contents of EINTCRx are updated each time an interrupt request signal is generated. Note 5: Bits 7 to 5 of EINTCR4 are read as "0". 4.3 Function The condition for generating interrupt request signals and the noise cancel time can be set for external interrupts 1 to 4. The condition for generating interrupt request signals and the noise cancel time are fixed for external interrupts 0 and 5. Page 69 RA000 4. 4.3 External Interrupt control circuit Function TMP89FM42 Table 4-1 External Interrupts Source Pin Enable conditions External interrupt pin input signal width and noise removal Interrupt request signal generated at NORMAL1/2, IDLE1/2 Less than 1/fcgck: Noise INT0 INT0 INT1 IMF AND EF16 = 1 Falling edge IMF AND EF17 = 1 Rising edge Both edges Falling edge INT2 INT2 IMF AND EF18 = 1 Rising edge Both edges Falling edge INT3 INT3 IMF AND EF19 = 1 Rising edge Both edges INT4 INT4 INT5 INT5 IMF AND EF20 = 1 IMF AND EF8 = 1 Less than 4/fs: Noise More than 1/fcgck and less than 2/fcgck: More than 4/fs and less than 8/fs: IndeIndeterminate terminate Falling edge INT1 SLOW1/2, SLEEP1 More than 2/fcgck: Signal More than 8/fs: Signal Less than 2/fspl: Noise Less than 4/fs: Noise More than 2/fspl and less than 3/fspl+1/ fcgck: Indeterminate More than 4/fs and less than 8/fs: Indeterminate More than 3/fspl+1/fcgck: Signal More than 8/fs: Signal Less than 2/fspl: Noise Less than 4/fs: Noise More than 2/fspl and less than 3/fspl+1/ fcgck: Indeterminate More than 4/fs and less than 8/fs: Indeterminate More than 3/fspl+1/fcgck: Signal More than 8/fs: Signal Less than 2/fspl: Noise Less than 4/fs: Noise More than 2/fspl and less than 3/fspl+1/ fcgck: Indeterminate More than 4/fs and less than 8/fs: Indeterminate More than 3/fspl+1/fcgck: Signal More than 8/fs: Signal Falling edge Less than 2/fspl: Noise Less than 4/fs: Noise Rising edge Both edges More than 2/fspl and less than 3/fspl+1/ fcgck: Indeterminate More than 4/fs and less than 8/fs: Indeterminate "H" level More than 3/fspl+1/fcgck: Signal More than 8/fs: Signal Less than 1/fcgck: Noise Less than 4/fs: Noise More than 1/fcgck and less than 2/fcgck: More than 4/fs and less than 8/fs: IndeIndeterminate terminate Falling edge More than 2/fcgck: Signal More than 8/fs: Signal Note 1: fcgck, Gear clock [Hz]; fs, low frequency clock [Hz]; fspl, Sampling interval [Hz] 4.3.1 Low power consumption function External interrupts have a function that saves power by using the low power consumption register (POFFCR3) when they are not used. Setting POFFCR3 to "0" stops (disables) the basic clock for external interrupts and helps save power. Note that this makes external interrupts unavailable. Setting POFFCR3 to "1" supplies (enables) the basic clock for external interrupts and makes external interrupts available. After reset, POFFCR3 is initialized to "0" and external interrupts become unavailable. When using the external interrupt function for the first time, be sure to set POFFCR3 to "1" in the initial setting of software (before operating the external interrupt control registers). Note:Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.2 External interrupt 0 External interrupt 0 detects the falling edge of the INT0 pin and generates interrupt request signals. In NORMAL1/2 or IDLE1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. In SLOW/SLEEP mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized as signals. Page 70 RA000 TMP89FM42 4.3.3 External interrupts 1/2/3 External interrupts 1/2/3 detect the falling edge, the rising edge or both edges of the INT1, INT2 and INT3 pins and generate interrupt request signals. 4.3.3.1 Interrupt request signal generating condition detection function Select interrupt request signal generating conditions at EINTCRx for external interrupts 1/2/3. Table 4-2 Selection of Interrupt Request Generation Edge EINTCRx Detected at 00 Rising edge 01 Falling edge 10 Both edges 11 Reserved Note:x=1 to 3 4.3.3.2 A noise canceller pass signal monitoring function when interrupt request signals are generated The level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using EINTCRx. When both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading EINTCRx. INTi pin Signal that has passed through the noise canceller Interrupt request signal (detected at the falling edge) INT LVL Interrupt request signal (detected at the rising edge) INT LVL Interrupt request signal (detected at both edges) INT LVL Note:The contents of EINTCRx are updated each time an interrupt request signal is generated. Figure 4-4 Interrupt Request Generation and EINTCRx 4.3.3.3 Noise cancel time selection function In NORMAL1/2 or IDLE1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at EINTCRx. If the same level is detected three consecutive times, the signal is recognized as a signal. If not, the signal is removed as noise. Page 71 RA000 4. 4.3 External Interrupt control circuit Function TMP89FM42 Table 4-3 Noise Canceller Sampling Lock EINTCRx Sampling interval 00 fcgck 01 fcgck/22 10 fcgck/23 11 fcgck/24 INTi pin i=1 to 3 Signal Noise Signal after noise removal Figure 4-5 Noise Cancel Operation In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided by 4. If the same level is detected twice consecutively, the signal is recognized as a signal. In IDLE0, SLEEP0 or STOP mode, the noise canceller sampling operation is stopped and an external interrupts are unavailable. When operation returns to NORMAL1/2, IDLE1/2, SLOW1/2 or SLEEP1 mode, sampling operation restarts. Note 1: If noise is input consecutively during sampling of external interrupt pins, the noise cancel function does not work properly. Set EINTCRx according to the cycle of externally input noise. Note 2: If an external interrupt pin is used as an output port, the input signal to the port is fixed to "L" when the mode is switched to the output mode, and thus an interrupt request occurs. To use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. Note 3: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.4 External interrupt 4 External interrupt 4 detects the falling edge, the rising edge, both edges or "H" level of the INT4 pin and generates interrupt request signals. 4.3.4.1 Interrupt request signal generating condition detection function Select an interrupt request signal generating condition at EINTCR4 for external interrupt 4. Table 4-4 Selection of Interrupt Request Generation Edge EINTCR4 Detected at 00 Rising edge 01 Falling edge 10 Both edges 11 "H" level interrupt Page 72 RA000 TMP89FM42 4.3.4.2 A noise canceller pass signal monitoring function when interrupt request signals are generated The level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using EINTCR4. When both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading EINTCR4. INT4 pin Signal that has passed through the noise canceller Interrupt request signal (detected at the falling edge) INT4LVL Interrupt request signal (detected at the rising edge) INT4LVL Interrupt request signal (detected at both edges) INT4LVL Interrupt request signal (level detection) INT4LVL Figure 4-6 Interrupt Request Generation and EINTCR4 4.3.4.3 Noise cancel time selection function In NORMAL1/2 or IDLE1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at EINTCRx. If the same level is detected three consecutive times, the signal is recognized as a signal. If not, the signal is removed as noise. Table 4-5 Noise Canceller Sampling Lock EINTCR4 Sampling interval 00 fcgck 01 fcgck/22 10 fcgck/23 11 fcgck/24 Page 73 RA000 4. 4.3 External Interrupt control circuit Function TMP89FM42 Signal INT4 pin Noise Signal after noise removal Figure 4-7 Noise Cancel Operation In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided by 4. If the same level is detected twice consecutively, the signal is recognized as a signal. In IDLE0, SLEEP0 or STOP mode, the noise canceller sampling operation is stopped and an external interrupts are unavailable. When operation returns to NORMAL1/2, IDLE1/2, SLOW1/2 or SLEEP1 mode, sampling operation restarts. Note 1: When noise is input consecutively during sampling external interrupt pins, the noise cancel function does not work properly. Set EINTCRx according to the cycle of externally input noise. Note 2: When an external interrupt pin is used as an output port, the input signal to the port is fixed to "L" when the mode is switched to the output mode, and thus an interrupt request occurs. To use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. Note 3: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.5 External interrupt 5 External interrupt 5 detects the falling edge of the INT5 pin and generates interrupt request signals. In NORMAL1/2 or IDLE1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. In SLOW/SLEEP mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized as signals. Page 74 RA000 TMP89FM42 5. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request signals or watchdog timer reset signals. Note:Care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturbing noise and other effects. Configuration 10 fcgck/2 or fs/23 12 fcgck/2 or fs/25 14 fcgck/2 or fs/27 16 fcgck/2 or fs/29 Selector 5.1 Source clock 2 8-bit up counter 3 4 5 6 7 8 Interrupt request/reset signal control circuit Overflow Clear 2 8 CPU/peripheral circuits reset Clear time control circuit Disable control circuit Disable code (0xB1) Clear code (0x4E) WDST Figure 5-1 Watchdog Timer Configuration Page 75 RA000 WDTST WINTST2 WDCTR WINTST1 WDTT WDTOUT WDCDR WDTW WDCNT WDTEN Control code decoder Watchdog timer interrupt requestl Watchdog timer reset signal 5. 5.2 Watchdog Timer (WDT) Control TMP89FM42 5.2 Control The watchdog timer is controlled by the watchdog timer control register (WDCTR), the watchdog timer control code register (WDCDR), the watchdog timer counter monitor (WDCNT) and the watchdog timer status (WDST). The watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished. Watchdog timer control register 7 6 5 Bit Symbol - - WDTEN WDTW WDTT WDTOUT Read/Write R R R/W R/W R/W R/W After reset 1 0 1 WDCTR (0x0FD4) WDTEN WDTW Enables/disables the watchdog timer operation. Sets the clear time of the 8-bit up counter. 4 3 0 0: Disable 1: Enable 2 0 1 1 1 WDTOUT Sets the overflow time of the 8-bit up counter. 0 00 : The 8-bit up counter is cleared by writing the clear code at any point within the overflow time of the 8-bit up counter. 01 : A watchdog timer interrupt request is generated by writing the clear code at a point within the first quarter of the overflow time of the 8-bit up counter. The 8-bit up counter is cleared by writing the clear code after the first quarter of the overflow time has elapsed. 10 : A watchdog timer interrupt request is generated by writing the clear code at a point within the first half of the overflow time of the 8-bit up counter. The 8-bit up counter is cleared by writing the clear code after the first half of the overflow time has elapsed. 11 : A watchdog timer interrupt request is generated by writing the clear code at a point within the first three quarters of the overflow time of the 8-bit up counter. The 8-bit up counter is cleared by writing the clear code after the first three quarters of the overflow time have elapsed. NORMAL mode WDTT 0 SLOW mode DV9CK=0 DV9CK=1 00 : 218/fcgck 211/fs 211/fs 01: 2 fcgck 2 /fs 213/fs 10: 222/fcgck 215/fs 215/fs 11: 2 /fcgck 2 /fs 217/fs Selects an overflow detection signal of the 8-bit up counter. 20/ 13 24 17 0: Watchdog timer interrupt request signal 1: Watchdog timer reset request signal Note 1: fcgck, Gear clock [Hz]; fs, Low frequency clock [Hz] Note 2: WDCTR, WDCTR and WDCTR cannot be changed when WDCTR is "1". If WDCTR is "1", clear WDCTR to "0" and write the disable code (0xB1) into WDCDR to disable the watchdog timer operation. Note that WDCTR, WDCTR and WDCTR can be changed at the same time as setting WDCTR to "1". Note 3: Bit 7 and bit 6 of WDCTR are read as "1" and "0" respectively. Watchdog timer control code register 7 WDCDR (0x0FD5) 6 5 4 Bit Symbol WDTCR2 Read/Write W After reset WDTCR2 0 0 Writes watchdog timer control codes. 0 0 2 1 0 0 0 0 0 0x4E : Clears the watchdog timer. (Clear code) 0xB1 : Disables the watchdog timer operation and clears the 8-bit up counter when WDCTR is "0". (Disable code) Others : Invalid Page 76 RA000 3 TMP89FM42 Note:WDCDR is a write-only register and must not be accessed by using a read-modify-write instruction, such as a bit operation. 8-bit up counter monitor 7 WDCNT (0x0FD6) 6 5 4 Bit Symbol WDCNT Read/Write R After reset WDCNT 0 0 Monitors the count value of the 8-bit up counter 0 0 3 2 1 0 0 0 0 0 The count value of the 8-bit up counter is read. Watchdog timer status 7 6 5 4 3 2 1 0 Bit Symbol - - - - - WINTST2 WINTST1 WDTST Read/Write R R R R R R R R After reset 0 1 0 1 1 0 0 1 WDST (0x0FD7) WINTST2 Watchdog timer interrupt request signal factor status 2 WINTST1 Watchdog timer interrupt request signal factor status 1 WDTST Watchdog timer operating state status 0: No watchdog timer interrupt request signal has occurred. 1: A watchdog timer interrupt request signal has occurred due to the overflow of the 8-bit up counter. 0: No watchdog timer interrupt request signal has occurred. 1: A watchdog timer interrupt request signal has occurred due to releasing of the 8-bit up counter outside the clear time. 0: Operation disabled 1: Operation enabled Note 1: WDST and WDST are cleared to "0" by reading WDST. Note 2: Values after reset are read from bits 7 to 3 of WDST. Page 77 RA000 5. 5.3 Watchdog Timer (WDT) Functions 5.3 TMP89FM42 Functions The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8-bit up counter and detecting releasing of the 8-bit up counter outside the clear time. The watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up counter at random times and comparing the value to the last read value. 5.3.1 Setting of enabling/disabling the watchdog timer operation Setting WDCTR to "1" enables the watchdog timer operation, and the 8-bit up counter starts counting the source clock. WDCTR is initialized to "1" after the warm-up operation that follows reset is released. This means that the watchdog timer is enabled. To disable the watchdog timer operation, clear WDCTR to "0" and write 0xB1 into WDCDR. Disabling the watchdog timer operation clears the 8-bit up counter to "0". Note:If the overflow of the 8-bit up counter occurs at the same time as 0xB1 (disable code) is written into WDCDR with WDCTR set at "1", the watchdog timer operation is disabled preferentially and the overflow detection is not executed. To re-enable the watchdog timer operation, set WDCTR to "1". There is no need to write a control code into WDCDR. Watchdog timer source clock 8-bit up counter value 0x00 0xFF 0x01 0x00 WDCTR Overflow time WDCTR Overflow time Interrupt request signal 1 clock (max.) Figure 5-2 WDCTR Set Timing and Overflow Time Note:The 8-bit up counter source clock operates out of synchronization with WDCTR. Therefore, the first overflow time of the 8-bit up counter after WDCTR is set to "1" may get shorter by a maximum of 1 source clock. The 8-bit up counter must be cleared within the period of the overflow time minus 1 source clock cycle. 5.3.2 Setting the clear time of the 8-bit up counter WDCTR sets the clear time of the 8-bit up counter. When WDCTR is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the 8-bit up counter can be cleared at any time. When WDCTR is not "00", the clear time is fixed to only a certain period within the overflow time of the 8-bit up counter. If the operation for releasing the 8-bit up counter is attempted outside the clear time, a watchdog timer interrupt request signal occurs. At this time, the watchdog timer is not cleared but continues counting. If the 8-bit up counter is not cleared within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs due to the overflow, depending on the WDCTR setting. Page 78 RA000 TMP89FM42 8-bit up counter value 0xFF 0x00 0x01 0x3F 0x40 When WDCTR is “00” When WDCTR is “01” When WDCTR is “10” 0x7F 0x80 0xBF 0xC0 0xFF 0x00 Clear time Outside the clear time Clear time Outside the clear time Clear time Outside the clear time When WDCTR is “11” Clear time Figure 5-3 WDCTR and the 8-bit up Counter Clear Time 5.3.3 Setting the overflow time of the 8-bit up counter WDCTR sets the overflow time of the 8-bit up counter. When the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs, depending on the WDCTR setting. If the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog counter continues counting, even after the overflow has occurred. The watchdog timer temporarily stops counting up in the STOP mode (including warm-up) or in the IDLE/ SLEEP mode, and restarts counting up after the STOP/IDLE/SLEEP mode is released. To prevent the 8-bit up counter from overflowing immediately after the STOP/IDLE/SLEEP mode is released, it is recommended to clear the 8-bit up counter before the operation mode is changed. Table 5-1 Watchdog Timer Overflow Time (fcgck=10.0 MHz; fs=32.768 kHz) Watchdog timer overflow time [s] NORMAL mode WDTT SLOW DV9CK = 0 DV9CK = 1 mode 00 26.21 m 62.50 m 62.50 m 01 104.86 m 250.00 m 250.00 m 10 419.43 m 1.000 1.000 11 1.678 4.000 4.000 Note:The 8-bit up counter source clock operates out of synchronization with WDCTR. Therefore, the first overflow time of the 8-bit up counter after WDCTR is set to "1" may get shorter by a maximum of 1 source clock. The 8-bit up counter must be cleared within a period of the overflow time minus 1 source clock cycle. 5.3.4 Setting an overflow detection signal of the 8-bit up counter WDCTR selects a signal to be generated when the overflow of the 8-bit up counter is detected. 1. When the watchdog timer interrupt request signal is selected (when WDCTR is "0") Releasing WDCTR to "0" causes a watchdog timer interrupt request signal to occur when the 8-bit up counter overflows. A watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regardless of the interrupt master enable flag (IMF) setting. Note: When a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is already accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put on hold. Therefore, if watchdog timer interrupts are generated continuously without execution of the RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller. Page 79 RA000 5. 5.3 Watchdog Timer (WDT) Functions TMP89FM42 2. When the watchdog timer reset request signal is selected (when WDCTR is "1") Setting WDCTR to "1" causes a watchdog timer reset request signal to occur when the 8-bit up counter overflows. This watchdog timer reset request signal resets the TMP89FM42 and starts the warm-up operation. 5.3.5 Writing the watchdog timer control codes The watchdog timer control codes are written into WDCDR. By writing 0x4E (clear code) into WDCDR, the 8-bit up counter is cleared to "0" and continues counting the source clock. When WDCTR is "0", writing 0xB1 (disable code) into WDCDR disables the watchdog timer operation. To prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the overflow time of the 8-bit up counter and within the clear time. By designing the program so that no overflow will occur, the program malfunctions and deadlock can be detected through interrupts generated by watchdog timer interrupt request signals. By applying a reset to the microcomputer using watchdog timer reset request signals, the CPU can be restored from malfunctions and deadlock. Example: When WDCTR is "0", set the watchdog timer detection time to 220/fcgck [s], set the counter clear time to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is detected. LD (WDCTR), 0y00110011 ;WDTW←10, WDTT←01, WDTOUT←1 LD (WDCDR), 0x4E ;Clear the 8-bit up counter LD (WDCDR), 0x4E ;Clear the 8-bit up counter Clear the 8-bit up counter at a point after half of its overflow time and within a period of the overflow time minus 1 source clock cycle. Clear the 8-bit up counter at a point after half of its overflow time and within a period of the overflow time minus 1 source clock cycle. Note:If the overflow of the 8-bit up counter and writing of 0x4E (clear code) into WDCDR occur simultaneously, the 8-bit up counter is cleared preferentially and the overflow detection is not executed. 5.3.6 Reading the 8-bit up counter The counter value of the 8-bit up counter can be read by reading WDCNT. The stoppage of the 8-bit up counter can be detected by reading WDCNT at random times and comparing the value to the last read value. 5.3.7 Reading the watchdog timer status The watchdog timer status can be read at WDST. WDST is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when the watchdog timer operation is disabled. WDST is set to "1" when a watchdog timer interrupt request signal occurs due to the overflow of the 8-bit up counter. Page 80 RA000 TMP89FM42 WDST is set to "1" when a watchdog timer interrupt request signal occurs due to the operation for releasing the 8-bit up counter outside the clear time. You can know which factor has caused a watchdog timer interrupt request signal by reading WDST and WDST in the watchdog timer interrupt service routine. WDST and WDST are cleared to "0" when WDST is read. If WDST is read at the same time as the condition for turning WDST or WDST to "1" is satisfied, WDST or WDST is set to "1", rather than being cleared. 8-bit up counter value 0xFF 0x00 0x01 When WDCTR is “10” 0x3F 0x40 0x7F 0x80 Outside the clear time 0xBF 0xC0 0xFF 0x00 0x01 Clear time Writing of 4EH (clear code) Reading of WDST Interrupt request signal generated by clearing the 8-bit up counter outside the clear time Interrupt request signal generated by the overflow of the 8-bit up counter Watchdog timer interrupt request signal WDST WDST Figure 5-4 Changes in the Watchdog Timer Status Page 81 RA000 5. 5.3 Watchdog Timer (WDT) Functions TMP89FM42 Page 82 RA000 TMP89FM42 6. Power-on Reset Circuit The power-on reset circuit generates a reset when the power is turned on. When the supply voltage is lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated. 6.1 Configuration The power-on reset circuit consists of a reference voltage generation circuit and a comparator. The supply voltage divided by ladder resistor is compared with the voltage generated by the reference voltage generation circuit by the comparator. VDD Comparator Power-on reset signal Reference voltage generation circuit Figure 6-1 Power-on Reset Circuit 6.2 Function When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the power-on reset circuit, a power-on reset signal is generated and if it is higher than the releasing voltage of the poweron reset circuit, a power-on reset signal is released. When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting voltage of the power-on reset circuit, a power-on reset signal is generated. Until the power-on reset signal is generated, a warm-up circuit and a CPU is reset. When the power-on reset signal is released, the warm-up circuit is activated. The reset of the CPU and peripheral circuits is released after the warm-up time that follows reset release has elapsed. Increase the supply voltage into the operating range during the period from detection of the power-on reset release voltage until the end of the warm-up time that follows reset release. If the supply voltage has not reached the operating range by the end of the warm-up time that follows reset release, the TMP89FM42 cannot operate properly. Page 83 RA000 6. 6.2 Power-on Reset Circuit Function TMP89FM42 Supply voltage (VDD) Operating voltage VPROFF VPRON PPW VDD Power-on reset signal PRON PROFF Warm-up counter start Warm-up counter clock PWUP CPU/peripheral circuits reset signal Note 1: The power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer to the electrical characteristics and take them into consideration when designing equipment. Note 2: For the AC timing, refer to the electrical characteristics. Figure 6-2 Operation Timing of Power-on Reset Page 84 RA000 TMP89FM42 7. Voltage Detection Circuit The voltage detection circuit detects any decrease in the supply voltage and generates INTVLTD interrupt request signals and voltage detection reset signals. Note:The voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer to the electrical characteristics and take them into consideration when designing equipment. 7.1 Configuration The voltage detection circuit consists of a reference voltage generation circuit, a detection voltage level selection circuit, a comparator and control registers. The supply voltage (VDD) is divided by the ladder resistor and input to the detection voltage selection circuit. The detection voltage selection circuit selects a voltage according to the specified detection voltage (VDxLVL) (x = 1 or 2), and the comparator compares it with the reference voltage. When the comparator detects the selected voltage, a voltage detection reset signal or an INTVLTD interrupt request signal can be generated. Whether to generate a voltage detection reset signal or an INTVLTD interrupt request signal can be programmed by software. In the former case, a voltage detection reset signal is generated when the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL). In the latter case, an INTVLTD interrupt request signal is generated when the supply voltage (VDD) falls to the detection voltage level. Note:Since the comparators used for voltage detection do not have a hysteresis structure, INTVLTD interrupt request signals may be generated frequently if the supply voltage (VDD) is close to the detection voltage (VDxLVL). INTVLTD interrupt request signals may be generated not only when the supply voltage falls to the detection voltage but also when it rises to the detection voltage. Detection voltage 1 level selection circuit VDD F/F − Voltage detection reset signal 1 + Detection voltage 2 level selection circuit Interrupt request signal generation circuit F/F − Voltage detection reset signal 2 + VD1EN VD1MOD VD2EN VD2MOD VD2F VD2SF VD1F VD1SF VD1LVL VD2LVL Reference voltage generation circuit VDCR1 VDCR2 Internal bus Figure 7-1 Voltage Detection Circuit Page 85 RB000 INTVLTD interrupt request signal 7. 7.2 Voltage Detection Circuit Control TMP89FM42 7.2 Control The voltage detection circuit is controlled by voltage detection control registers 1 and 2. Voltage detection control register 1 7 6 Bit Symbol VD2F VD2SF Read/Write R/W Read Only After reset 0 0 VDCR1 (0x0FC6) VD2F Voltage detection 2 flag (Retains the state when VDD to "1" and read the received data from the SBI0DBR (Reading data is undefined immediately after a slave address is sent). After the data is read, SBI0CR2 becomes "1" by writing the dummy data (0x00) to the SBI0DBR. The serial bus interface circuit outputs a serial clock pulse to the SCL0 pin to transfer the subsequent 1-word data and sets the SDA0 pin to "0" at the acknowledge signal timing. An interrupt request occurs and SBI0CR2 becomes "0". Then a serial bus interface circuit outputs a clock pulse for 1-word data transfer and the acknowledge signal by writing data to the SBI0DBR or setting SBI0CR2 to "1" after reading the received data. Read SBI0DBR Write to SBI0DBR SCL0 pin SDA0 pin 9 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 9 New D7 Acknowledge signal to the transmitter SBI0CR2 INTSBI0 Interrupt request Figure 18-19 Example when SBI0CR1="000" and SBI0CR1="1" To make the transmitter terminate transmission, execute following procedure before receiving a last data. 1. Read the received data. 2. Clear SBI0CR1 to "0" and set SBI0CR1 to "000". 3. To set SBI0CR2 to "1", write a dummy data (0x00) to SBI0DBR. Transfer 1-word data in which no clock is generated for an acknowledge signal by setting SBI0CR2 to "1". Next, execute following procedure. 1. Read the received data. 2. Clear SBI0CR1 to "0" and set SBI0CR1 to "001". Page 292 RA002 TMP89FM42 3. To set SBI0CR2 to "1", write a dummy data (0x00) to SBI0DBR. Transfer 1-bit data by setting SBI0CR1 to "1". In this case, since the master device is a receiver, the SDA line on a bus keeps the high level. The transmitter receives the high-level signal as a negative acknowledge signal. The receiver indicates to the transmitter that data transfer is complete. After 1-bit data is received and an interrupt request has occurred, generate the stop condition to terminate data transfer. SCL0 pin 9 SDA0 pin 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Negative acknowledge signal to the transmitter SBI0CR INTSBI0 Interrupt request After reading the received data, clear SBI0CR1 to "0" and writing the dummy data (0x00) After reading the reveived data, set SBI0CR1 to "001" and write dummy data (0x00) Figure 18-20 Termination of Data Transfer in the Master Receiver Mode 18.5.3.2 When SBI0SR2 is "0" (Slave mode) In the slave mode, a serial bus interface circuit operates either in the normal slave mode or in the slave mode after losing arbitration. In the slave mode, the conditions of generating the serial bus interface interrupt request (INTSBI0) are follows: ・ At the end of the acknowledge signal when the received slave address matches the value set by the I2C0AR with SBI0CR1 set at "0" ・ At the end of the acknowledge signal when a "GENERAL CALL" is received with SBI0CR1 set at "0" ・ At the end of transferring or receiving after matching of slave address or receiving of "GENERAL CALL" The serial bus interface circuit changes to the slave mode if arbitration is lost in the master mode. And an interrupt request occurs when the word data transfer terminates after losing arbitration. The generation of the interrupt request and the behavior of SBI0CR2 after losing arbitration are shown in Table 18-4. Table 18-4 The Behavior of an interrupt request and SBI0CR2 After Losing Arbitration When the Arbitration Lost Occurs during Transmission When the Arbitration Lost Occurs during Transmission of Slave Address as a Master of Data as Master Transmitter interrupt request An interrupt request is generated at the termination of word-data transfer. SBI0CR2 SBI0CR2 is cleared to "0". When an interrupt request occurs, SBI0CR2 is reset to "0", and the SCL0 pin is set to the low level. Either writing data to the SBI0DBR or setting SBI0CR2 to "1" releases the SCL0 pin after taking tLOW. Page 293 RA002 18. 18.5 Serial Bus Interface (SBI) Data Transfer of I2C Bus TMP89FM42 Check SBI0SR2, SBI0SR2, SBI0SR2 and SBI0SR2 and implement processes according to conditions listed in Table 18-5. Table 18-5 Operation in the Slave Mode SBI0SR2< SBI0SR2< SBI0SR2< SBI0SR2< TRX> AL> AAS> AD0> 1 1 0 1 0 1 Conditions Process The serial bus interface circuit loses arbitration when transmitting a slave address, and receives a slave address of which the value of the direction bit sent from another Set the number of bits in 1 word to master is "1". SBI0CR1 and write the transmitted In the slave receiver mode, the serial bus data to the SBI0DBR. interface circuit receives a slave address of which the value of the direction bit sent from the master is "1". 0 Check SBI0SR2. If it is set to "1", set SBI0CR2 to "1" since the receiver does not request subsequent data. Then, In the slave transmitter mode, the serial clear SBI0CR2 to "0" to release the bus interface circuit finishes the transmis- bus. If SBI0SR2 is set to "0", set the sion of 1-word data number of bits in 1 word to SBI0CR1 and write the transmitted data to SBI0DBR since the receiver requests subsequent data. 1/0 The serial bus interface circuit loses arbitration when transmitting a slave address, Write the dummy data (0x00) to the and receives a slave address of which the SBI0DBR to set SBI0CR2 to "1", or value of the direction bit sent from another write "1" to SBI0CR2. master is "0" or receives a "GENERAL CALL". 0 The serial bus interface circuit is changed The serial bus interface circuit loses arbito the slave mode. Write the dummy data tration when transmitting a slave address (0x00) to the SBI0DBR to clear or data, and terminates transferring the SBI0SR2 to "0" and set word data. SBI0CR2 to "1". 1 1/0 In the slave receiver mode, the serial bus interface circuit receives a slave address Write the dummy data (0x00) to the of which the value of the direction bit sent SBI0DBR to set SBI0CR2 to "1", or from the master is "0" or receives "GEN- write "1" to SBI0CR2. ERAL CALL". 0 1/0 Set the number of bits in 1-word to In the slave receiver mode, the serial bus SBI0CR1, read the received data interface circuit terminates the receipt of from the SBI0DBR and write the dummy 1-word data. data (0x00). 0 0 1 1 0 0 0 Note:In the slave mode, if the slave address set in I2C0AR is "0x00", a START Byte "0x01" in I2C bus standard is received, the device detects slave address match and SBI0CR2 is set to "1". Do not set I2C0AR to "0x00". 18.5.4 Stop condition generation When SBI0CR2 is "1", a sequence of generating a stop condition is started by setting "1" to SBI0CR2, SBI0CR2 and SBI0CR2 and clearing SBI0CR2 to "0". Do not modify the contents of SBI0CR2, SBI0CR2, SBI0CR2 and SBI0CR2 until a stop condition is generated on a bus. When a SCL line on a bus is pulled down by other devices, a serial bus interface circuit generates a stop condition after a SCL line is released. The time from the releasing SCL line until the generating the STOP condition takes tHIGH. Page 294 RA002 TMP89FM42 Example :Generate the stop condition CHK_BB: LD (SBI0CR2), 0xD8 ; Sets SBI0CR2, and to "1" and SBI0CR2 to "0" TEST (SBI0SR2).BB ;Waits until the bus is set free JR T, CHK_BB SBI0CR2="1" SBI0CR2="1" SBI0CR2="0" SBI0CR2="1" If the SCL of the bus is pulled down by other devices, the stop condition is generated after it is released Stop condition SCL0 pin SCL (Bus) SDA0 pin SBI0CR2 SBI0SR2 Figure 18-21 Stop Condition Generation 18.5.5 Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart the serial bus interface circuit. Clear SBI0CR2, SBI0CR2 and SBI0CR2 to "0" and set SBI0CR2 to "1". The SDA0 pin retains the high level and the SCL0 pin is released. Since this is not a stop condition, the bus is assumed to be in a busy state from other devices. Check SBI0SR2 until it becomes "0" to check that the SCL0 pin of the serial bus interface circuit is released. Check SBI0SR2 until it becomes "1" to check that the SCL line on the bus is not pulled down to the low level by other devices. After confirming that the bus stays in a free state, generate a start condition in the procedure "18.5.2 Start condition and slave address generation". In order to meet the setup time at a restart, take at least 4.7μs of waiting time by the software in the standard mode I2C bus standard or at least 0.6μs of waiting time in the fast mode I2C bus standard from the time of restarting to confirm that a bus is free until the time to generate a start condition. Note:When the master is in the receiver mode, it is necessary to stop the data transmission from the slave device before the STOP condition is generated. To stop the transmission, the master device make the slave device receiving a negative acknowledge. Therefore, SBI0SR2 is "1" before generating the Restart and it can not be confirmed that SCL line is not pulled down by other devices. Please confirm the SCL line state by reading the port. Page 295 RA002 18. 18.5 Serial Bus Interface (SBI) Data Transfer of I2C Bus TMP89FM42 Example :Generate a restart CHK_BB: CHK_LRB: LD (SBI0CR2), 0x18 ; Sets SBI0CR2, and to "0" and SBI0CR2 to "1" TEST (SBI0SR2).BB ; Waits until SBI0SR2 becomes "0" JR T, CHK_BB TEST (SBI0SR2).LRB JR F, CHK_LRB ; Waits until SBI0SR2 becomes "1" . . ; Wait time process by the software . LD (SBI0CR2), 0xf8 ; Sets SBI0CR2, , and to "1" SBI0CR2="0" SBI0CR2="0" SBI0CR2="0" SBI0CR2="1" SBI0CR2="1" SBI0CR2="1" SBI0CR2="1" SBI0CR2="1" 4.7 µs min. in the normal mode or 0.6 µs min. in the fast mode SCL (Bus) SCL0 pin SDA0 pin SBI0SR2 SBI0SR2 SBI0CR2 Figure 18-22 Timing Diagram When Restarting Page 296 RA002 Start condition TMP89FM42 18.6 AC Specifications The AC specifications are as listed below. The operating mode (fast or standard) mode should be selected suitable for frequency of fcgck. For these operating mode, refer to the following table. Table 18-6 AC Specifications (Circuit Output Timing) Parameter Standard mode Symbol Fast mode Unit MIN. MAX. MIN. MAX. fSCL 0 fcgck / (m+n) 0 fcgck / (m+n) kHz Hold time (re)start condition. This period is followed by generation of the first clock pulse. tHD;STA m / fcgck - m / fcgck - μs Low-level period of SCL clock (output) tLOW n / fcgck - n / fcgck - μs High-level period of SCL clock (output) tHIGH m / fcgck - m / fcgck - μs Low-level period of SCL clock (input) tLOW 5 / fcgck - 5 / fcgck - μs High-level period of SCL clock (input) tHIGH 3 / fcgck - 3 / fcgck - μs Restart condition setup time tSU;STA Depends on the software - Depends on the software - μs Data hold time tHD;DAT 0 5 / fcgck 0 5 / fcgck μs Data setup time tSU;DAT 250 - 100 - ns Rising time of SDA and SCL signals tr - 1000 - 300 ns Falling time of SDA and SCL signals tf - 300 - 300 ns tSU;STO m / fcgck - m / fcgck - μs Bus free time between the stop condition and the start condition tBUF Depends on the software - Depends on the software - μs Time before rising of SCL after SBICR2 is changed from "0" to "1" tSU;SCL n / fcgck - n / fcgck - μs SCL clock frequency Stop condition setup time Note:For m and n, refer to"18.4.4.1 Clock source". tf t SU;DAT t LOW tr t HD;STA tf t HD;STA t HD;DAT t SU;STA t HIGH Figure 18-23 Definition of Timing (No. 1) Page 297 RA002 tf t BUF t SU;STO 18. 18.6 Serial Bus Interface (SBI) AC Specifications TMP89FM42 SCL SBICR2 t SU;SCL Figure 18-24 Definition of Timing (No. 2) Page 298 RA002 TMP89FM42 18.7 Revision History Rev Description " Serial bus interface control register 1" Revised SCK description. Added Note5. RA001 "18.6 AC Specifications" Revised fcgck description. "Table 18-8 AC Specifications (Circuit Output Timing)" Revised value of "SCL clock frequency". Revised from "normal mode" to "standard mode". RA002 "18.5.1 Device initialization" Revised example of program. Page 299 RA002 18. 18.7 Serial Bus Interface (SBI) Revision History TMP89FM42 Page 300 RA002 TMP89FM42 19. Key-on Wakeup (KWU) The key-on wakeup is a function for releasing the STOP mode at the STOP pin or at pins KWI7 through KWI0. 19.1 Configuration SYSCR1 S Stop mode Y 0 release signal 1 (to be released Selector if set to “1”) Rising edge detection Port STOP Port KWI0 Port KWI1 Port KWI2 Port KWI3 Port KWI4 Port KWI5 Port KWI6 Port KWI7 KWUCR0 (0x0FC4) 7 6 5 4 3 2 1 0 KWUCR1 (0x0FC5) 7 6 5 4 3 2 1 0 Figure 19-1 Key-on Wakeup Circuit Page 301 RA000 19. 19.2 Key-on Wakeup (KWU) Control TMP89FM42 19.2 Control Key-on wakeup control registers (KWUCR0 and KWUCR1) can be configured to designate the key-on wakeup pins (KWI7 through KWI0) as STOP mode release pins and to specify the STOP mode release levels of each of these designated pins. Key-on wakeup control register 0 7 6 5 4 3 2 1 0 Bit Symbol KW3LE KW3EN KW2LE KW2EN KW1LE KW1EN KW0LE KW0EN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 KWUCR0 (0x0FC4) KW3LE STOP mode release level of KWI3 pin 0: Low level 1: High level KW3EN Input enable/disable control of KWI3 pin 0: Disable 1: Enable KW2LE STOP mode release level of KWI2 pin 0: Low level 1: High level KW2EN Input enable/disable control of KWI2 pin 0: Disable 1: Enable 0: Low level 1: High level Input enable/disable control of KWI1 pin 0: Disable 1: Enable KW0LE STOP mode release level of KWI0 pin 0: Low level 1: High level KW0EN Input enable/disable control of KWI0 pin 0: Disable 1: Enable KW1LE KW1EN STOP mode release level of KWI1 Key-on wakeup control register 1 7 6 5 4 3 2 1 0 Bit Symbol KW7LE KW7EN KW6LE KW6EN KW5LE KW5EN KW4LE KW4EN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 KWUCR1 (0x0FC5) STOP mode release level of KWI7 pin 0: Low level 1: High level Input enable/disable control of KWI7 pin 0: Disable 1: Enable KW6LE STOP mode release level of KWI6 pin 0: Low level 1: High level KW6EN Input enable/disable control of KWI6 pin 0: Disable 1: Enable KW5LE STOP mode release level of KWI5 pin 0: Low level 1: High level KW5EN Input enable/disable control of KWI5 pin 0: Disable 1: Enable KW4LE STOP mode release level of KWI4 pin 0: Low level 1: High level Input enable/disable control of KWI4 pin 0: Disable 1: Enable KW7LE KW7EN KW4EN Page 302 RA000 TMP89FM42 19.3 Functions By using the key-on wakeup function, the STOP mode can be released at a STOP pin or at KWIm pin (m: 0 through 7). After resetting, the STOP pin is the only STOP mode release pin. To designate the KWIm pin as a STOP mode release pin, therefore, it is necessary to configure the key-on wakeup control register (KWUCRn) (n: 0 or 1). Because the STOP pin lacks a function for disabling inputs, it can be designated as a pin for receiving a STOP mode release signal, irrespective of whether the key-on wakeup function is used or not. ・ Setting KWUCRn and P4PU registers To designate a key-on wakeup pin (KWIm) as a STOP mode release pin, set KWUCRn to "1". After KWIm pin is set to "1" at KWUCRn, a specific STOP mode release level can be specified for this pin at KWUCRn. If KWUCRn is set to "0", STOP mode is released when an input is at a low level. If it is set to "1", STOP mode is released when an input is at a high level. For example, if you want to release STOP mode by inputting a high-level signal into a KWI0 pin, set KWUCR0 to "1", " and KWUCR0 to "1". Each KWIm pin can be connected to internal pull-up resistors. Before connecting to internal pull-up resistors, the corresponding bits in the pull-up control register (P4PU) at port P4 must be set to "1". ・ Starting STOP mode To start the STOP mode, set SYSCR1 to "1" (level release mode), and SYSCR1 to "1". To use the key-on wakeup function, do not set SYSCR1 to "0" (edge release mode). If the keyon wakeup function is used in edge release mode, STOP mode cannot be released, although a rising edge is input into the STOP pin. This is because the KWIm pin enabling inputs to be received is at a release level after the STOP mode starts. ・ Releasing STOP mode To release STOP mode, input a high-level signal into the STOP pin or input a specific release level into the KWIm pin for which receipt of inputs is enabled. If you want to release STOP mode at the KWIm pin, rather than the STOP pin, continue inputting a low-level signal into the STOP pin throughout the period from when the STOP mode is started to when it is released. If the STOP pin or KWIm pin is already at a release level when the STOP mode starts, the following instruction will be executed without starting the STOP mode (with no warm-up performed). Note 1: If an analog voltage is applied to KWIm pin for which receipt of inputs is enabled by the key-on wakeup control register (KWUCRn) setting, a penetration current will flow. Therefore, in this case, the analog voltage should be not applied to this pin. Table 19-1 STOP Mode Release Level (edge) Release level (edge) Pin name SYSCR1="1" (level release mode) KWUCRn="0" STOP KWIm KWUCRn="1" "H" level "L" level (edge release mode) Rising edge "H" level Page 303 RA000 SYSCR1="0" Don't use 19. 19.3 Key-on Wakeup (KWU) Functions TMP89FM42 Example :A case in which STOP mode is started with the release level of the STOP pin set to a high level and the release level of KWI0 set to a low level (connected to an internal pull-up resistor of the KWI0 pin) DI ; IMF←0 SET (P4PU).0 ; KWI0 (P40) connected to a pull-up resistor LD (KWUCR0), 0y00000001 ; the KWI0 pin is set to enable inputs, and its release level is set LD (SYSCR1), 0y10100000 ; to a low level. ; Starting in level release mode Page 304 RA000 TMP89FM42 20. 10-bit AD Converter (ADC) The TMP89FM42 has a 10-bit successive approximation type AD converter. 20.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 20-1. It consists of control registers ADCCR1 and ADCCR2, converted value registers ADCDRL and ADCDRH, a DA converter, a sample-hold circuit, a comparator, a successive comparison circuit, etc. DA converter VAREF/AVDD VSS R/2 Input selector AIN0 A R R/2 Sample-hold circuit Reference voltage Y 10 Analog comparator n S EN Shift clock 10 INTADC Control circuit 3 2 AMD ACK ADCCR1 ADCCR2 Selector RSEL AINDS ADRS 4 SAIN Successive approximation circuit EOCF ADBF AIN7 AD converter control registers 1 and 2 8 ADCDRL 8 ADCDRH AD converted value registers 1 and 2 Figure 20-1 10-bit AD Converter Note 1: Before using the AD converter, set an appropriate value to the I/O port register which is also used as an analog input port. For details, see the section on "I/O ports". Note 2: The DA converter current (IREF) is automatically cut off at times other than during AD conversion. Page 305 RA002 20. 20.2 10-bit AD Converter (ADC) Control 20.2 TMP89FM42 Control The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCR1) This register selects an analog channel in which to perform AD conversion, selects an AD conversion operation mode, and controls the start of the AD converter. 2. AD converter control register 2 (ADCCR2) This register selects the AD conversion time, and monitors the operating status of the AD converter. 3. AD converted value registers (ADCDRH and ADCDRL) These registers store the digital values generated by the AD converter. Page 306 RA002 TMP89FM42 AD converter control register 1 7 ADCCR1 (0x0034) 6 5 4 3 2 Bit Symbol ADRS AMD AINEN SAIN Read/Write R/W R/W R/W R/W After reset 0 ADRS AMD AINEN SAIN 0 AD conversion start AD operating mode Analog input control Analog input channel select 0 0 0: - 1: AD conversion start 0 0 00: AD operation disable, forcibly stop AD operation 01: Single mode 10: Reserved 11: Repeat mode 0: Analog input disable 1: Analog input enable 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 1000: Reserved 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: Reserved 1 0 0 0 Note 1: Do not perform the following operations on the ADCCR1 register while AD conversion is being executed (ADCCR2="1"). - Changing SAIN - Setting AINEN to "0" - Changing AMD (except a forced stop by setting AMD to "00") - Setting ADRS to "1" Note 2: If you want to disable all analog input channels, set AINEN to "0". Note 3: Although analog input pins are also used as input/output ports, it is recommended for the purpose of maintaining the accuracy of AD conversion that you do not execute input/output instructions during AD conversion. Additionally, do not input widely varying signals into the ports adjacent to analog input pins. Note 4: When STOP, IDLE0 or SLOW mode is started, ADRS, AMD and AINEN are initialized to "0". If you use the AD converter after returning to NORMAL mode, you must reconfigure ADRS, AMD and AINEN. Note 5: After the start of AD conversion, ADRS is automatically cleared to "0" ("0" is read). Page 307 RA002 20. 20.2 10-bit AD Converter (ADC) Control TMP89FM42 AD converter control register 2 7 6 5 4 3 Bit Symbol EOCF ADBF - - "0" Read/Write R R R R W After reset 0 0 0 0 0 ADCCR2 (0x0035) EOCF ADBF ACK AD conversion end flag AD conversion BUSY flag AD conversion time select (examples of AD conversion time are shown in the table below) 2 1 ACK R/W 0 0 0: Before conversion or during conversion 1: Conversion end 0: AD conversion being halted 1: AD conversion being executed 000: 39/fcgck 001: 78/fcgck 010: 156/fcgck 011: 312/fcgck 100: 624/fcgck 101: 1248/fcgck 110: Reserved 111: Reserved 0 0 Note 1: Make sure that you make the ACK setting when AD conversion is in a halt condition (ADCCR2="0"). Note 2: Make sure that you write "0" to bit 3 of ADCCR2. Note 3: If STOP, IDLE0 or SLOW mode is started, EOCF and ADBF are initialized to "0". Note 4: If the AD converted value register (ADCDRH) is read, EOCF is cleared to "0". It is also cleared to "0" if AD conversion is started (ADCCR1="1") without reading ADCDRH after completing AD conversion in single mode. Note 5: If an instruction to read ADCCR2 is executed, 0 is read from bits 3 through 5. Table 20-1 ACK Settings and Conversion Times Relative to Frequencies Frequency (fcgck) ACK setting Conversion time 10MHz 8MHz 5MHz 4MHz 2.5MHz 2MHz 1MHz 0.5MHz 0.25 MHz 000 39/fcgck - - - - 15.6 μs 19.5 μs 39.0 μs 78.0 μs 156.0 μs 001 78/fcgck - - 15.6 μs 19.5 μs 31.2 μs 39.0 μs 78.0 μs 156.0 μs - 010 156/fcgck 15.6 μs 19.5 μs 31.2 μs 39.0 μs 62.4 μs 78.0 μs 156.0 μs - - 011 312/fcgck 31.2 μs 39.0 μs 62.4 μs 78.0 μs 124.8 μs 156.0 μs - - - 100 624/fcgck 62.4 μs 78.0 μs 124.8 μs 156.0 μs - - - - - 101 1248/fcgck 124.8 μs 156.0 μs - - - - - - - 11* Reserved Note 1: Spaces indicated by "-" in the above table mean that it is prohibited to establish conversion times in these spaces. fcgck: High Frequency oscillation clock [Hz] Note 2: Above conversion times do not include the time shown below. - Time from when ADCCR1 is set to 1 to when AD conversion is started - Time from when AD conversion is finished to when a converted value is stored in ADCDRL and ADCDRH. If ACK = 00*, the longest conversion time is 10/fcgck (s). If ACK = 01*, it is 32/fcgck (s). If ACK = 10*, it is 128/fcgck(s). Note 3: The conversion time must be longer than the following time by analog reference voltage (VAREF). - VAREF = 4.5 to 5.5 V 15.6 μs or longer - VAREF = 2.7 to 5.5 V 31.2 μs or longer - VAREF = 2.2 to 5.5 V 124.8 μs or longer Page 308 RA002 TMP89FM42 AD converted value register (lower side) ADCDRL (0x0036) 7 6 5 4 3 2 1 0 Bit Symbol AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 Read/Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 5 4 3 2 1 0 AD converted value register (upper side) 7 ADCDRH (0x0037) 6 Bit Symbol - - - - - - AD09 AD08 Read/Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 Note 1: A read of ADCDRL or ADCDRH must be read after the INTADC interrupt is generated or after ADCCR2 becomes "1". Note 2: In single mode, do not read ADCDRL or ADCDRH during AD conversion (ADCCR2="1"). (If AD conversion is finished in the interim between a read of ADCDRL and a read of ADCDRH, the INTADC interrupt request is canceled, and the conversion result is lost.) Note 3: If STOP, IDLE0 or SLOW mode is started, ADCDRL and ADCDRH are initialized to "0". Note 4: If ADCCR1 is set to "00", ADCDRL and ADCDRH are initialized to "0". Note 5: If an instruction to read ADCDRH is executed, "0" is read from bits 7 through 2. Note 6: If AD conversion is finished in repeat mode in the interim between a read of ADCDRL and a read of ADCDRH, the previous converted value is retained without overwriting the AD converted value register. In this case, the INTADC interrupt request is canceled, and the conversion result is lost. Page 309 RA002 20. 20.3 10-bit AD Converter (ADC) Functions TMP89FM42 20.3 Functions The 10-bit AD converter operates in either single mode in which AD conversion is performed only once or repeat mode in which AD conversion is performed repeatedly. 20.3.1 Single mode In single mode, the voltage at a designated analog input pin is AD converted only once. Setting ADCCR1 to "1" after setting ADCCR1 to "01" allows AD conversion to start. ADCCR1 is automatically cleared after the start of AD conversion. As AD conversion starts, ADCCR2 is set to "1". It is cleared to "0" if AD conversion is finished or if AD conversion is forced to stop. After AD conversion is finished, the conversion result is stored in the AD converted value registers (ADCDRL and ADCDRH), ADCCR2 is set to "1", and the AD conversion finished interrupt (INTADC) is generated. The AD converted value registers (ADCDRL and ADCDRH) should be usually read according to the INTADC interrupt processing routine. If the upper side (ADCDRH) of the AD converted value register is read, ADCCR2 is cleared to "0". Note:Do not perform the following operations on the ADCCR1 register when AD conversion is being executed (ADCCR2="1"). If the following operations are performed, there is the possibility that AD conversion may not be executed properly. ・ Changing the ADCCR1 setting ・ Setting ADCCR1 to "0" ・ Changing the ADCCR1 setting (except a forced stop by setting AMD to "00") ・ Setting ADCCR1 to "1" AD conversion start AD conversion start ADCCR1 ADCCR2 Status of ADCDRL and ADCDRH Indeterminate Result of the first conversion Result of the second conversion Clearing EOCF based on the conversion result ADCCR2 INTADC interrupt request Read of ADCDRH Read of conversion result Read of conversion result Read of ADCDRL Read of conversion result Read of conversion result Figure 20-2 Single Mode 20.3.2 Repeat mode In repeat mode, the voltage at an analog input pin designated at ADCCR1 is AD converted repeatedly. Setting ADCCR1 to "1" after setting ADCCR1 to "11" allows AD conversion to start. After the start of AD conversion, ADCCR1 is automatically cleared. After the first AD conversion is finished, the conversion result is stored in the AD converted value registers (ADCDRL and ADCDRH), ADCCR2 is set to "1", and the AD conversion finished interrupt (INTADC) is generated. After this interrupt is generated, the second (next) AD conversion starts immediately. Page 310 RA002 TMP89FM42 The AD converted value registers (ADCDRL and ADDRH) should be read before the next AD conversion is finished. If the next AD conversion is finished in the interim between a read of ADCDRL and a read of ADCDRH, the previous converted value is retained without overwriting the AD converted value registers (ADCDRL and ADCDRH). In this case, the INTADC interrupt request is not generated, and the conversion result is lost. (See Figure 20-3.) To stop AD conversion, write "00" (AD operation disable) to ADCCR1. As "00" is written to ADCCR1, AD conversion stops immediately. In this case, the converted value is not stored in the AD converted value register. As AD conversion starts, ADCCR2 is set to "1". It is cleared to "0" if "00" is written to AMD. ADCCR1 “11” “00” AD conversion start ADCCR1 Result of the 2nd conversion Conversion operation Status of ADCDRL and ADCDRH Indeterminate Result of the 3rd conversion Result of the 1st conversion Result of the 4th conversion Result of the 3rd conversion AD conversion is suspended. The conversion result is not stored. Result of the 4th conversion ADCCR2 A read of the conversion result will clear EOCF. INTADC interrupt Read of ADCDRH Read of conversion result Read of ADCDRL The INTADC interrupt request is not generated in the interim between a read of ADCDRL and a read of ADCDRH. Read of conversion result Read of conversion result Read of conversion result Read of conversion result Read of conversion result Figure 20-3 Repeat Mode 20.3.3 AD operation disable and forced stop of AD operation If you want to force the AD converter to stop when AD conversion is ongoing in single mode or if you want to stop the AD converter when AD conversion is ongoing in repeat mode, set ADCCR1 to "00". If ADCCR1 is set to "00", registers ADCCR2, ADCCR2, ADCDRL, and ADCDRH are initialized to "0". Page 311 RA002 20. 20.4 10-bit AD Converter (ADC) Register Setting 20.4 TMP89FM42 Register Setting 1. Set the AD converter control register 1 (ADCCR1) as described below: ・ From the AD input channel select (SAIN), select the channel in which AD conversion is to be performed. ・ Set the analog input control (AINEN) to "Analog input enable". ・ At AMD, specify the AD operating mode (single or repeat mode). 2. Set the AD converter control register 2 (ADCCR2) as described below: ・ At the AD conversion time (ACK), specify the AD conversion time. For information on how to specify the conversion time, refer to the AD converter control register 2 and Table 20-1. 3. After the above two steps are completed, set "1" on the AD conversion start (ADRS) of the AD converter control register 1 (ADCCR1), and AD conversion starts immediately if single mode is selected. 4. As AD conversion is finished, the AD conversion end flag (EOCF) of the AD converter control register 2 (ADCCR2) is set to "1", the AD conversion result is stored in the AD converted value registers (ADCDRH and ADCDRL), and the INTADC interrupt request is generated. 5. After the conversion result is read from the AD converted value register (ADCDRH), EOCF is cleared to "0". EOCF will also be cleared to "0" if AD conversion is performed once again before reading the AD converted value register (ADCDRH). In this case, the previous conversion result is retained until AD conversion is finished. Example: After selecting the conversion time 15.6 μs at 10 MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, store the conversion result in the HL register. The operation mode is single mode. : (Port setting) ;Before setting AD converter registers, make an appropriate port ;register setting.(For further details, refer to the section that describes ;I/O ports.) SLOOP : 20.5 LD (ADCCR1), 0y00110011 ;Select AIN3 and operation mode LD (ADCCR2), 0y00000010 ;Select conversion time (156/fcgck) SET (ADCCR1). 7 ;ADRS = 1 (AD conversion start) TEST (ADCCR2). 7 ;EOCF = 1 ? J T, SLOOP LD HL, (ADCDRL) ;Read result data Starting STOP/IDLE0/SLOW Modes If STOP/IDLE0/SLOW mode is started, registers ADCCR1, ADCCR2, ADCDRL and ADCDRH are initialized to "0". If any of these modes is started during AD conversion, AD conversion is suspended, and the AD converter stops (registers are likewise initialized). When restored from STOP/ IDLE0/ SLOW mode, AD conversion is not automatically restarted. Therefore, registers must be reconfigured as necessary. If STOP/IDLE0/SLOW mode is started during AD conversion, analog reference voltage is automatically disconnected and, therefore, there is no possibility of current flowing into the analog reference voltage. Page 312 RA002 TMP89FM42 20.6 Analog Input Voltage and AD Conversion Result Analog input voltages correspond to AD-converted, 10-bit digital values, as shown in Figure 20-4. AD-converted value 3FFH 3FEH 3FDH 03H 02H 01H VAREF/AVDD − VSS 0 1 2 3 1021 1022 1023 1024 1024 Analog input voltage Figure 20-4 Relationships between Analog Input Voltages and AD-converted Values (typical values) Page 313 RA002 20. 20.7 10-bit AD Converter (ADC) Precautions about the AD Converter 20.7 TMP89FM42 Precautions about the AD Converter 20.7.1 Analog input pin voltage range Analog input pins (AIN0 through AIN7) should be used at voltages from VAREF to VSS. If any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain, and converted values on other pins will also be affected. 20.7.2 Analog input pins used as input/output ports Analog input pins (AIN0 to AIN7) are also used as input/output ports. In using one of analog input pins (ports) to execute AD conversion, input/output instructions at all other pins (ports) must not be executed. If they are executed, there is the possibility that the accuracy of AD conversion may deteriorate. This also applies to pins other than analog input pins; if one pin receives inputs or generates outputs, noise may occur and its adjacent pins may be affected by that noise. 20.7.3 Noise countermeasure The internal equivalent circuit of the analog input pins is shown in Figure 20-5. The higher the output impedance of the analog input source, the more susceptible it becomes to noise. Therefore, make sure the output impedance of the signal source in your design is 5 kΩ or less. It is recommended that a capacitor be attached externally. rnal resistance: Analog comparator 5 kΩ (max) AINi Permissible signal rnal capacitance: source impedance: Internal resistance: Analog comparator kΩ (typ) 5#!Undefined!# kΩ (typ) Internal capacitance: C = 22 pF (typ.) DA converter DA converter Note) i = 7 to 0 Figure 20-5 Analog Input Equivalent Circuit and Example of Input Pin Processing Page 314 RA002 TMP89FM42 20.8 Revision History Rev RA002 Description "20.4 Register Setting" Revised ADCCR2 value and comment of example program. Page 315 RA002 20. 20.8 10-bit AD Converter (ADC) Revision History TMP89FM42 Page 316 RA002 TMP89FM42 21. Flash Memory The TMP89FM42 has flash memory of 32768 bytes. A write and erase to be performed on flash memory can be controlled in the following three modes: - MCU mode In MCU mode, the flash memory is accessed by the CPU control, and the flash memory can be executed the erasing and writing without affecting the operations of a running application. Therefore, this mode is used for software debugging and firmware change after shipment of the TMP89FM42. - Serial PROM mode In serial PROM mode, the flash memory is accessed by the CPU control. Use of the serial interface (UART and SIO) enables the flash memory to be controlled by the small number of pins. The TMP89FM42 used in serial PROM mode supports on-board programming, which enables users to program flash memory after the microcontroller is mounted on a user board. - Parallel PROM mode The parallel PROM mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by a third party. High-speed access to the flash memory is available by controlling address and data signals directly. To receive a support service for the program writer, please ask a Toshiba sales representative. In MCU and serial PROM modes, flash memory control registers (FLSCR1 and FLSCR2) are used to control the flash memory. This chapter describes how to access the flash memory using the MCU and serial PROM modes. Page 317 RA006 21. 21.1 Flash Memory Flash Memory Control 21.1 TMP89FM42 Flash Memory Control The flash memory is controlled by the flash memory control register 1 (FLSCR1), flash memory control register 2 (FLSCR2), and flash memory standby control register (FLSSTB). Flash memory control register 1 7 FLSCR1 (0x0FD0) Bit Symbol 6 FLSMD 4 FLSMD Read/Write After reset 5 BAREA R/W 0 1 3 FAREA R/W 0 sequence and toggle control R/W 0 Flash memory command 2 0 0 - - R/W R/W 0 0 Disable command sequence and toggle execution 101: Enable command sequence and toggle execution Others: BOOTROM mapping control 0 010: Reserved MCU mode BAREA 1 Serial PROM mode 0: Hide BOOTROM - 1: Show BOOTROM Show BOOTROM 00: Assign the data area 0x8000 through 0xFFFF to the data area 0x8000 through 0xFFFF (standard mapping). FAREA Flash memory area select control 01: Reserved 10: Assign the code area 0x8000 through 0xFFFF to the data area 0x8000 through 0xFFFF. 11: Reserved Note 1: It is prohibited to make a setting in "Reserved". Note 2: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register. Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift register can be checked by reading the register FLSCRM. Note 3: FLSMD must be set to either "0y010" or "0y101". Flash memory control register 2 7 FLSCR2 (0x0FD1) 6 5 4 Bit Symbol Read/Write After reset CR1EN 3 2 1 0 * * * * CR1EN W * FLSCR1 register enable/disable control * * * 0xD5 Others Enable a change in the FLSCR1 setting Reserved Note 1: If "0xD5" is set on FLSCR2 with FLSCR1 set to "101", the flash memory goes into an active state, and MCU consumes the same amount of current as it does during a read. Page 318 RA006 TMP89FM42 Flash memory control register 1 monitor 7 FLSCRM (0x0FD1) 6 Bit Symbol 5 4 FLSMDM BAREAM Read/Write R R R R After reset 0 0 0 0 0 3 2 FAREAM R 0 R 0 0 FLSCR1="101" setting disabled Monitoring of FLSCR1 status BAREAM Monitoring of FLSCR1 status Value of currently enabled FLSCR1 FAREAM Monitoring of FLSCR1 status Value of currently enabled FLSCR1 Monitoring of FLSCR1 status Value of currently enabled FLSCR1 ROMSELM 0 ROMSELM FLSMDM 1 1 FLSCR1="101" setting enabled Note 1: FLSCRM is the register that checks the value of the shift register of the flash memory control register 1. Note 2: FLSMDM turns into "1" only if FLSMD="101" becomes effective. Note 3: If an instruction to read FLSCRM is executed, "0" is read from bits 7 and 6. Note 4: In serial PROM mode, "1" is always read from BAREAM. Page 319 RA006 0 21. 21.1 Flash Memory Flash Memory Control TMP89FM42 Flash memory standby control register (0x0FD2) 0 7 6 5 4 3 2 1 Read/Write R R R R R R R W After reset 0 0 0 0 0 0 0 0 FLSSTB Bit Symbol FSTB FSTB Flash memory standby control 0 Disable flash memory standby 1 Enable flash memory standby Note 1: A value can be written to FSTB only by using a program that resides in RAM. A value written using a program residing in the flash memory will be invalidated. Note 2: If FSTB is set to "1", do not execute instructions to fetch or read data from or write data to the flash memory. If they are executed, a flash standby reset will occur. Note 3: If an instruction to read FLSSTB is executed, "0" is read from bits 7 through 0. Port input control register (this register works only in serial PROM mode) 7 6 5 4 3 2 Read/Write R R R R R R After reset 1 0 0 0 0 0 SPCR (0x0FD3) Bit Symbol In serial PROM mode PIN1 PIN0 Port input control (SCLK0 pin) in serial PROM mode Port input control (except RXD0, TXD0 and SCLK0) in serial PROM mode 1 0 PIN1 PIN0 R/W R/W 0 0 In MCU mode 0 Port input disabled Input enabled for all ports 1 Port input enabled 0 Port input disabled Nonfunctional whatever settings are made 1 Port input enabled "0" is read Note 1: A read or write can be performed on the SPCR register only in serial PROM mode. If a write is performed on this register in MCU mode, the port input control does not function. If a read is performed on the SPCR register in MCU mode, "0" is read from bits 7 through 0. Note 2: All I/O ports are controlled by PIN0, except the ports RXD0, TXD0 and SCLK0 which are used in serial PROM mode. By using PIN1, the SCLK0 pin can be configured separately from other pins. Page 320 RA006 TMP89FM42 21.2 Functions 21.2.1 Flash memory command sequence execution and toggle control (FLSCR1 ) To prevent inadvertent writes to the flash memory due to program error or microcontroller malfunction, the execution of the flash memory command sequence and the toggle operation can be disabled (the flash memory can be write protected) by making an appropriate control register setting (write protect). To enable the execution of the command sequence and the toggle operation, set FLSCR1 to "0y101", and then set "0xD5" on FLSCR2. To disable the execution of the command sequence, set FLSCR1 to "0y010", and then set "0xD5" on FLSCR2. If the command sequence or the toggle operation is executed with the execution of the command sequence and the toggle operation set to "disable", the executed command sequence or toggle operation takes no effect. After a reset, FLSCR1 is initialized to "0y010" to disable the execution of the command sequence. FLSCR1 should normally be set to "0y010" except when a write or erase is to be performed on the flash memory. Note 1: If "0xD5" is set on FLSCR2 with FLSCR1 set to "101", the flash memory goes into an active state, and MCU consumes the same amount of current as it does during a read. Note 2: If FLSCR1 is set to "disable", subsequent commands (write instructions) generated are rejected but a command sequence being executed is not initialized. If you want to set FLSCR1 to "disable", you must finish all command sequences and verify that the flash memory is ready to be read. Page 321 RA006 21. 21.2 Flash Memory Functions 21.2.2 TMP89FM42 Flash memory area switching (FLSCR1) To perform an erase or write on the flash memory, a memory transfer instruction (command sequence) must be executed. If a memory transfer instruction is used to read or write data, a read or write can be performed only on the data area. To perform an erase or write on the code area, therefore, part of the code area must be temporarily switched to the data area. This switching between data and code areas is performed by making the appropriate FLSCR1 setting. By setting "0xD5" on FLSCR2 after setting FLSCR1 to "10", 0x8000 through 0xFFFF (AREA C1) in the code area is mapped to 0x8000 through 0xFFFF (AREA D1) in the data area. To restore the flash memory to the initial state of mapping, set FLSCR1 to "00", and then set "0xD5" on FLSCR2. All flash memory areas can be accessed by performing the appropriate steps described above and then executing the memory transfer instruction on 0x8000 through 0xFFFF (AREA D1) in the data area. 0x8000 through 0xFFFF (AREA D1) in the data area and 0x8000 through 0xFFFF (AREA C1) in the code area are mirror areas; these two areas refer to the same physical address in memory. Therefore, an erase or write must be performed on one of these two mirror areas. For example, If a write is performed on 0x8000 in the data area with FLSCR1 set to "10" after performing a write on 0x8000 in the data area with FLSCR1 set to "00", data is overwritten. To write data to the flash memory that already has data written to it, existing data must first be erased from the flash memory by performing a sector erase or chip erase, and then data must be written. Additionally, access to areas to which memory is not assigned should be avoided by executing an instruction or specifying such an area by using jump or call instructions. Page 322 RA006 TMP89FM42 0x0000 SFR RAM 0x0000 0x0FFF 0x7FFF 0x8000 0x7FFF 0x8000 32768 bytes Flash AREA D1 32768 bytes Flash 0xFFFF AREA C1 0xFFFF Data area Code area If FLSCR = “00” 0x0000 0x0000 SFR RAM 0x0FFF 0x7FFF 0x8000 0x7FFF 0x8000 32768 bytes Flash AREA C1 32768 bytes Flash 0xFFFF AREA C1 0xFFFF Data area Code area If FLSCR = “10” Figure 21-1 Area Switching Using the FLSCR1 Setting Page 323 RA006 21. 21.2 Flash Memory Functions 21.2.3 TMP89FM42 RAM area switching (SYSCR3) If "0xD4" is set on SYSCR4 after SYSCR3 is set to "1" in MCU mode, RAM is mapped to the code area. To restore the RAM area to the initial state of mapping, set SYSCR3 to "0", and then set "0xD4" on SYSCR4. In serial PROM mode, RAM is mapped to the code area, irrespective of the SYSCR3 setting. 21.2.4 BOOTROM area switching (FLSCR1) If "0xD5" is set on FLSCR2 after FLSCR1 is set to "1" in MCU mode, 0x1000 through 0x17FF in the code and data areas is masked by flash memory, and 2K-byte (first half of 4KB) BOOTROM is mapped. If you do not want to map BOOTROM, set "0xD5" on FLSCR2 after setting FLSCR1 to "0". A set of codes for programming flash memory in serial PROM mode are built into BOOTROM, and a support program (API) for performing an erase or write on flash memory in a simple manner is also built into one part in the BOOTROM area. Therefore, by calling a subroutine in the support program after BOOTROM is mapped, it is possible to erase, write and read flash memory easily. In serial PROM mode, BOOTROM is mapped to 0x1000 through 0x17FF in the data area and 0x1000 through 0x1FFF in the code area, irrespective of the FLSCR1 setting. BAREA is always "1", and the set BAREA value remains unchanged, even if data is written. "1" is always read from BAREA. Page 324 RA006 TMP89FM42 0x0000 0x003F 0x0040 0x0000 0x0000 SFR 0x003F 0x0040 RAM 0xXXXX 0xXXXX 0x1000 0x1000 0xFFFF 0xFFFF RAM 0x0000 0xFFFF Data area Code area If SYSSR4=“1” FLSCR1=“0” 0x0000 0x0000 SFR 0x003F 0x0040 RAM 0xXXXX 0x0000 SFR 0x003F 0x0040 RAM 0xXXXX 0x1000 0x1000 BOOTROM 0x17FF 0x1800 0xFFFF 0x1000 BOOTROM 0x17FF 0x1800 0xFFFF BOOTROM 0x17FF 0x1800 0xFFFF Code area Data area RAM 0xXXXX 0x1000 BOOTROM 0x17FF 0x1800 RAM 0xXXXX 0xXXXX+1 If SYSSR4=“0” FLSCR1=“0” 0x003F 0x0040 0x003F 0x0040 0xFFFF Code area Data area 0x0000 SFR 0xFFFF Data area If SYSSR4=“0” FLSCR1=“1” Code area If SYSSR4=“1” FLSCR1=“1” 0x0000 0x0000 0x003F 0x0040 SFR RAM 0x003F 0x0040 RAM 0xXXXX 0xXXXX 0x1000 0x1000 BOOTROM BOOTROM 0x17FF 0x1800 0x17FF 0x1800 0xFFFF 0xFFFF Data area Note : XXXXH is end of RAM address. Code area In serial PROM mode Figure 21-2 Show/Hide Switching for BOOTROM and RAM Page 325 RA006 21. 21.2 Flash Memory Functions 21.2.5 TMP89FM42 Flash memory standby control (FLSSTB) FLSSTB is the register provided to maintain the compatibility with the previous product version. It must normally be set to "0". In using FLSSTB built into the TMP89FM42, the following point should be noted: FLSSTB can be configured only by using a program allocated to RAM. If it is configured by using a program allocated to the flash memory, the configured value will be invalidated and does not take effect. To access the flash memory again after setting FLSSTB to "1", set FLSSTB to "0" by using a program allocated to RAM. If the flash memory is accessed with FLSSTB set to "1," a flash standby reset will occur. If an interrupt occurs when the interrupt vector is assigned to the flash memory area (SYSCR3 = "0" is effective), FSTB is automatically initialized to "0", and then the interrupt vector of the flash memory area is read. If an interrupt occurs when the interrupt vector is assigned to the RAM area (SYSCR3 = "1" is effective), FSTB is not cleared to "0", and then the interrupt vector of the RAM area is read. In this case, the RAM area should be designated as a referential address of interrupt vector. If the flash memory area is designated as a referential address of interrupt vector, a flash standby reset occurs after an interrupt is generated. Page 326 RA006 TMP89FM42 21.2.6 Port input control register (SPCR) In serial PROM mode, the input levels of all ports, except the ports RXD0 and TXD0 used in serial PROM mode, are physically fixed after a reset is released. This is designed to prevent a penetration current from flowing through unused ports (port inputs and functional peripheral inputs, which are also used as ports, are disabled). To access the flash memory using the RAM loader mode and a method other than the UART, therefore, port inputs must be set to "enable". To enable the SCLK0 port input, set SPCR to "1". To enable port inputs other than RXD0, TXD0 and SCLK0 port inputs, set SPCR to "1". In MCU mode, the SPCR register does not function. Page 327 RA006 21. 21.3 Flash Memory Command Sequence 21.3 TMP89FM42 Command Sequence In MCU and serial PROM modes, the command sequence consists of six commands (JEDEC compatible), as shown in Table 21-1. Table 21-1 Command Sequence 1st Bus Write Cycle Command sequence 1 Byte Program 2 (partial erase in units of 4KB) 2nd Bus Write Cycle 3rd Bus Write Cycle Add Data Add Data Add Data 0x#555 0xAA 0x#AAA 0x55 0x#555 0xA0 0x#555 0xAA 0x#AAA 0x55 0x#555 0x#555 0xAA 0x#AAA 0x55 0x#555 0xAA 0x#AAA 0x55 4th Bus Write Cycle Add 5th Bus Write Cycle Data 6th Bus Write Cycle Add Data Add Data - - - - BA Data (Note 1) (Note 1) 0x80 0x#555 0xAA 0x#AAA 0x55 0x#555 0x80 0x#555 0xAA 0x#AAA 0x55 0x#555 0x10 0x#555 0x90 - - - - - - Sector Erase Chip Erase 3 (all erase) 4 Product ID Entry SA (Note 2) 0x30 5 Product ID Exit 0xXX 0xF0 - - - - - - - - - - 6 Security Program 0x#555 0xAA 0x#AAA 0x55 0x#555 0xA5 0xFF7F 0x00 - - - - Note 1: Specify the address and data to be written (Refer to Table 21-2 about BA). Note 2: The area to be erased is specified with the upper 4 bits of the address (Refer to Table 21-3 about SA). Note 3: Do not start the STOP, IDLE0, IDLE1, IDLE2, SLEEP1 or SLEEP0 mode while a command sequence is being executed or a task specified in a command sequence is being executed (write, erase or ID entry). Note 4: # ; 0x8 through 0xF should be specified as the upper 4bits of the address. Usually, it is recommended that 0xF is specified. Note 5: XXX ; Don’t care 21.3.1 Byte program This command writes the flash memory in units of one byte. The address and data to be written are specified in the 4th bus write cycle. The range of addresses that can be specified is shown in Table 21-2. For example, to write data to 0x8000 in the data area, set FLSCR1 to "0y00", set "0xD5" on FLSCR2, and then specify 0x8000 as an address in the 4th bus write cycle. The time needed to write each byte is 40 μs maximum. The next command sequence cannot be executed if an ongoing write operation is not completed. To check the completion of the write operation, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read from the flash memory. During the write operation, bit 6 is reversed each time a read is performed. Note 1: To rewrite data to addresses in the flash memory where data (including 0xFF) is already written, make sure that you erase the existing data by performing a sector erase or chip erase before writing data. Note 2: The data and code areas become mirror areas. As you access these areas, you are brought to the same physical address in memory. When performing a Byte Program, make sure that you write data to either of these two areas, not both. Note 3: Do not perform a Byte Program on areas other than those shown in Table 21-2. Table 21-2 Range of Addresses Specifiable (BA) FLSCR1 Address specified by instruction (Address of 4th bus write cycle) 0x8000 through 0xFFFF 00 0x8000 through 0xFFFF 0x8000 through 0xFFFF 10 0x8000 through 0xFFFF Write Area AREA D1 (Data area) AREA C1 (Code area) Page 328 RA006 TMP89FM42 21.3.2 Sector erase (4-kbyte partial erase) This command erases the flash memory in units of 4 kbytes. The flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address. The range of addresses that can be specified is shown in Table 21-3. For example, to erase 4 kbytes from 0x8000 through 0x8FFF in the code area, set FLSCR1 to "0y10", set "0xD5" on FLSCR2, and then specify either 0x8000 or 0x8FFF as the 6th bus write cycle. The sector erase command is effective only in MCU and serial PROM modes, and it cannot be used in parallel PROM mode. The time needed to erase 4 kbytes is 30 ms maximum. The next command sequence cannot be executed if an ongoing erase operation is not completed. To check the completion of the erase operation, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read from the flash memory. During the erase operation, bit 6 is reversed each time a read is performed. Data in the erased area is 0xFF. Note 1: The data and code areas become mirror areas. As you access these areas, you are brought to the same physical address in memory. When performing a sector erase, make sure that you erase data from either of these two areas, not both. Note 2: Do not perform a sector erase on areas other than those shown in Table 21-3. Table 21-3 Range of Addresses Specifiable Erase Area FLSCR1 Address specified by instruction (Address of 6th bus write cycle) 0x8000 through 0x8FFF 21.3.3 0x8000 through 0x8FFF 0x9000 through 0x9FFF 0x9000 through 0x9FFF 0xA000 through 0xAFFF 0xA000 through 0xAFFF AREA D1 0xB000 through 0xBFFF (Data area) 0xC000 through 0xCFFF 00 0xB000 through 0xBFFF 0xC000 through 0xCFFF 0xD000 through 0xDFFF 0xD000 through 0xDFFF 0xE000 through 0xEFFF 0xE000 through 0xEFFF 0xF000 through 0xFFFF 0xF000 through 0xFFFF 0x8000 through 0x8FFF 0x8000 through 0x8FFF 0x9000 through 0x9FFF 0x9000 through 0x9FFF 0xA000 through 0xAFFF 0xA000 through 0xAFFF AREA C1 0xB000 through 0xBFFF (Code area) 0xC000 through 0xCFFF 10 0xB000 through 0xBFFF 0xC000 through 0xCFFF 0xD000 through 0xDFFF 0xD000 through 0xDFFF 0xE000 through 0xEFFF 0xE000 through 0xEFFF 0xF000 through 0xFFFF 0xF000 through 0xFFFF Chip erase (all erase) This command erases the entire flash memory. The time needed to erase it is 30 ms maximum. The next command sequence cannot be executed if an ongoing erase operation is not completed. To check the completion of the erase operation, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read from the flash memory. During the erase operation, bit 6 is reversed each time a read is performed. Data in the erased area is 0xFF. Page 329 RA006 21. 21.4 Flash Memory Toggle Bit (D6) TMP89FM42 21.3.4 Product ID entry This command activates the product ID mode. If an instruction to read the flash memory is executed in Product ID mode, the vendor ID, flash ID and security status can be read from the flash memory. Table 21-4 Values to Be Read in Product ID Mode Address 21.3.5 Meaning Read value 0xF000 Vendor ID 0x98 0xF001 Flash ID 0x4D 0xFF7F Security status 0xFF: Security program disabled Other than 0xFF: Security program enabled Product ID exit This command is used to exit the Product ID mode. 21.3.6 Security program If the security program is enabled, the flash memory is write and read protected in parallel PROM mode, and the flash memory overwrite command and the RAM loader command cannot be executed in serial PROM mode. To disable the security program, the chip erase must be performed. To check whether the security program is enabled or disabled, read 0xFF7F in product ID mode. Refer to Table 21-4 for further details. The time needed to enable or disable the security program is 40 μs maximum. The next command sequence cannot be executed until the security program setting is completed. To check the completion of the security program setting, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read. When the security program setting is being made, bit 6 is reversed each time a read is performed. 21.4 Toggle Bit (D6) After the flash memory write, the chip erase, and the security program command sequence are executed, the value of the 6th bit (D6) in data read by a read operation is reversed each time a read is performed. This bit reversal can be used as a software mechanism for checking the completion of each operation. Normally, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read from the flash memory. After the flash memory write, the chip erase, and the security program command sequence are executed, the toggle bit read by the first read operation is always "1". Note 1: If FLSCR1 is set to "disable", the toggle bit is not reversed. Note 2: Do not read the toggle bit by using a 16-bit transfer instruction. If the toggle bit is read using a 16-bit transfer instruction, the toggle bit does not function properly. Note 3: Because the instruction cycle is longer than the write time in SLOW mode, the value is not reversed, even if the toggle bit is read right after the Byte Program is performed. Page 330 RA006 TMP89FM42 21.5 Access to the Flash Memory Area A read or a program fetch cannot be performed on the whole of the flash memory area if data is being written to the flash memory, if data in flash memory is being erased or if a security setting is being made in the flash memory. When performing these operation on the flash memory area, the flash memory cannot be directly accessed by using a program in the flash memory; the flash memory must be accessed using a program in the BOOTROM area or the RAM area. Data can be written to and read from the flash memory area in units of one byte. Data in the flash memory can be erased in units of 4 kbytes, and all data in the flash memory can be erased at one stroke. A read can be performed using one memory transfer instruction. A write or erase, however, must be performed using more than one memory transfer instruction because the command sequence method is used. For information on the command sequence, refer to Table 21-1. Note 1: To allow a program to resume control on the flash memory area that is rewritten, it is recommended that you let the program jump (return) after verifying that the program has been written properly. Note 2: Do not reset the MCU (including a reset generated due to internal factors) when data is being written to the flash memory, data is being erased from the flash memory or the security command is being executed. If a reset occurs, there is the possibility that data in the flash memory may be rewritten to an unexpected value. 21.5.1 Flash memory control in serial PROM mode The serial PROM mode is used to access the flash memory by using a control program provided in the BOOTROM area. Since almost all operations relating to access to the flash memory can be controlled simply using data supplied through the serial interface (UART or SIO), it is not necessary to operate the control register for the user. For details of the serial PROM mode, see "Serial PROM Mode". To access the flash memory in serial PROM mode by using a user-specific program or peripheral functions other than UART and SIO, it is necessary to execute a control program in the RAM area by using the RAM loader command of the serial PROM mode. How to execute this control program is described in "21.5.1.1 How to transfer and write a control program to the RAM area in RAM loader mode of the serial PROM mode". 21.5.1.1 How to transfer and write a control program to the RAM area in RAM loader mode of the serial PROM mode How to execute a control program in the RAM area in serial PROM mode is described below. A control program to be executed in the RAM area must be generated in the Intel-Hex format and be transferred using the RAM loader of the serial PROM mode. Steps 1 and 2 shown below are controlled by a program in the BOOTROM, and other steps are controlled by a program transferred to the RAM area. The following procedure is linked with a program example to be explained later. 1. 2. 3. 4. 5. 6. 7. 8. 9. Transfer the write control program to the RAM area in RAM loader mode. Jump to the RAM area. Set a nonmaskable interrupt vector in the RAM area. Set FLSCR1 to "0y101", and specify the area to be erased by making the appropriate FLSCR1 setting. (Make the appropriate FLSCR1 setting as required.) Then set "0xD5" on FLSCR2. Execute the erase command sequence. Read the same flash memory address twice consecutively. (Repeat step 6 until the read values become the same.) Specify the area (area erased in step 5 above) to which data is written by making the appropriate FLSCR1 setting. (Make the appropriate FLSCR1 setting as required.) Then set "0xD5" on FLSCR2. Execute the write command sequence. Read the same flash memory address twice consecutively. (Repeat step 9 until the read values become the same.) Page 331 RA006 21. 21.5 Flash Memory Access to the Flash Memory Area TMP89FM42 10. Set FLSCR1 to "0y010", and then set "0xD5" on FLSCR2 (to disable the execution of the command sequence). Note 1: If the RAM loader is used in serial PROM mode, the BOOTROM disables (DI) a maskable interrupt, and the interrupt vector area is designated as a RAM area (SYSCR3="1"). Considering that a nonmaskable interrupt may be generated unexpectedly, it is recommended that vector addresses corresponding these interrupts (INTUNDEF, INTSWI: 0x01F8 to 0x01F9, WDT: 0x01FC to 0x01FD) be established and that an interrupt service routine be defined inside the RAM area. Note 2: If a certain interrupt is used in the RAM loader program, a vector address corresponding to that interrupt and the interrupt service routine must be established inside the RAM area. In this case, it is recommended that a nonmaskable interrupt be handled as explained in Note 1. Note 3: Do not set SYSCR3 to "0" by using the RAM loader program. If an interrupt occurs with SYSCR3 set to "0", the BOOTROM area is referenced as a vector address and, therefore, the program will not function properly. Example: A case in which a program is transferred to RAM, the sector erase is performed on 0xE000 through 0xEFFF in the code area, and then data of 0x3F is written to 0xE500. If nonmaskable interrupts (INTSWI, INTUNDEF or INTWDT) occur, system clock reset is generated. main section code abs = 0x0100 ; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3) LD HL,0x01FC LDW (HL),sINTSWI ; Set INTUNDEF and INTSWI interrupt vectors LD HL,0x01F8 LDW (HL),sINTWDT ; Set INTWDT interrupt vector ; #### Sector erase and write process #### LD HL,0xF555 ; Variable for command sequence LD DE,0xFAAA ; Variable for command sequence LD C,0x00 ; Set upper address LD IX,0xE000 ; Set middle and lower addresses CALL sSectorErase ; Perform a sector erase (0xE000) LD C,0x00 ; Set upper address LD IX,0xE500 ; Set middle and lower addresses LD B,0x3F ; Data to be written CALL sByteProgram ; Write process (0xE500) ; Sector erase process (step 5) ; Write process (step 8) ; #### Execute the next main program #### : : J XXXXX ; Execute the main program ; #### Program to be executed in RAM #### sSectorErase: CALL sAddConv ; Address conversion process LD (HL),E ; 1st Bus Write Cycle (note 1) LD (DE),L ; 2nd Bus Write Cycle (note 1) LD (HL),0x80 ; 3rd Bus Write Cycle (note 1) LD (HL),E ; 4th Bus Write Cycle (note 1) LD (DE),L ; 5th Bus Write Cycle (note 1) LD (IX),0x30 ; 6th Bus Write Cycle (note 1) J sRAMopEnd CALL sAddConv ; Convert address LD (HL),E ; 1st Bus Write Cycle (note 1) LD (DE),L ; 2nd Bus Write Cycle (note 1) LD (HL),0xA0 ; 3rd Bus Write Cycle (note 1) LD (IX),B ; 4th Bus Write Cycle (note 1) ; Sector erase process ; Write process sByteProgram: Page 332 RA006 TMP89FM42 ; End process sRAMopEnd sLOOP1: NOP ; (note 2) NOP ; (note 2) NOP ; (note 2) LD A,(IX) CMP A,(IX) ; (step 6,9) J NZ,sLOOP1 ; Loop until the read values become the same LD (FLSCR1),0x40 ; Disable the execution of command sequence (step 10) LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting RET ; Return to the program in RAM ; Convert address (steps 4 and 7) sAddConv: LD WA,IX SWAP C AND C,0x10 SWAP W AND W,0x08 OR C,W XOR C,0x08 SHRC C OR C,0xA0 LD (FLSCR1),C ; Enable the execution of command sequence. Make the ; FAREA setting. sAddConvEnd: LD (FLSCR2),0xD5 LD WA,IX TEST C.3 J Z,sAddConvEnd OR W,0x80 LD IX,WA ; Reflect the FLSCR1 setting RET ; Interrupt subroutine sINTWDT: sINTSWI: LD IX,0xF000 LD A,(IX) CMP A,(IX) J NZ,sINTWDT ; Loop until the read values become the same LD (SYSCR2),0x10 ; Generate system clock reset RETN Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more than three machine cycles or arrange write instructions in such a way that they are generated at intervals of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions are executed at intervals of two machine cycles, the flash memory command sequence will not be transmitted properly, and a malfunction may occur. Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is generated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals of three or more machine cycles; machine cycles are counted from when the last xth bus write cycle is generated to when each instruction is generated. Three NOP instructions are normally used. If the interval between instructions is short, the toggle bit does not operation correctly. Page 333 RA006 21. 21.5 Flash Memory Access to the Flash Memory Area 21.5.2 TMP89FM42 Flash memory control in MCU mode In MCU mode, a write can be performed on the flash memory by executing a control program in RAM or using a support program (API) provided inside BOOTROM. 21.5.2.1 How to write to the flash memory by transferring a control program to the RAM area This section describes how to execute a control program in RAM in MCU mode. A control program to be executed in RAM must be acquired and stored in the flash memory or it must be imported from an outside source through a communication pin. (The following procedure assumes that a program copy is provided inside the flash memory.) Steps 1 through 5 and 11 shown below concern the control by a program in the flash memory, and other steps concern the control by a program transferred to RAM. The following procedure is linked with a program example to be described later. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Set the interrupt master enable flag to "disable (DI)" (IMF ← "0"). Transfer the write control program to RAM. Establish the nonmaskable interrupt vector in the RAM area. After setting both SYSCR3 and SYSCR3 to "1", set "0xD4" on SYSCR4. Then allocate RAM to the code area, and switch the vector area to the RAM area. Invoke the erase processing program in the RAM area by generating a CALL instruction. Set FLSCR1 to "0y101", and specify the area to be erased by making the appropriate FLSCR1 setting. (Make the appropriate FLSCR1 setting, as necessary.) Then set "0xD5" on FLSCR2. Execute the erase command sequence. Perform a read on the same address in the flash memory twice consecutively. (Repeat this step until the read values become the same.) After setting FLSCR1 to "0y010" and FLSCR1 to "0y00", set "0xD5" on FLSCR2. (This disables the execution of the command sequence and returns FAREA to the initial state of mapping.) Generate the RET instruction to return to the flash memory. Invoke the write program in the RAM area by generating a CALL instruction. Set FLSCR1 to "0y101", and make the appropriate FLSCR1 setting to specify the area (area erased by performing step 7 above) on which a write is to be performed. (Make the appropriate FLSCR1 setting, as necessary.) Then set "0xD5" on FLSCR2. Execute the write command sequence. Perform a read on the same address in the flash memory twice consecutively. (Repeat this step until the read values become the same.) After setting FLSCR1 to "0y010" and FLSCR1 to "0y00", set "0xD5" on FLSCR2. (This disables the execution of the command sequence and returns FAREA to the initial state of mapping.) Generate the RET instruction to return to the flash memory. After setting both SYSCR3 and SYSCR3 to "0", set "0xD4" on SYSCR4. Then release RAM allocation for the code area, and switch the vector area to the flash area. Note 1: Before writing data to the flash memory from the RAM area in MCU mode, the vector area must be switched to the RAM area by using SYSCR3, data must be written to the vector addresses (INTUNDEF, INTSWI: 0x01F8 to 0x01F9, INTWDT: 0x01FC to 0x01FD) that correspond to nonmaskable interrupts, and the interrupt subroutine (RAM area) must be defined. This allows you to trap the errors that may occur due to an unexpected nonmaskable interrupt during a write. If SYSCR3 is set in the flash memory area and if an unexpected interrupt occurs during a write, a malfunction may occur because the vector area in the flash memory cannot be read properly. Note 2: Before using a certain interrupt in MCU mode, the vector address corresponding to that interrupt and the interrupt service routine must be established inside the RAM area. In this case, the nonmaskable interrupt setting must be made, as explained in Note 1. Page 334 RA006 TMP89FM42 Note 3: Before jumping from the flash memory to the RAM area, RAM must be allocated to the code area by making the appropriate SYSCR3 setting (setting made in step 4 in the procedure described on the previous page). Example: Case in which a program is transferred to RAM, a sector erase is performed on 0xE000 through 0xEFFF in the code area, and then 0x3F data is written to 0xE500. If nonmaskable interrupts (INTSWI, INTUNDEF or INTWDT) occur, system clock reset is generated. cRAMStartAdd equ 0x0200 ; RAM start address main section code abs = 0xF000 DI ; Disable interrupts (step 1) ; #### Transfer the program to RAM #### (step 2) sRAMLOOP: LD HL,cRAMStartAdd LD IX,sRAMprogStart LD A,(IX) ; Transfer the program from sRAMprogStart to LD (HL),A ; sRAMprogEnd to cRAMStartAdd. INC HL INC IX CMP IX,sRAMprogEnd J NZ,sRAMLOOP ; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3) LD HL,0x01FC ; Set INTUNDEF and INTSWI interrupt vectors LDW (HL),sINTSWI - sRAMprogStart + cRAMStartAdd LD HL,0x01F8 LDW (HL),sINTWDT - sRAMprogStart + cRAMStartAdd ; Set INTWDT interrupt vector ; #### Allocate RAM to the code area. Switch the vector area to RAM #### (step 4) LD (SYSCR3),0x06 ; Set RAREA and RVCTR to "1" LD (SYSCR4),0xD4 ; Enable Code ; #### Sector erase and write process #### LD HL,0xF555 ; Variable for command sequence LD DE,0xFAAA ; Variable for command sequence LD C,0x00 ; Set upper addresses LD IX,0xE000 ; Set middle and lower addresses CALL sSectorErase - sRAMprogStart + cRAMStartAdd ; Sector erase process (step 5) ; Perform a sector erase (0xE000) ; Write process (step 11) LD C,0x00 ; Set upper addresses LD IX,0xE500 ; Set middle and lower addresses LD B,0x3F ; Data to be written CALL sByteProgram - sRAMprogStart + cRAMStartAdd ; Write process (0xE500) ; #### Allocate RAM to the code area. Switch the vector area to RAM #### (step 17) LD (SYSCR3),0x00 ; Set RAREA and RVCTR to "0" LD (SYSCR4),0xD4 ; Enable Code ; #### Execute the next main program #### : : J XXXXX ; Execute the main program ; #### Program to be executed in RAM #### sRAMprogStart: NOP ; Fail-safe process NOP NOP Page 335 RA006 21. 21.5 Flash Memory Access to the Flash Memory Area TMP89FM42 NOP NOP sSectorErase: LD (SYSCR2),0x10 CALL sAddConv - sRAMprogStart + cRAMStartAdd ; Generate system clock reset ; Address conversion process ; Sector erase process (step 7) LD (HL),E ; 1st Bus Write Cycle (note 1) LD (DE),L ; 2nd Bus Write Cycle (note 1) LD (HL),0x80 ; 3rd Bus Write Cycle (note 1) LD (HL),E ; 4th Bus Write Cycle (note 1) LD (DE),L ; 5th Bus Write Cycle (note 1) LD (IX),0x30 ; 6th Bus Write Cycle (note 1) J sRAMopEnd ; Write process (step 13) sByteProgram: CALL sAddConv - sRAMprogStart + cRAMStartAdd LD (HL),E ; 1st Bus Write Cycle (note 1) LD (DE),L ; 2nd Bus Write Cycle (note 1) LD (HL),0xA0 ; 3rd Bus Write Cycle (Note 1) LD (IX),B ; 4th Bus Write Cycle (note 1) ; Address conversion process ; End process sRAMopEnd: sLOOP1: NOP ; (note 2) NOP ; (note 2) NOP ; (note 2) LD A,(IX) CMP A,(IX) ; (steps 8,14) J NZ,sLOOP1 ; Loop until the read values become the same LD (FLSCR1),0x40 ; Disable the execution of command sequence ; (steps 9 and 15) LD (FLSCR2),0xD5 RET ; Reflect the FLSCR1 setting ; Return to flash memory ; Address conversion process (steps 6 and 12) sAddConv: LD WA,IX SWAP C AND C,0x10 SWAP W AND W,0x08 OR C,W XOR C,0x08 SHRC C OR C,0xA0 LD (FLSCR1),C LD (FLSCR2),0xD5 LD WA,IX TEST C.3 J Z,sAddConvEnd OR W,0x80 LD IX,WA ; Enable the execution of command sequence. Make the ; FAREA setting. sAddConvEnd: RET ; Interrupt subroutine Page 336 RA006 ; Reflect the FLSCR1 setting TMP89FM42 sINTWDT: sINTSWI: LD IX,0xF000 LD A,(IX) CMP A,(IX) J NZ,sINTWDT ; Loop until the read values become the same LD (SYSCR2),0x10 ; Generate system clock reset RETN sRAMprogEnd: NOP Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more than three machine cycles or arrange write instructions in such a way that they are generated at intervals of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions are executed at intervals of two machine cycles, the flash memory command sequence will not be transmitted properly, and a malfunction may occur. Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is generated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals of three or more machine cycles; machine cycles are counted from when the last xth bus write cycle is generated to when each instruction is generated. Three NOP instructions are normally used. If the interval between instructions is short, the toggle bit does not operation correctly. Page 337 RA006 21. 21.5 Flash Memory Access to the Flash Memory Area 21.5.2.2 TMP89FM42 How to write to the flash memory by using a support program (API) of BOOTROM TMP89FM42 has following support program (API) inside BOOTROM. The following shows how to perform an erase and a write on the flash memory by using a support program (API) of BOOTROM in MCU mode. For details, please refere to "21.6 API (Application Programming Interface)". Steps 1 through 16 shown below concern the control by a program in the flash memory. 1. Transfer the subroutine program of nonmaskable interrupt (INTSWI, INTWDT) to RAM. 2. Establish the nonmaskable interrupt vector in the RAM area. 3. After setting both SYSCR3 and SYSCR3 to "1", set "0xD4" on SYSCR4. Then allocate RAM to the code area, and switch the vector area to the RAM area. 4. Set "0xD5" on FLSCR2 after setting FLSCR1 to "1". 5. Set the erasing address range to A register. For example, to erase sector area from 0xE000 through 0xEFFF, set 0x0E to register.To erase sector area from 0x1F000 through 0x1FFFF, set 0x1F to register. 6. Set "0xD5" to C register as enable code. 7. Call address (0x1012). (Sector erase is performed. It is not necessary from 2 through 4 steps, if programing area is already erased beforehand.) 8. Set "0x00" to C register. 9. Set A[15:0] of address for programing to WA register. 10. Set programing data to E register. 11. Set "0xD5" to (SP-) as enable code. 12. Call address (0x1010). (Byte program is performed) 13. If programing is continued for other address, return to step 8. 14. Set "0xD5" to FLSCR2 after setting FLSCR1 to "0". 15. Set "0xD4" to SYSCR4 after setting SYSCR3 to "0". Example: Case in which a sector erase is performed on 0xE000 through 0xEFFF in the data area, and then data at 0x0100 through 0x01FF is written to 0xE000 through 0xE0FF in the data area. If nonmaskable interrupts (INTSWI, INTUNDEF or INTWDT) occur, system clock reset is generated. .BTWrite equ 0x1010 ; Write data to the flash memory .BTEraseSec equ 0x1012 ; Sector Erase .BTEraseChip equ 0x1014 ; Chip Erase .BTGetRP equ 0x1016 ; Check the status of the security program .BTSetRP equ 0x1018 ; Configure the security program cRAMStartAdd equ 0x0200 ; RAM start address main section code abs = 0xF000 ; #### Transfer the program to RAM #### sRAMLOOP: LD HL,cRAMStartAdd LD IX,sRAMprogStart LD A,(IX) ; Transfer the program from sRAMprogStart to LD (HL),A ; sRAMprogEnd to cRAMStartAdd. INC HL INC IX CMP IX,sRAMprogEnd J NZ,sRAMLOOP ; #### Set a nonmaskable interrupt vector inside the RAM area #### LD HL,0x01FC LDW (HL),sINTSWI - sRAMprogStart + cRAMStartAdd ; Set INTUNDEF and INTSWI interrupt vectors LD HL,0x01F8 LDW (HL),sINTWDT - sRAMprogStart + cRAMStartAdd ; Set INTWDT interrupt vector ; #### Allocate RAM to the code area. Switch the vector area to RAM #### Page 338 RA006 TMP89FM42 LD (SYSCR3),0x06 ; Set RAREA and RVCTR to "1" LD (SYSCR4),0xD4 ; Enable Code ; #### Allocate BOOTROM to the data/code area #### LD (FLSCR1),0x50 ; Set BAREA to "1" (note) LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting ; #### Sector erase process (API) #### LD A,0x0E ; Specify the area to be erased (0xE000 through 0xEFFF) LD C,0xD5 ; Enable Code CALL (.BTEraseSec) ; Execute sector erase LD HL,0xE000 ; Flash start address (address where data is written) LD IY,0x0100 ; RAM start address LD C,0x00 ; Address where data is written (bit 16) LD WA,HL ; Address where data is written (bits 15 to 0) LD E,(IY) ; Data to be written LD (SP-),0xD5 ; Enable Code CALL (.BTWrite) ; Write data to the flash memory (1 byte) INC IY ; Increment flash address INC HL ; Increment RAM address CMP L,0x00 ; Finish 256-byte write? J NZ,sLOOP1 ; Return to sLOOP1 if the number of bytes is less than 256 LD (FLSCR1),0x40 ; Set BAREA to "0" LD (FLSCR2),0xD5 LD (SYSCR3),0x00 ; Set RAREA and RVCTR to "0" LD (SYSCR4),0xD4 ; Enable Code : : J XXXX ; #### Write process #### sLOOP1: ; #### End process #### ; #### Program to be executed in RAM #### sRAMprogStart: ; Interrupt subroutine sINTWDT: sINTSWI: LD IX,0xF000 LD A,(IX) CMP A,(IX) J NZ,sINTWDT ; Loop until the read values become the same LD (SYSCR2),0x10 ; Generate system clock reset RETN sRAMprogEnd: NOP Note 1: It is not necessary to add DI instruction for above example program, because the support program include it. However, the support program does not include EI instruction. Therefore, if interrupt process is used, enable IMF after finishing all above process. 21.5.2.3 How to set the security program by using a support program (API) of BOOTROM 1. Transfer the subroutine program of nonmaskable interrupt (INTSWI, INTWDT) to RAM. 2. Establish the nonmaskable interrupt vector in the RAM area. 3. After setting both SYSCR3 and SYSCR3 to "1", set "0xD4" on SYSCR4. Then allocate RAM to the code area, and switch the vector area to the RAM area. Page 339 RA006 21. 21.5 Flash Memory Access to the Flash Memory Area 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. TMP89FM42 Set "0xD5" on FLSCR2 after setting FLSCR1 to "1". Set "0xD5" to A register as enable code. Set "0x00" to C register. Call address (0x1016). (After processing, security program state returns to A register.) If A register is not "0xFF", jump to sSKIP because security program is already set. Set "0xD5" to A register as enable code. Set "0x00" to C register. Call address (0x1016). (Security program is performed.) Set "0xD5" to FLSCR2 after setting FLSCR1 to "0". Set "0xD4" to SYSCR4 after setting SYSCR3 to "0". Example: Whether the security program is enabled or disabled is checked. If it is disabled, it is enabled. .BTWrite equ 0x1010 ; Write data to the flash memory .BTEraseSec equ 0x1012 ; Sector Erase .BTEraseChip equ 0x1014 ; Chip Erase .BTGetRP equ 0x1016 ; Check the status of the security program .BTSetRP equ 0x1018 ; Enable the security program cRAMStartAdd equ 0x0200 ; RAM start address main section code abs = 0xF000 ; #### Transfer the program to RAM #### sRAMLOOP: LD HL,cRAMStartAdd LD IX,sRAMprogStart LD A,(IX) ; Transfer the program from sRAMprogStart to LD (HL),A ; sRAMprogEnd to cRAMStartAdd. INC HL INC IX CMP IX,sRAMprogEnd J NZ,sRAMLOOP ; #### Set a nonmaskable interrupt vector inside the RAM area #### LD HL,0x01FC LDW (HL),sINTSWI - sRAMprogStart + cRAMStartAdd ; Set INTUNDEF and INTSWI interrupt vectors LD HL,0x01F8 LDW (HL),sINTWDT - sRAMprogStart + cRAMStartAdd ; Set INTWDT interrupt vector ; #### Allocate RAM to the code area. Switch the vector area to RAM #### LD (SYSCR3),0x06 ; Set RAREA and RVCTR to "1" LD (SYSCR4),0xD4 ; Enable Code ; #### Allocate BOOTROM to the data/code area #### LD (FLSCR1),0x50 ; Set BAREA to "1" LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting ; #### Check the status of the security program #### LD A,0xD5 ; Enable Code LD C,0x00 ; Set 0x00 (note 1) CALL (.BTGetRP) ; Check the status of the security program CMP A,0xFF J NZ,sSKIP ; Go to sSKIP if the security program is enabled ; #### Security program enable process (API) #### LD A,0xD5 ; Enable Code LD C,0x00 ; Set 0x00 (note 1) CALL (.BTSetRP) ; Enable the security program Page 340 RA006 TMP89FM42 sSKIP LD (FLSCR1),0x40 LD (FLSCR2),0xD5 ; Set BAREA to "0" LD (SYSCR3),0x00 ; Set RAREA and RVCTR to "0" LD (SYSCR4),0xD4 ; Enable Code : : J XXXX ; #### Program to be executed in RAM #### sRAMprogStart: ; Interrupt subroutine sINTWDT: sINTSWI: LD IX,0xF000 LD A,(IX) CMP A,(IX) J NZ,sINTWDT ; Loop until the read values become the same LD (SYSCR2),0x10 ; Generate system clock reset RETN sRAMprogEnd: NOP Note 1: Make sure that you set the C register to "0x00". Note 2: It is not necessary to add DI instruction for above example program, because the support program include it. However, the support program does not include EI instruction. Therefore, if interrupt process is used, enable IMF after finishing all above process. 21.5.2.4 How to read data from flash memory To read data from flash memory, execute transfer instruction for memory. It is possible to read the corresponding individual data (include data of code area) to each address in flash memory, if FLSCR1 and FLSCR2 is selected properly. Example: Case in which data is read from 0xF000 in the code area and stored at 0x98 in RAM LD (FLSCR1),0xA8 ; Select AREA C1 LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting LD A,(0xF000) ; Read data from 0xF000 LD (0x98),A ; Store data at 0x98 LD (FLSCR1),0x40 ; Select AREA D0 LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting Page 341 RA006 21. 21.6 Flash Memory API (Application Programming Interface) 21.6 TMP89FM42 API (Application Programming Interface) The BOOTROM has a support program (API) which contains a special subroutine for erasing or writing on the flash memory. After mapping of the BOOTROM, it allows easy erasing or writing on the flash memory by only calling the subroutine in BOOTROM. The Table 21-5 shows the list of API. Table 21-5 List of API Address Contents Using Working Stack Register (Note2) (Note1) Writing the data to specified address of one byte. 0x1010 Setting Value Register WA Specify the address to be written. - - - - - - - - - A 0xFF Security Program disabled. Other than 0xFF Security Program enabled. BC C 0x00 DE E Specify the data to be written. IX (SP-) 0x1012 Erasing the specified one sector. WA 4bytes (.BTEraseSec) Contents 0xD5 (Enable Code) A Specify the sector to be erased. C 0xD5 (Enable Code) WA A 0xD5 (Enable Code) BC C 0x00 A 0xD5 (Enable Code) C 0x00 WA A 0xD5 (Enable Code) BC C 0x00 BC DE Return value Register WA 7bytes (.BTWrite) Argument IX 0x1014 Executing the Chip Erase. 6bytes (.BTEraseChip) DE IX 0x1016 Getting the status of Security Program. WA 6bytes (.BTGetRP) BC DE IX 0x1018 Setting the Security Program. 6bytes (.BTSetRP) - - - DE IX 0x101E (.BTCalcUART) Calculating the setting for UART (Baud rate) from the captured value by timer counter. WA WA Captured value by timer counter W Setting value for RTSEL C The number of bit for calculation. A Setteing value for UARTDR BC 4bytes DE IX IY Note 1: Because working registers (general-purpose registers) are rewritten in the support program, the contents of generalpurpose registers should be saved before calling the support program. Note 2: While the support program is executed, a maximum 7 bytes are used as stack which doesn’t include the stack used by interrupts. Therefore, be sure to reserve a stack area beforehand. Note 3: Each API works properly without the setting Enable Code (0xD5) as argument. However, it is recommended to set the Enable Code (0xD5) to keep compatibility in the family products. Page 342 RA006 TMP89FM42 21.6.1 .BTWrite Data in E register is written into the address specified by WA register. C register should be written 0x00 and (SP-) should be written Enable Code (0xD5) before calling the subroutine. 21.6.2 .BTEraseSec The sector specified by A register is erased. C register should be written Enable Code (0xD5) before calling the subroutine. Table 21-6 shows the sector erased by this API. Table 21-6 Erased Sector by setting of A register A register Erased area 0x08 0x8000 through 0x8FFF 0x09 0x9000 through 0x9FFF 0x0A 0xA000 through 0xAFFF 0x0B 0xB000 through 0xBFFF 0x0C 0xC000 through 0xCFFF 0x0D 0xD000 through 0xDFFF 0x0E 0xE000 through 0xEFFF 0x0F 0xF000 through 0xFFFF Others Reserved Note:Reserved : Do not set the reserved data into A register. Unexpected sector might be erased by the reserved data setting. 21.6.3 .BTEraseChip All flash memory area is erased. C register should be written 0x00 and A register should be written Enable Code (0xD5) before calling the subroutine. 21.6.4 .BTGetSP The security status of flash memory can be read out. C register should be written 0x00 and A register should be written Enable Code (0xD5) before calling the subroutine. After completion of the execution, API returns A register with the contents of 0xFF7F (security status) in Product ID as return value. 21.6.5 .BTSetSP The setting of security program can be executed by this API. C register should be written 0x00 and A register should be written Enable Code (0xD5) before calling the subroutine. Page 343 RA006 21. 21.6 Flash Memory API (Application Programming Interface) 21.6.6 TMP89FM42 .BTCalcUART This API calculates the proper setting for baud rate of UART from the value of C and WA register. Generally, 8 bits data (0x80) of UART is captured by 16-bit timer counter which is set to pulse width measurement mode. In this case, the timer counter input pin should be assigned to RXD pin. And stores the captured value in WA register. Be sure to select fcgck/2 as the source clock for 16-bit timer counter and capture the length of 8 bits. C register should be written 0x08. RXD pin can be used as TCA pin. To capture the value, please select the pin as TCA pin by SERSEL temporarily. After capturing, be sure to resume the pin to RXD pin. The possible value for WA register as argument is from 0x0020 to 0x3BFF. In the return value of WA register, bits 5, 4 and 3 are suitable value for UARTCR2 and the return value of A register is a suitable data for UARTDR. The API sets bits 7, 6, 2, 1 and 0 to "0" as return value. Therefore, set the proper value for UARTCR2. If the contents of WA register is out of the area 0x0020 to 0x3BFF, the API returns WA register with 0xFFFF as return value. Note 1: If the captured value of WA register is little even though the value is within 0x0020 to 0x3BFF, the proper setting may not be gotten. The following procedure shows example how to calculate the baud rate for UART in MCU mode by using support program. 1. By serial interface selection control register SERSEL, assign TCA pin to RXD pin. 2. Set 16-bit timer counter to pulse width measurement mode. And set falling edge/L level as an external trigger and select fcgck/2 as the source clock. 3. Receive data (0x80) via RXD pin and capture it by 16-bit timer counter. In this case, enabling of UART is no need. 4. Write the captured value into WA register. Because general-purpose registers (DE, BC, IX, IY) are rewritten in the support program, the contents of these registers should be saved before calling the support program. 5. Set the interrupt master enable flag to "disable (DI)" (IMF ← "0"). 6. Set "0xD5" on FLSCR2 after setting FLSCR1 to "1". 7. Set "0x08" to C register as the number of bit. 8. Call address (0x101E). 9. Set bits 5, 4 and 3 of W register into UARTCR2 and set the contents of A register to UARTDR. If the value of WA register is 0xFFFF which indicates an error of calculation, retry the execution from receiving data (0x80). 10. Set "0xD5" to FLSCR2 after setting FLSCR1 to "0". Note 1: If general-purpose registers (WA, BC, DE, IX, IY) are used in non-maskable interrupt subroutine, occurring of non-maskable interrupt may cause unexpected result. Note 2: With success of calculation, this API returns "0" into bits 7, 6, 2, 1 and 0 as return value. Therefore, set proper value for these bits to set UART0CR2 and UART0CR2. Page 344 RA006 TMP89FM42 Example: Captures the low width of 8 bit value via RXD pin by 16-bit timer counter which is set to the pulse width measurement mode. And calculates baud rate for UART from the captured value. .BTCalcUART equ 0x101E ; Calculating the setting for UART (Baud rate) CalcUART secion code abs = 0xF000 ; #### Assign TCA input to RXD pin #### LD (SERSEL),0x40 ; Assign TCA0 pin to RXD pin¶ ; #### Receive data (0x80) from a master device #### LD (TA0MOD),0x5E ; Set the pulse width measurement mode and select falling ; edge/L level for external trigger ; Select fcgck/2 as the surce clock sTimerStart: LD (TA0CR),0x01 : ; Timer start : Receives data (0x80) via TCA0 pin : : LD WA,(TA0DRL) ; Write the captured data into WA register LD (TA0CR), 0x00 ; Timer stop DI ; #### Allocate BOOTROM to the data/code area #### LD (FLSCR1),0x50 ; Set BAREA to "1" LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting ; #### Calculation for UART setting (API) #### LD C,0x08 ; The number of bit length (8 bit) CALL (.BTCalcUART) ; Calculate UART setting CMP W, 0xFF J Z, sTimerStart ; Return to sTimerStart if W register equals 0xFF ; #### Setting the calculated result to UART registers #### LD (UARTCR2),W ; Set RTSEL LD (UARTDR), A ; Set UARTDR LD (FLSCR1),0x40 ; Set BAREA to "0" LD (FLSCR2),0xD5 ; Reflect the FLSCR1 setting ; #### End process #### Page 345 RA006 21. 21.7 Flash Memory Revision History 21.7 TMP89FM42 Revision History Rev RA003 Description "Figure 21-7 Show/Hide Switching for BOOTROM and RAM" Revised from WDTCR1 to SYSSR4 Revised example program (Added fail safe process) RA004 "21.5.2.1 How to write to the flash memory by transferring a control program to the RAM area", "21.5.2.2 How to write to the flash memory by using a support program (API) of BOOTROM" Revised register name from FLSCR4 to SYSCR4. "21.5.2.2 How to write to the flash memory by using a support program (API) of BOOTROM" Added new detail description and note. "21.5.2.3 How to set the security program by using a support program (API) of BOOTROM", "21.5.2.4 How to read data from flash memory" Added new chapter. RA005 "21.5.2.1 How to write to the flash memory by transferring a control program to the RAM area" Added fail-safe process to example program. Added step 17. "21.5.2.2 How to write to the flash memory by using a support program (API) of BOOTROM" Added new table for support program. RA006 "21.6 API (Application Programming Interface)" Added new chapter. Page 346 RA006 TMP89FM42 22. Serial PROM Mode 22.1 Outline The TMP89FM42 has a 4K-byte BOOTROM (Mask ROM) for programming to flash memory. BOOTROM is available in serial PROM mode. The serial PROM mode is controlled by RXD0/SI0 pins, TXD0/SO0 pins, MODE pin, and RESET pin. In serial PROM mode, communication is performed via the UART or SIO. Table 22-1 Operating Range in Serial PROM Mode Parameter Power supply voltage High frequency 22.2 Min Max Unit 4.5 5.5 V 1 10 MHz Security In serial PROM mode, two security functions are provided to prevent illegal memory access attempts by a third party: password and security program functions. For more security-related information, refer to "22.12 Security". Page 347 RA003 22. 22.3 Serial PROM Mode Serial PROM Mode Setting 22.3 TMP89FM42 Serial PROM Mode Setting 22.3.1 Serial PROM mode control pins To execute on-board programming, activate the serial PROM mode. Table 22-2 shows the pin setting used to activate the serial PROM mode. Table 22-2 Serial PROM Mode Setting Pin Setting RXD0 / SI0 / P21 pin H level TXD0 / SO0 / P20 pin H level MODE, RESET pin Note:Before you activate the serial PROM mode, you must set the RXD0/SI0/P21 and TXD0/SO0/P20 pins to high (H) level by using a pull-up resistor. Table 22-3 Pin Functions in Serial PROM Mode Pin name (in serial PROM mode) Input/output TXD0 / SO0 Output RXD0 / SI0 RESET MODE Function Serial PROM mode control/serial data output TXD0 / SO0 / P20 Input Serial PROM mode control/serial data input RXD0 / SI0 / P21 Input Serial PROM mode control RESET Input Serial PROM mode control Serial clock input (if SIO is used) SCLK0 Input Power VDD supply VAREF / AVDD Power supply Power VSS supply Input/ Input/output port other than RXD0 and TXD0 output XIN Input XOUT Pin name (in MCU mode) Output These ports are in the high-impedance state in the serial PROM mode. If the UART is used, the port input is physically fixed to a specified input level in order to prevent a penetration current. To enable the port input, the SPCR must be set to "1" by operating the RAM loader control program. MODE (See note 1) SCLK0 4.5 V to 5.5 V Connect to VDD. 0V These ports are in the high-impedance state in the serial PROM mode. The port input is physically fixed to a specified input level in order to prevent a penetration current (the port input is disabled). To enable the port input, the SPCR must be set to "1" by operating the RAM loader control program. Connect a resonator to make these pins self-oscillate. Note 1: If other parts are mounted on a user board, they may interfere with data being communicated through these communication pins during on-board programming. It is recommended that these parts be somehow isolated to prevent the pins from being affected. Page 348 RA003 TMP89FM42 TMP89FM42 VDD (4.5 V to 5.5 V) VDD XIN Pull-up resistors SCLK0 RXD0 (P21) XOUT VSS TXD0 (P20) External control RESET MODE GND Figure 22-1 Serial PROM Mode Pin Setting Note 1: In the case of access using the UART, the control of the SCLK0 pin is unnecessary. Note 2: For information on other pin settings, refer to "Table 22-3 Pin Functions in Serial PROM Mode". Page 349 RA003 22. 22.4 Serial PROM Mode Example Connection for On-board Writing 22.4 TMP89FM42 Example Connection for On-board Writing Figure 22-2 shows example connections to perform on-board writing. VDD (4.5 V to 5.5 V) VDD Pull-up resistors RXD0 (P21) Level converter TXD0 (P20) PC control (Note 2) Other parts TMP89FM42 RESET control (Note 1) RC power-on reset circuit RESET MODE Serial PROM mode MCU mode XIN XOUT VSS GND Target board External control board If UART is used VDD (4.5 V to 5.5 V) VDD Pull-up resistors SI0 (P21) Microcomputer, etc. SO0 (P20) SCLK0 (P22) (Note 2) Other parts TMP89FM42 RESET control (Note 1) RC power-on reset circuit RESET MODE Serial PROM mode MCU mode XIN XOUT VSS GND Target board External control board If SIO is used Figure 22-2 Example Connections for On-board Writing Note 1: If other parts on a target board interfere with the UART communication in serial PROM mode, disconnect these pins by using a jumper or switch. Note 2: If the reset control circuit on a target board interferes with the startup of serial PROM mode, disconnect the circuit by using a jumper, etc. Note 3: For information on other pin settings, refer to "Table 22-3 Pin Functions in Serial PROM Mode". Page 350 RA003 TMP89FM42 22.5 Activating the Serial PROM Mode Activate the serial PROM mode by performing the following procedure. For information on the detailed timing, refer to "22.14.1 Reset timing". 1. 2. 3. 4. 5. 6. Supply power to the VDD pin. Set the RESET and MODE pins to low. Set the RXD0/SI0/P21 and TXD0/SO0/P20 pins to high. Wait until the power supply and clock oscillation stabilize. Set the RESET and MODE pins from low to high. Input the matching data 0x86 or 0x30 to the RXD0/SI0/P21 pins after the setup period has elapsed. Page 351 RA003 22. 22.6 Serial PROM Mode Interface Specifications 22.6 TMP89FM42 Interface Specifications The serial PROM mode supports two communication methods: UART and SIO. The communication method is selected based on the first serial data value received after a reset. To execute an on-board program, the communication format of the external controller (personal computer, microcontroller, etc.) must be set as described below. 22.6.1 SIO communication - Transfer rate: 250 kbps (Max.) Data length: 8 bits Slave (external clock) Hardware flow control (SO0 pin) If the TMP89FM42 receives serial data "0x30" after a reset, it starts the SIO communication. In the SIO communication, the TMP89FM42 functions as a slave device. Therefore, the external controller must supply the TMP89FM42 with a serial clock (SCLK0 pin) for synchronization. If the TMP89FM42 is not outputting serial data, it controls the hardware flow by using the SO0 pin. If internal data processing is not completed yet, though data has been received, the SO0 pin outputs the L level. If internal data processing has progressed to a near-completion state or if it has been completed, the SO0 pin outputs the H level. The external controller must check the status of the SO0 pin before it starts to supply a serial clock. 22.6.2 UART communication - Baud rate: 9600 to 128000 bps (automatic detection) Data length: 8 bits (LSB first) Parity bit: None STOP bit: 1 bit If the TMP89FM42 receives serial data "0x86" after a reset, it starts the UART communication. It also measures the pulse width of the received data (0x86), and automatically establishes the reference baud rate. In all subsequent data communication transactions, this reference baud rate is used. For information on the communication timings of each operation command, refer to "22.14 AC Characteristics (UART)". Usable baud rates differ depending on the operating frequency and are shown in Table 22-4. However, there is the possibility of data communication not working properly, even if a baud rate shown in Table 22-4 is used, because data communication is affected by frequency errors of a resonator of the external controller (personal computer, etc.), the load capacity of a communication pin, and various other factors. Page 352 RA003 TMP89FM42 Table 22-4 Usable Baud Rates as a General Guideline 9600 bps 19200 bps 38400 bps 57600bps 115200 bps 128000 bps 10 MHz Ο Ο Ο Ο Ο Ο 8 MHz Ο Ο Ο Ο Ο Ο 7.3728 MHz Ο Ο Ο Ο Ο - 6.144 MHz Ο Ο Ο - - Ο 6 MHz Ο Ο Ο Ο Ο Ο 5 MHz Ο Ο Ο - - - 4.9152 MHz Ο Ο Ο Ο - - 4.19 MHz Ο Ο Ο - - Ο 4 MHz Ο Ο Ο Ο Ο Ο 2 MHz Ο Ο Ο Ο - - 1 MHz Ο Ο - Ο - - Note 1: "Ο" means a usable baud rate. "-" means an unusable baud rate. Page 353 RA003 22. Serial PROM Mode 22.7 Memory Mapping 22.7 TMP89FM42 Memory Mapping Figure 22-3 shows memory maps in serial PROM and MCU modes. In serial PROM mode, the BOOTROM (mask ROM) is mapped to the 0x1000 through 0x17FF in the data area and 0x1000 through 0x1FFF in the code area respectively. To write data to or erase data from flash memory by using the RAM loader command (hereafter called the 0x60 command) and an original program, data write or erase operations must be performed while switching between areas by using the flash memory control registers (FLSCR1 and 2). For information on how to specify addresses, refer to Flash Memory. When the command to write data to flash memory (hereafter called the 0x30 command) or the command to erase data from flash memory (hereafter called the 0xF0 command) is executed, BOOTROM automatically converts addresses. Therefore, as the address of flash memory, specify an address equivalent to that specified in MCU mode (if FLSCR1="0"), namely, 0x8000 through 0xFFFF. 0x0000 0x003F 0x0040 SFR 0x0000 0x0000 0x003F 0x0040 RAM 0x1000 0x17FF 0x8000 0x8000 FLASH 0xFFFF Data area RAM BOOTROM (2048 bytes 0x8000 FLASH 0xFFFF 0x0000 SFR 0x1000 0x17FF BOOTROM (2048 bytes 0x8000 FLASH 0xFFFF 0xFFFF Code area FLASH Data area If FLSCR1=”0” (MCU mode) Code area If FLSCR1=”1” (MCU mode) 0x0000 0x003F 0x0040 0x1000 0x17FF 0x0000 SFR RAM BOOTROM (2048 bytes 0x1000 BOOTROM (4096 bytes 0x1FFF 0x8000 0x8000 FLASH 0xFFFF FLASH 0xFFFF Data area Code area If serial PROM mode Figure 22-3 Memory Mapping 22.8 Operation Commands In serial PROM mode, the commands shown in Table 22-5 are used. After a reset is released, the TMP89FM42 goes into a standby state and awaits the arrival of matching data 1 (0x86 or 0x30). Page 354 RA003 TMP89FM42 Table 22-5 Operation Command in Serial PROM Mode Command data 0x86 or 0x30 Operation command Setup Description After a reset is released, the serial PROM mode always starts operation with this command. (matching data 1, 2) If matching data 1 is 0x86, communication starts in the UART format. If matching data 1 is 0x30, communication starts in the SIO format. 0xF0 Flash memory erase Data in the flash memory area (address 0x8000 through 0xFFFF) can be erased. 0x30 Flash memory write Data can be written to the flash memory area (address 0x8000 through 0xFFFF). 0x40 Flash memory read Data can be read from the flash memory area (address 0x8000 through 0xFFFF). 0x60 RAM loader Data can be written to a specified RAM area (address 0x0060 through 0x083F). 0x90 Flash memory SUM output 0xFF check data and 2-byte checksums of the entire flash memory area (address 0x8000 through 0xFFFF) are output in descending order (from upper to lower bytes). 0xC0 Product ID code output Product ID codes are output. 0xC3 Flash memory status output The security program status and other status codes are output. 0xD0 Mask ROM emulation setting Flash products of 124K or 96Kbytes can be provisioned to emulate a small-capacity mask ROM product. 0xFA Flash memory security setting The security program setting is enabled. Each command is outlined below. For detailed information on how each command works, refer to 22.8.1 and subsequent sections. 1. Flash memory erase command Either Chip Erase (total erase of flash memory) or Sector Erase (erase of flash memory in 4K-byte units) can be used to erase the data in flash memory. Data in the erased area is 0xFF. If the security program is enabled or if the option code EPFC_OP is 0xFF, the flash erase command of Sector Erase cannot be executed. To disable the security program setting, execute the flash erase command of Chip Erase. Before erasing the data in flash memory, the TMP89FM42 performs password authentication except where a product is a blank product or EPFC_OP is 0xFF. If a password is not authenticated, the flash memory erase command is not executed. 2. Flash memory write command Data can be written in single-byte units to a specified address in flash memory. Provision the external controller so that it transmits data to write as binary data in the Intel Hex format. If errors do not occur until the end record is reached, the TMP89FM42 calculates checksums in the entire flash memory area (0x8000 through 0xFFFF), and returns the calculation results. If the security program is enabled, the flash memory write command cannot be executed. In this case, execute Chip Erase beforehand by using the flash memory erase command. Before executing the flash memory write command, the TMP89FM42 performs password authentication except where a product is a blank product. If a password is not authenticated, the flash memory write command is not executed. 3. Flash memory read command Data can be read from a specified address in flash memory in single-byte units. Provision the external controller so that it transmits the address in memory where a read starts, as well as the number of bytes. After outputting the number of data equal to the number of bytes, the TMP89FM42 calculates the checksums of the output data, and returns the calculation results. If the security program is enabled, the flash memory read command cannot be executed. In this case, execute Chip Erase beforehand by using the flash memory erase command. Before executing the flash memory read command, the TMP89FM42 performs password authentication except where a product is blank. If a password is not authenticated, the flash memory read command is not executed. 4. RAM loader command The RAM loader transfers the Intel Hex format data sent by the external controller to the built-in RAM. If it completes the data transfer normally, it calculates the checksums, transmits the calculation results, jumps to the RAM address specified by the first data record, and starts to execute the user program. If the security Page 355 RA003 22. 22.8 Serial PROM Mode Operation Commands TMP89FM42 program is enabled, the RAM loader command is not executed. In this case, execute Chip Erase beforehand by using the flash memory erase command. Before executing the RAM loader command, the TMP89FM42 performs password authentication except where a product is blank. If a password is not authenticated, the RAM loader command is not executed. 5. Flash memory SUM output command Checksums in the entire flash memory area (0x8000 through 0xFFFF) are calculated, and the calculation results are returned. 6. Product ID code output command This is a code output used to identify a product. The output code consists of information on the ROM area and on the RAM area respectively. The external controller reads this code to identify the product to which data is to be written. 7. Flash memory status output command The status of 0xFFE0 through 0xFFFF and that of the security program are output. The external controller reads this code to identify the status of flash memory. 8. Mask ROM emulation setting command This command is nonfunctional in the TMP89FM42. It becomes functional if used for a product with flash memory of more than 96Kbytes. 9. Flash memory security setting command This command is used to prohibit the reading or writing of data in flash memory in parallel mode. In serial PROM mode, the flash memory write command and RAM loader command are prohibited. To disable the flash memory security program, execute Chip Erase by using the flash memory erase command. Page 356 RA003 TMP89FM42 22.8.1 Flash memory erase command (0xF0) Table 22-6 shows the flash memory erase commands. Table 22-6 Flash Memory Erase Commands Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment - (Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted Error: No data transmitted 5th byte Operation command data (0xF0) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0xF0) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte Password count storage address bit 23 to 16 8th byte 9th byte Baud rate after adjustment Baud rate after adjustment Password count storage address bit 15 to 08 10th byte OK: No data transmitted Error: No data transmitted Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 11th byte Password count storage address bit 07 to 00 12th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted BOOT ROM 13th byte Password comparison start address bit 23 to 16 14th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 15th byte Password comparison start address bit 15 to 08 16th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 17th byte Password comparison start address bit 07 to 00 18th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 19th byte Password string Baud rate after adjustment - - Baud rate after adjustment OK: No data transmitted : m-th byte Error: No data transmitted n-th - 2 byte Erase area specification Baud rate after adjustment - n-th - 1 byte - Baud rate after adjustment OK: Checksum (upper byte) (note 3) Error: No data transmitted n-th byte - Baud rate after adjustment OK: Checksum (lower byte) (note 3) Error: No data transmitted n-th + 1 byte (Wait for the next operation command data) Baud rate after adjustment - Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. Note 2: For information on the erase area specification, refer to "22.8.1.1 Specifying the erase area". For information on checksums, refer to "22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords". Note 3: Do not transmit a password string if 0xFFFA of a flash memory is 0xFF, or blank product. (However, the password count storage address and the password comparison start address must be transmitted.) Note 4: If a value less than 0x20 is transmitted at the n-th - 2 byte (execution of Sector Erase) and if 0xFFFA of flash memory is 0xFF, the TMP89FM42 goes into an idle state. Note 5: When a password error occurs, the TMP89FM42 stops communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 6: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM42 stops communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Page 357 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.1.1 TMP89FM42 Specifying the erase area The flash memory erase command is used to specify an area in flash memory to be erased at n-th-2 byte; specifically, ERASEC is used to specify the address of an area to be erased. If data of less than 0x20 is specified, Sector Erase (erasing flash memory in 4K-byte units) is executed. Executing Sector Erase with 0xFFFA memory set to "0xFF" or with the security program enabled will cause the device to go into an infinite loop state. If data of more than 0x20 is specified, Chip Erase (total erasure of flash memory) is executed, and the security program in flash memory is disabled. Therefore, to disable the security program in flash memory, execute Chip Erase, not Sector Erase. Page 358 RA003 TMP89FM42 Erase area specification data (data at n-th-2 bytes) 7 6 5 4 3 2 1 0 ERASEC ERASEC Erase area start address 0x00 Reserved 0x01 Reserved 0x02 Reserved 0x03 Reserved 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07 Reserved 0x08 0x8000 - 0x8FFF 0x09 0x9000 - 0x9FFF 0x0A 0xA000 - 0xAFFF 0x0B 0xB000 - 0xBFFF 0x0C 0xC000 - 0xCFFF 0x0D 0xD000 - 0xDFFF 0x0E 0xE000 - 0xEFFF 0x0F 0xF000 - 0xFFFF 0x10 Reserved 0x11 Reserved 0x12 Reserved 0x13 Reserved 0x14 Reserved 0x15 Reserved 0x16 Reserved 0x17 Reserved 0x18 Reserved 0x19 Reserved 0x1A Reserved 0x1B Reserved 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved 0x20 or more Chip Erase (erasure of the entire area) Note 1: If Sector Erase is performed on an area where flash memory does not exist, the TMP89FM42 stops communication, and goes into an idle state. Note 2: If Reserved data is transmitted, the TMP89FM42 stops communication, and goes into an idle state. Page 359 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.2 TMP89FM42 Flash memory write command (operation command: 0x30) Table 22-7 shows the transfer formats of flash memory write commands. Table 22-7 Transfer Formats of Flash Memory Write Commands Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment - (Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) Error: No data transmitted 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted 5th byte Operation command data (0x30) Baud rate after adjustment OK: Echo back data (0x30) 6th byte - Baud rate after adjustment Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte 8th byte Password count storage address 23 to 16 Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 9th byte Password count storage address 15 to 08 10th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 11th byte Password count storage address 07 to 00 12th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 13th byte Password comparison start address 23 to 16 14th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted BOOT ROM Error: No data transmitted 15th byte Password comparison start address 15 to 08 16th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 17th byte Password comparison start address 07 to 00 18th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 19th byte Password string (note) Baud rate after adjustment - - Baud rate after adjustment OK: No data transmitted : m-th byte Error: No data transmitted m-th+1 byte : Baud rate after adjustment Intel Hex format (binary) n-th-3 byte - n-th-2 byte - Baud rate after adjustment n-th-1 byte - Baud rate after adjustment OK: 0x55 Overwrite detect: 0xAA OK: Checksum (high) (note 3) Error: No data transmitted n-th byte - Baud rate after adjustment n-th+1 byte (Wait for the next operation command data) Baud rate after adjustment OK: Checksum (low) (note 3) Error: No data transmitted - Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to Table 22-18. Note 2: For information on the Intel Hex format, refer to "22.11 Intel Hex Format (Binary)". For information on checksums, refer to "22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords". Note 3: If the area 0xFFE0 through 0xFFFF is all 0xFF, password authentication is not performed and, therefore, the password string need not be transmitted. The password count storage address and password comparison start address, however, must be specified, even for a blank product. If the password count storage address and/or password comparison start Page 360 RA003 TMP89FM42 address is/are incorrect, a password error occurs, the TMP89FM42 stops communication, and it goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 4: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM42 stops communication, and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 5: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM42 stops communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 6: If all data in flash memory are the same data, make sure that you never write data to the address 0xFFE0 through 0xFFFF. If data is written to this address, a password error occurs, and the subsequent operations cannot be performed. Note 7: The n-th-2 byte is a flag for detecting an overwrite. If memory contents at an address where data is to be written are other than 0xFF, the n-th-2 byte is 0xAA (data is not written to this address, and the data write routine is skipped). The checksum at the n-th-1 byte or n-th byte is calculated based on data in which data in memory areas where data was not written are included. Therefore, if an overwrite is detected, the checksum of transmitted data does not match that at the n-th-1 byte or n-th byte. Page 361 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.3 TMP89FM42 Flash memory read command (operation command: 0x40) Table 22-8 shows the transfer formats of the flash memory read command. Table 22-8 Transfer Formats of the Flash Memory Read Command Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment - (Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) Error: No data transmitted 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted 5th byte Operation command data (0x40) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0x40) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte Password count storage address 23 to 16 8th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 9th byte Password count storage address 15 to 08 10th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 11th byte Password count storage address 07 to 00 12th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 13th byte Password comparison start address 23 to 16 14th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 15th byte BOOT Password comparison start address 15 to 08 16th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted ROM Error: No data transmitted 17th byte Password comparison start address 07 to 00 18th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 19th byte Password string Baud rate after adjustment - - Baud rate after adjustment OK: No data transmitted : m-th byte Error: No data transmitted m-th + 1 byte Read start address 23 to 16 m-th + 2 byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted m-th + 3 byte Read start address 15 to 08 m-th + 4 byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted m-th + 5 byte Read start address 07 to 00 m-th + 6 byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted m-th + 7 byte Number of bytes to read 23 to 16 m-th + 8 byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted m-th + 9 byte m-th + 10 byte Number of bytes to read 15 to 08 Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted Page 362 RA003 TMP89FM42 Table 22-9 Transfer Formats of the Flash Memory Read Command Transfer data from the external controller to TMP89FM42 Transfer byte m-th + 11 byte Number of bytes to read 07 to 00 m-th + 12 byte Baud rate Transfer data from TMP89FM42 to the external controller Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted m-th + 13 byte Baud rate after adjustment Memory data Baud rate after adjustment Memory data OK: Checksum (high) : BOOT ROM n-th - 2 byte n-th - 1 byte - Baud rate after adjustment n-th byte - Baud rate after adjustment Error: No data transmitted OK: Checksum (low) Error: No data transmitted n-th + 1 byte (Wait for the next operation command data) Baud rate after adjustment - Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to Table 22-18. Note 2: For information on checksums, refer to "22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords". Note 3: If the area 0xFFE0 through 0xFFFF is all 0xFF, password authentication is not performed and, therefore, the password string need not be transmitted. The password count storage address and password comparison start address, however, must be specified, even for a blank product. If the password count storage address and/or password comparison start address are/is incorrect, a password error occurs; the TMP89FM42 stops communication and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 4: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM42 stops communication, and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 5: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM42 stops communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 6: If the number of bytes received at the m-th + 7 byte, m-th + 9 byte or m-th + 11 byte is more than 0x000000 or the size of internal memory, the TMP89FM42 stops communication and goes into an idle state. Page 363 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.4 TMP89FM42 RAM loader command (operation command: 0x60) Table 22-10 shows the transfer formats of the RAM loader command. Table 22-10 Transfer Formats of the RAM Loader Command Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment - (Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted Error: No data transmitted 5th byte Operation command data (0x60) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0x60) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte Password count storage address 23 to 16 8th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 9th byte Password count storage address 15 to 08 10th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 11th byte Password count storage address 07 to 00 12th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted BOOT 13th byte ROM 14th byte Password comparison start address 23 to 16 Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 15th byte Password comparison start address 15 to 08 16th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 17th byte Password comparison start address 07 to 00 18th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 19th byte Password string Baud rate after adjustment - - Baud rate after adjustment OK: No data transmitted : m-th byte Error: No data transmitted m-th + XX byte Intel Hex format (binary) Baud rate after adjustment - Baud rate after adjustment OK: Checksum (high) (note 3) : n-th - 2 byte n-th - 1 byte - Baud rate after adjustment n-th byte - Baud rate after adjustment Error: No data transmitted OK: Checksum (low) (note 3) Error: No data transmitted RAM - The program jumps to the start address of RAM in which the first transferred data is written, and executes itself. Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to Table 22-18. Note 2: For information on the Intel Hex format, refer to "22.11 Intel Hex Format (Binary)". For information on checksums, refer to "22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords". Note 3: If the area 0xFFE0 through 0xFFFF is all 0xFF, password authentication is not performed and, therefore, the password string need not be transmitted. The password count storage address and password comparison start address, however, must be specified, even for a blank product. If the password count storage address and/or password comparison start address are/is incorrect, a password error occurs; the TMP89FM42 stops communication and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 4: After sending a password string, do not send the end record only. If the TMP89FM42 receives the end record after receiving a password string, it may malfunction. Page 364 RA003 TMP89FM42 Note 5: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM42 stops communication, and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 6: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM42 stops communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Page 365 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.5 TMP89FM42 Flash memory SUM output command (operation command: 0x90) Table 22-11 shows the transfer formats of the flash memory SUM output command. Table 22-11 Transfer Formats of the Flash Memory SUM Output Command Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment - (Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted Error: No data transmitted BOOT 5th byte Operation command data (0x90) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: No data transmitted (0x90) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) ROM 7th byte - Baud rate after adjustment 8th byte - Baud rate after adjustment 0x55 : 0xAA: All data are 0xFF. OK: Checksum (high) (note 2) Error: No data transmitted 9th byte - Baud rate after adjustment 10th byte (Wait for the next operation command data) Baud rate after adjustment OK: Checksum (low) (note 2) Error: No data transmitted - Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to Table 22-18. Note 2: For information on checksums, refer to "22.10 Checksum (SUM)". Note 3: If data to be included in the checksum are all 0xFF, the 7th byte becomes 0xAA. If any one piece of data to be included in the checksum is other than 0xFF, the 7th byte becomes 0x55. Page 366 RA003 TMP89FM42 22.8.6 Product ID code output command (operation command: 0xC0) Table 22-12 shows the transfer formats of the product ID code output command. Table 22-12 Transfer Formats of the Product ID Code Output Command Transfer byte Transfer data from the external controller to TMP89FM42 Transfer data from TMP89FM42 to the external controller Baud rate 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment -(Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted Error: No data transmitted 5th byte Operation command data (0xC0) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0xC0) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte Baud rate after adjustment 0x3A Start mark 8th byte Baud rate after adjustment 0x13 Number of transfer data (from 9th to 27th bytes) 9th byte Baud rate after adjustment 0x03 Length of address (3 bytes) 10th byte Baud rate after adjustment 0xFD Reserved 11th byte Baud rate after adjustment 0x00 Reserved 12th byte Baud rate after adjustment 0x00 Reserved 13th byte Baud rate after adjustment 0x00 Reserved 0x80 ROM size code 14th byte (note 2) BOOT ROM ROM block count 15th byte Baud rate after adjustment 0x01 16th byte (note 3) Baud rate after adjustment 0x00 First address of ROM (upper byte) 17th byte (note 3) Baud rate after adjustment 0x80 First address of ROM (middle byte) 0x00 First address of ROM (lower byte) 18th byte (note 3) Baud rate after adjustment (1 block) 19th byte (note 3) Baud rate after adjustment 0x00 End address of ROM (upper byte) 20th byte (note 3) Baud rate after adjustment 0xFF End address of ROM (middle byte) 21st byte (note 3) Baud rate after adjustment 0xFF End address of ROM (lower byte) 22nd byte (note 4) Baud rate after adjustment 0x00 First address of RAM (upper byte) 23rd byte (note 4) Baud rate after adjustment 0x00 First address of RAM (middle byte) 24th byte (note 4) Baud rate after adjustment 0x60 First address of RAM (lower byte) 25th byte (note 4) Baud rate after adjustment 0x00 End address of RAM (upper byte) 26th byte (note 4) Baud rate after adjustment 0x08 End address of RAM (middle byte) 27th byte (note 4) Baud rate after adjustment 0x3F End address of RAM (lower byte) 28th byte Baud rate after adjustment 0xYY YYH : Checksum of transfer data (complement of 2 of the sum total from 9th through 27th bytes) 29th byte (Wait for the next operation command data) Baud rate after adjustment - Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to Table 22-18. Note 2: The ROM size code at the 14th byte is shown in Table 22-13. Note 3: 16th through 21st bytes show the range of addresses in flash memory where data can be written. Note 4: 22nd through 27th bytes show the flash memory area and RAM area that can be used by the RAM loader. Because the range of addresses shown here does not include the work area used by BOOTROM, it is smaller than the size of a RAM built into an actual product. Page 367 RA003 22. 22.8 Serial PROM Mode Operation Commands TMP89FM42 Table 22-13 ROM Size Code (14th Byte) 7 6 5 4 ROMSIZE 3 2 1 0 "0" "0" "0" TMP89FM42 specified value (1000 0000) 00010 : 4Kbytes 00100 : 8Kbytes 01000 : 16Kbytes ROMSIZE Data on the flash memory size 10000 : 32Kbytes Read 11000 : 48Kbytes only 11110 : 60Kbytes 10001 : 96Kbytes 11111 : 124Kbytes Page 368 RA003 TMP89FM42 22.8.7 Flash memory status output command (0xC3) Table 22-14 shows the flash memory status output commands. Table 22-14 Flash Memory Status Output Commands Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment -(Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) Error: No data transmitted 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted 5th byte Operation command data (0xC3) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0xC3) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) BOOT ROM 7th byte Baud rate after adjustment 0x3A Start mark 8th byte Baud rate after adjustment 0x04 Byte count 9th byte Baud rate after adjustment 0x00 to 0x7F Status code 1 10th byte Baud rate after adjustment 0x00 Reserved 11th byte Baud rate after adjustment 0x00 Reserved 12th byte Baud rate after adjustment 0x00 Reserved 13th byte Baud rate after adjustment (complement of 2 of the sum total from 9th through 12th bytes) Baud rate after adjustment - (from 9th through 12th bytes) Checksum 14th byte (Wait for the next operation command data) Note 1: "xxH × 3" means that the device goes into an idle state after transmitting 3 bytes of xxH. Note 2: For detailed information on the status code 1, refer to "22.8.7.1 Flash memory status code". Page 369 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.7.1 TMP89FM42 Flash memory status code The flash memory status code is 7-byte data. It shows the status of the flash memory security program and that of the address from 0xFFE0 to 0xFFFF. Table 22-15 Flash Memory Status Code Data Description In the case of TMP89FM42 1st Start mark 0x3A 2nd Number of transfer data (4 bytes from 3rd through 6th bytes) 0x04 3rd Status code 4th Reserved 0x00 5th Reserved 0x00 6th Reserved 0x00 Checksum of transfer data If 3rd data is 0x01: 0xFF (complement of 2 of the sum total of 3rd through 6th bytes) If 3rd data is 0x03: 0xFD 0x00 through 0x1F (see information below) If 3rd data is 0x00: 0x00 7th If 3rd data is 0x02: 0xFE : Status code 1 7 EPFC 6 5 4 Password string judgment when the flash memory erase command is executed (status of 0xFFFA) DAFC Security program check of the on-chip debugging function (OCD) 3 2 1 0 EPFC DAFC RPENA BLANK Initial value (**** ****) 0: To skip the judgment of a password string (to judge PNSA and PCSA only) 1: To judge a password string, PNSA, and PCSA 0: To skip the security program check at the start of OCD 1: To perform the security program check at the start of OCD 0: Status in which the security program is disabled 1: Status in which the security program is enabled 0: If data in the area 0xFFE0 through 0xFFFF are all 0xFF 1: If data in the area 0xFFE0 through 0xFFFF are other than 0xFF (status of 0xFFFB) RPENA BLANK Status of the flash memory security program Status of 0xFFE0 through 0xFFFF Restrictions are placed on the execution of some operation commands, depending on the contents of the status code 1. Detailed information on this is shown in the table below. If the security program is enabled, three commands cannot be executed: the flash memory write command, RAM loader mode command, and Sector Erase command. To execute these commands, Chip Erase must be performed on flash memory before they are executed. Page 370 RA003 TMP89FM42 RPENA BLANK EPFC DAFC Flash memory erase command Flash memory overwrite command, flash memory read command, and RAM loader command Flash memory SUM output command, product ID output command, and status output command Chip erase Sector erase Flash memory security setting command 0 0 0 0 Ο Ο Ο × × 1 0 0 0 × Ο Ο × × 0 1 0 * Pass Ο Ο × Pass 1 * Pass Ο 0 * × Ο Ο × Pass 1 * × Ο Pass × Pass 1 1 Pass Pass Note:Ο : A command can be executed. Pass: A password is required to execute a command. ×: A command cannot be executed. (After a command is echoed back, the TMP89FM42 stops communication, and goes into an idle state.) Page 371 RA003 22. 22.8 Serial PROM Mode Operation Commands 22.8.8 TMP89FM42 Mask ROM emulation setting command (0xD0) Table 22-16 shows the mask ROM emulation setting command. This command is nonfunctional in the TMP89FM42. It becomes functional if used for a product with flash memory of more than 96Kbytes. Table 22-16 Command to Change the Mask ROM Emulation Setting Number of transfer bytes Transfer data from the external controller to TMP89FM42 Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment -(Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) Error: No data transmitted 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted BOOT ROM 5th byte Operation command data (0xD0) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0xD0) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte Set value 8th byte Baud rate after adjustment - Baud rate after adjustment OK: Echo back data (0xD1) Error: No data transmitted 9th byte (Wait for the next operation command data) Baud rate after adjustment - Note 1: "xxH × 3" means that the device goes into an idle state after transmitting 3 bytes of xxH. Page 372 RA003 TMP89FM42 22.8.9 Flash memory security setting command (0xFA) Table 22-17 shows the flash memory security setting command. Table 22-17 Flash Memory Security Setting Command Transfer data from the external controller to TMP89FM42 Transfer byte Baud rate Transfer data from TMP89FM42 to the external controller 1st byte Matching data 1 (0x86 or 0x30) Automatic adjustment - (Automatic baud rate adjustment) 2nd byte - Baud rate after adjustment OK: Echo back data (0x86 or 0x30) 3rd byte Matching data 2 (0x79 or 0xCF) Baud rate after adjustment - 4th byte - Baud rate after adjustment OK: Echo back data (0x79 or 0xCF) Error: No data transmitted Error: No data transmitted 5th byte Operation command data (0xFA) Baud rate after adjustment - 6th byte - Baud rate after adjustment OK: Echo back data (0xFA) Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1) 7th byte Password count storage address 23 to 16 8th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 9th byte Password count storage address 15 to 08 10th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 11th byte BOOT Password count storage address 07 to 00 12th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted ROM 13th byte Password comparison start address 23 to 16 14th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 15th byte Password comparison start address 15 to 08 16th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 17th byte Password comparison start address 07 to 00 18th byte Baud rate after adjustment - Baud rate after adjustment OK: No data transmitted Error: No data transmitted 19th byte Password string Baud rate after adjustment - - Baud rate after adjustment OK: No data transmitted : m-th byte Error: No data transmitted n-th byte - Baud rate after adjustment OK: 0xFB (note 3) Error: No data transmitted n-th + 1 byte (Wait for the next command data) Baud rate after adjustment - Note 1: "xxH × 3" means that the device goes into an idle state after transmitting 3 bytes of xxH. Note 2: For information on passwords, refer to "22.12.1 Passwords". Note 3: If the flash memory security setting command is executed for a blank product or if a password error occurs for a non-blank product, the TMP89FM42 stops communication and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 4: If a communication error occurs during the transfer of a password address or password string, the TMP89FM42 stops communication and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM42 by using the RESET pin, and restart the serial PROM mode. Note 5: If the flash memory security is not enabled, it becomes possible to read ROM data freely in parallel PROM mode. Make sure that you enable the flash memory security in mass production. Page 373 RA003 22. 22.9 Serial PROM Mode Error Code 22.9 TMP89FM42 Error Code Table 22-18 shows the error codes that the TMP89FM42 transmits when it detects errors. Table 22-18 Error Codes Data transmitted Meaning of error data 0x63, 0x63, 0x63 Operation command error 0xA1, 0xA1, 0xA1 Framing error in the received data 0xA3, 0xA3, 0xA3 Overrun error in the received data Note:If a password error occurs, the TMP89FM42 does not transmit an error code. Page 374 RA003 TMP89FM42 22.10 Checksum (SUM) For the following operation commands, a checksum is returned to verify the appropriateness of the result of command execution: - 22.10.1 Flash memory erase command (0xF0) Flash memory write command (0x30) Flash memory SUM output command (0x30) Flash memory read command (0x40) RAM loader command (0x60) Product ID code output command (0xC0) Flash memory status output command (0xC3) Calculation method The checksum (SUM) is calculated with the sum of all bytes, and the obtained result is returned as a word. The data is read in single-byte units, and the calculated result is returned as a word. Example: 0xA1 If the data to be calculated consists of four bytes as shown on the left, the checksum of the data is as follows: 0xB2 0xA1 + 0xB2 + 0xC3 + 0xD4 = 0x02EA 0xC3 SUM (HIGH)= 0x02 0xD4 SUM (LOW)= 0xEA In the case of the product ID code output command and flash memory status output command, however, a different calculation method is used. For more information, refer to Table 22-19. 22.10.2 Calculation data Table 22-19 shows the data for which a checksum is calculated for each command. Table 22-19 Data for which a Checksum Is Calculated Operation command Flash memory erase command Calculation data Description In the case of the chip erase, an entire area of the flash memory All data in the erased area of flash memory is used. When the sector erase is executed, only the erased (whole or part of flash memory) area is used to calculate the checksum. Flash memory write command Even if a part of the flash memory is written, the checksum of the entire flash memory area (0x8000 to 0xFFFF) is calculated. The data length, address, record type and checksum in Intel Hex format are not included in the checksum. Flash memory SUM output command Data in the entire area of flash memory Flash memory read command Data in the read area of flash memory RAM loader command RAM data written in the first received RAM The length of data, address, record type and checksum in Intel address through the last received RAM adHex format are not included in the checksum. dress Product ID code output command 9th through 18th bytes of transferred data For details, refer to "22.8.6 Product ID code output command (operation command: 0xC0)". Flash memory status output command 9th through 12th bytes of transferred data For details, refer to Table "Table 22-14 Flash Memory Status Output Commands". Page 375 RA003 22. Serial PROM Mode 22.11 Intel Hex Format (Binary) 22.11 TMP89FM42 Intel Hex Format (Binary) For the following two commands, the Intel Hex format is used in part of the transfer format: - Flash memory write command (0x30) RAM loader command (0x60) For information on the definition of the Intel Hex format, refer to Table 22-20. Data is in binary form. The start mark ":" must be transmitted as binary data of 0x3A. 1. After receiving the checksum of each data record, the TMP89FM42 goes into a wait state and awaits the arrival of the start mark (0x3A ":") of the next data record. Although the external controller transmits data other than 0x3A between records, the TMP89FM42 ignores such data when it is in this wait state. 2. The external controller must be provisioned so that after it transmits the checksum of end record, it goes into a wait state and does not transmit any data until the arrival of 3-byte data (overwrite detection, upper and lower bytes of the checksum). (3-byte data is used if the flash memory write command is used. If the RAM loader command is used, the external controller awaits the arrival of 2-byte data, or upper and lower bytes of the checksum.) 3. If a receiving error or Intel Hex format error occurs, the TMP89FM42 goes into an idle state without returning an error code to the external controller. The Intel Hex format error occurs in the following cases: - If the record type is other than 00h, 01h, or 02h - If a checksum error of the Intel Hex format occurs - If the data length of an extended record (record type = 0x02) is not 0x02 - If the TMP89FM42 receives the data record after receiving an extended record (record type = 0x02) whose segment address is more than 0x2000 - I the data length of the end record (record type = 0x01) is not 0x00 - If the offset address of an extended record (record type = 0x02) is not 0x0000 Table 22-20 Definition of the Intel Hex Format (1) (2) (3) (4) (5) (6) Start mark Data length Offset address Record type Data Checksum (1 byte) (2 bytes) (1 byte) (1 byte) (2) Data length Data record 3A (record type = 00) Starting byte storage address Number of data in a data field * Specified using bigendian (3) Offset address 00 Data (1 to 255 bytes) (4) Record type (5) Data Complement of 2 of the sum total of the above (2) Data length End record (3) Offset address 3A 00 00 00 01 None (record type = 01) (4) Record type Complement of 2 of the sum total of the above (2) Data length Segment address Extended record 3A 02 00 00 (record type = 02) Page 376 RA003 02 (2 bytes) (3) Offset address (4) Record type * Specified using big- (5) Segment address endian Complement of 2 of the sum total of the above TMP89FM42 22.12 Security In serial PROM mode, two security functions are provided to prohibit illegal memory access attempts by a third party: password and security program functions. 22.12.1 Passwords A password is one of the security functions, and can be used when the TMP89FM42 operates in serial PROM mode or when the on-chip debugging function (hereafter called OCD) is used. Specifically, a password can be established by using data (part of user memory) in flash memory. If a password is established, a password authentication process must be performed to execute the flash memory read command, flash memory write command, and other operation commands. In the case of the OCD, the password authentication process is required prior to the start of the OCD system. In parallel PROM mode, there are no access-related restrictions using a password. To establish the accessrelated restrictions that work in both serial and parallel PROM modes, the security program must be set to an appropriate setting. 22.12.1.1 How a password can be specified With the TMP89FM42, any piece of data in flash memory (8 or more consecutive bytes) can be specified as a password. A password thus specified is authenticated by comparing a password string transmitted by the external controller with the memory data string of MCU where the password is specified. The area where a password can be specified is 0x8000 through 0xFEFF in flash memory. 22.12.1.2 Password structure A password consists of three components: PNSA, PCSA, and a password string. Figure 22-4 shows the password structure (example of a transmitted password). ・ PNSA (password count storage address) A 3-byte address is specified in the area 0x8000 through 0xFEFF. The memory data of a specified address is the number of bytes of a password string. If the memory data is less than 0x07 or if an address is outside the specified address range, a password error occurs. The memory data specified here is defined as N. ・ PCSA (password comparison start address) A 3-byte address is specified in the area 0x8000 through 0xFEFF-N. An address thus specified is the starting address to be used to compare with a password string. If an address is outside the specified address range, a password error occurs. ・ Password string Data of 8 bytes to 255 bytes (=N) must be specified as a password string. Memory data and a password string are compared by a specified number "N" of bytes; a comparison starts at an address specified by PCSA. If there is a mismatch as a result of this comparison or if data of 3 or more consecutive bytes is specified, a password error occurs, and the TMP89FM42 goes into an idle state. In this idle state, external devices cannot communicate with the TMP89FM42. To resume communication, the TMP89FM42 must be restarted in serial PROM mode by using the reset pin. Page 377 RA003 22. Serial PROM Mode 22.12 Security TMP89FM42 MCU RXD/SI pin 0x00 0xF0 0x12 0x00 0xF1 0x07 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 PNSA Password string PCSA Flash memory 0xF012 Example: PNSA=0xF012 PCSA=0xF107 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are assumed. 0x08 0xF107 0x01 0xF108 0x02 0xF109 0x03 0xF10A 0x04 0xF10B 0x05 0xF10C 0x06 0xF10D 0x07 0xF10E 0x08 0x08 is the number of passwords. Compare 8 bytes Figure 22-4 Password Structure (Example of a Password Transmitted) Page 378 RA003 TMP89FM42 22.12.1.3 Password setting, cancellation and authentication ・ Password setting Because a password is created by using part of a user program, a special password setting routine is unnecessary. A password can be set by simply writing a program to flash memory. ・ Password cancellation To cancel a password, Chip Erase (all erase) must be performed on flash memory. A password is canceled when flash memory is all initialized to 0xFF. ・ Password authentication If there is data other than 0xFF in any one byte of data written to the address 0xFFE0 through 0xFFFF of the TMP89FM42, a product is considered a non-blank product, and password authentication is required to execute an operation command. In this password authentication process, PNSA, PCSA and a password string are used. An operation command is executed only if a password has been successfully authenticated. If a password is unsuccessfully authenticated, the TMP89FM42 goes into an idle state. If all data written to the address 0xFFE0 through 0xFFFF are 0xFF, a product is considered blank, and no password authentication is performed. To execute some special operation commands, however, PNSA and PCSA are still required (a password string is not required) even if a product is blank. In this case, the addresses defined in Table 22-21 must be selected as PNSA and PCSA. Whether a product is blank or non-blank can be confirmed by executing the status output command. The operation commands that require PNSA and PCSA (password string) for them to be executed are as follows: - 22.12.1.4 Flash memory erase command (0xF0) Flash memory write command (0x30) Flash memory read command (0x40) RAM loader command (0x60) Flash memory security setting command (0xFA) Password values and setting range A password must be set in accordance with the conditions shown in Table 22-21. If a password created without meeting these conditions is used, a password error occurs. In this case, the TMP89FM42 does not transmit data and goes into an idle state. Table 22-21 Password Values and Setting Range Password PNSA (password count storage address) Blank product (note 1) Non-blank product 0x8000 ≤ PNSA ≤ 0xFEFF 0x8000 ≤ PNSA ≤ 0xFEFF 0x8000 ≤ PCSA ≤ 0xFEFF 0x8000 ≤ PCSA ≤ 0xFF00 - N * 8≤N Not required (notes 4 and 5) Required (note 3) PCSA (password comparison start address) N (password count) Password string Note 1: *: Don’t care. Note 2: When addresses from 0xFFE0 through 0xFFFF are filled with "0xFF", the product is recognized as a blank product. Page 379 RA003 22. Serial PROM Mode 22.12 Security TMP89FM42 Note 3: The data including the same consecutive data (three or more bytes) cannot be used as a password. (A password error occurs during password authentication. The TMP89FM42 does not transmit any data and goes into an idle state.) Note 4: In flash memory writing mode or RAM loader mode, the blank product receives the Intel Hex format data immediately after receiving PCSA; it does not receive password strings. In this case, the subsequent processing is performed correctly because the TMP89FM42 keeps ignoring incoming data until the start mark (0x3A ":") in the Intel Hex format is detected, even if the external controller transmits the dummy password string. However, if the dummy password string contains "0x3A", it is detected as the start mark erroneously, and the microcontroller enters the halt mode. If this causes a problem, do not transmit the dummy password strings. Note 5: In executing the flash memory erase command, do not transmit a password string to a blank product. Page 380 RA003 TMP89FM42 22.12.2 Security program The security program can be used in parallel and serial PROM modes and for OCD. It has a special memory for protection, and a special command is required to make this protection setting. If the security program is enabled, the reading or writing of flash memory in parallel PROM mode is prohibited. In serial PROM mode, the read and write of flash memory and other operation commands cannot be used. In performing OCD, two options about system startup are provided: prohibiting the system startup by using an option code and starting the system by password authentication. 22.12.2.1 How the security program functions With the TMP89FM42, you can control the read of flash memory by writing protection-related information to a specially-designed memory. Because protection-related information is written to this specially-designed memory, no user memory resource are required. 22.12.2.2 Enabling or disabling the security program ・ Enabling the security program To enable the security program, execute the flash memory security setting command. ・ Disabling the security program To disable the security program, execute Chip Erase of the flash memory erase command. Page 381 RA003 22. Serial PROM Mode 22.12 Security TMP89FM42 22.12.3 Option codes If a specified option code is placed at a specified address inside the interrupt vector area, whether password string authentication is performed or not when executing the flash memory erase command and whether the security program is checked or not when starting OCD can be designated. - Erase password free code EPFC_OP (0xFFFA) If changes are frequently made to a program during software development, there are cases in which a password may get lost. In this case, you can cancel the password string authentication of the flash memory erase command (0xF0) by setting the erase password free code (EPFC_OP). EPFC_OP is assigned to 0xFFFA in the vector area. Allocate 0xFF to this EPFC_OP to cancel the password string of the flash memory erase command (0xF0). It is recommended that the password string authentication of the flash memory erase command (0xF0) be enabled during mass production by allocating data other than 0xFF to EPFC_OP. Only Chip Erase can cancel the password string authentication by using the flash memory erase command. If Sector Erase is executed with EPFC_OP set to 0xFF, the TMP89FM42 goes into an idle state. Commands other than the flash memory erase command cannot cancel the password string authentication. - OCD security program free code DAFC_OP (0xFFFB) With the TMP89FM42, you can enable the security program to prevent illegal access attempts by a third party. If the security program is enabled, restrictions are imposed on operation commands related to memory access, and the startup of OCD. The security program should be usually enabled at the time of shipment. If there is the possibility that the OCD may be used by keeping the contents of memory intact, it is possible to directly start the OCD by setting the OCD security program free code (DAFC_OP) and thereby skipping the security program check (the password string authentication, however, is still required). DAFC_OP is assigned to 0xFFFB in the vector area. To skip the security program check at the startup of the OCD, assign 0xFF to DAFC_OP. In this case, the security program check is not performed, and the OCD can be started by performing only the password string authentication. If DAFC_OP is not 0xFF, whether the OCD can be used or not is determined by the status of the security program. If the OCD is started with the security program enabled, the TMP89FM42 stops communication and goes into an idle state. To use the OCD when the TMP89FM42 is in this idle state, Chip Erase must be executed for flash memory by using the flash memory erase command (0xF0). If the security program is disabled, the OCD can be started by performing only the password string authentication. Table 22-22 Option Codes Symbol Function Address EPFC_OP Password string authentication when the flash memory erase command is executed 0xFFFA DAFC_OP Security program check when the OCD is started 0xFFFB 0xFF : The password string authentication is skipped (only PNSA and PCSA are authenticated). Other than 0xFF: The password string, PNSA, and PCSA are authenticated. 0xFF: The security program check is skipped. Page 382 RA003 Set value Other than 0xFF: The security program check is performed. TMP89FM42 Example :Case in which the password authentication and OCD security program authentication are disabled Vector Section romdata abs = 0xFFFA DB 0xFF ; Cancel the password string during the erase operation (EPFC_OP) DB 0xFF ; Permit access when the OCD is started (DAFC_OP) Page 383 RA003 22. Serial PROM Mode 22.12 Security TMP89FM42 22.12.4 Recommended settings Table 22-23 shows the option codes and recommended security program settings. Table 22-23 Option Codes and Recommended Security Program Settings Device status At the time of debugging during software development Serial PROM mode Parallel PROM mode EPFC_OP DAFC_OP (0xFFFA) (0xFFFB) Security Program Memory read Erase Memory read Erase 0xFF 0xFF Disable Password string required Possible Possible Possible 0xFF 0xFF In quantity production Other than 0xFF Other than 0xFF 0xFF OCD Can be used Can be used Possible Enable Impossible Impossible Possible Password string required Other than 0xFF Cannot be used Can be used Cannot be used Note 1: In parallel PROM mode, Chip Erase can be performed irrespective of the option code setting. Note 2: If the security program is not enabled in parallel PROM mode, ROM data can be read with no restrictions. Make sure that in parallel PROM mode, you always enable the security program to protect ROM data. Page 384 RA003 RA003 Figure 22-5 Flowchart Page 385 (detect all 0xFF) Transmit data (checksum of the entire area) Transmit data (checksum of the entire area) Non-blank product Execute a write OK Password check Blank product Blank check Disabled Security Program check Transmit data (0x60) Receive data =0x60 (RAM loader command) ≠ 0xCF Jump to the user program in RAM 0x55 : 0xAA: All data are 0xFF. Transmit data 0x55 : There is no error. 0xAA: There is an error. (Double writes are detected) Transmit data Calculate checksum Closed loop NG (detect double writes) Execute a write OK Password check Non-blank product Blank check Disabled Enabled Transmit data (0x90) Transmit data (0x30) Security Program check Receive data =0x90 (flash memory SUM output command) Transmit S1O data (0xCF) Receive data =0x30 (flash memory write command) Receive data Transmit UART data (0x79) = 0xCF Receive data Receive data = 0x79 Receive data Receive data Blank product ≠ 0x79 Transmit S1O data (0x30) Transmit UART data (0x86) = 0x30 Receive data S1O mode ≠ 0x86 UART mode = 0x86 Received data (product ID code) Transmit data Closed loop NG Enabled Transmit data (0xC0) Receive data =0xC0 (product ID code output command) Transmit data (0xFB) Transmit data (0xC3) (status) Transmit data DAFC-OP and EPFC-OP check Blank check Security Program check Closed loop NG = FFH = 0xFF Change FLSCR1 Receive data Transmit data (0xD0) (mask ROM emulation setting command) Receive data =D0H Transmit data (0xD1) Closed loop (erase in 4KB units) Security Program check Enabled Disabled Sector erase ≠ 0xFF EPFC-OP Closed loop < 0x20 (checksum of the erased area) Transmit data Disable Security Program (erase the entire area) Chip erase ≥ 0x20 Received data Receive data Execute an erase OK NG Non-blank product Password check Blank product Blank check ≠ 0xFF Perform password check EPFC-OP Transmit data (0xF0) Receive data =0xF0 (flash memory erase command) Not perform password check Receive data =0xC3 (status output command) Blank product Enable Security Program OK Password check Non-blank product Blank check Transmit data (0xFA) Receive data =0xFA (Security Program enable command) (checksum) Transmit data (Read data) Transmit data Receive data OK Enabled Closed loop NG Non-blank product Password check Blank product Blank check Disabled Security Program check Transmit data (0x40) Receive data =40H (flash memory read command) 22.13 Receive data Setup Start TMP89FM42 Flowchart 22. Serial PROM Mode 22.14 AC Characteristics (UART) 22.14 TMP89FM42 AC Characteristics (UART) Table 22-24 UART Timing-1 Minimum required time Symbol Clock frequency (fcgck) At fcgck = 1 MHz At fcgck = 10 MHz Time from when MCU receives 0x86 to when it echoes back CMeb1 Approx. 660 660 μs 66 μs Time from when MCU receives 0x79 to when it echoes back CMeb2 Approx. 540 540 μs 54 μs Time from when MCU receives an operation command to when it echoes back CMeb3 Approx. 300 300 μs 30 μs Time required to calculate the checksum (flash memory) CMfsm 1.5 s 149 ms Time required to calculate the checksum (RAM) CMrsm Approx. 160 160 μs 16 μs Time when MCU receives Intel Hex data to when it transmits overwrite detection data CMwr Approx. 200 200 μs 20 μs Time from when MCU receives data (number of read bytes) to when it transmits memory data CMrd Approx. 430 430 μs 43 μs Time from when MCU receives data (mask ROM emulation setting data) to when it echoes back CMem2 Approx. 420 420 μs 42 μs CMrp Approx. 1080 1.08 ms 108 μs Parameter Symbol Clock frequency (fcgck) At fcgck = 1 MHz Time required to keep MODE and RESET pins at L after power-on RSsup - 10 ms Time from when MODE and RESET pins are set to H to the acceptance of RXD RXsup - 20 ms Time from when MCU echoes back 0x86 to the acceptance of RXD CMtr1 Approx. 140 140 μs 14 μs Time from when MCU echoes back 0x79 to the acceptance of RXD CMtr2 Approx. 90 90 μs 9 μs Time from when MCU echoes back an operation command to the acceptance of RXD CMtr3 Approx. 270 270 μs 27 μs Time from when the execution of a current command is completed to the acceptance of the next operation command CMnx Approx. 1100 1.1 ms 110 μs Parameter Time required to enable the security program Approx. 1493340 (32KB) Table 22-25 UART Timing-2 Page 386 RA003 Minimum required time At fcgck = 10 MHz TMP89FM42 22.14.1 Reset timing VDD MODE RSsup RESET (0x86) RXD RXsup (0x79) (0x86) (0x79) TXD CMtr1 CMeb1 CMtr2 CMeb2 CMtr3 CMeb3 Operation command Figure 22-6 Reset Timing 22.14.2 Flash memory erase command (0xF0) PNSA PCSA Password string Area to be erased [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] RXD (0xF0) TXD CMtr3 Next command RXD [15:8] [7:0] TXD Checksum CMfsm Figure 22-7 Flash Memory Erase Command Page 387 RA003 CMnx 22. Serial PROM Mode 22.14 AC Characteristics (UART) 22.14.3 TMP89FM42 Flash memory write command (0x30) PNSA PCSA Password string [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] IntelHex (0x3A) RXD (0x30) TXD CMtr3 IntelHex(End Record) (0x00) (0x00) (0x01) (0xFF) Next command RXD [15:8] [7:0] (0x55) or (0xAA) TXD Overwrite CMwr detection CMfsm Checksum CMnx Figure 22-8 Flash Memory Write Command 22.14.4 Flash memory read command (0x40) PNSA PCSA Password string [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] Read start address [23:16] [15:8] [7:0] RXD (0x40) TXD CMtr3 Number of read bytes Next command [23:16] [15:8] [7:0] RXD [15:8] [7:0] TXD CMrd Memory data Checksum Figure 22-9 Flash Memory Read Command Page 388 RA003 CMnx TMP89FM42 22.14.5 RAM loader command (0x60) PNSA PCSA Password string [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] IntelHex (0x3A) RXD (0x60) TXD CMtr3 IntelHex(End Record) Execute RAM program (0x00) (0x00) (0x01) (0xFF) RXD [15:8] [7:0] TXD Checksum CMrsm Figure 22-10 RAM Loader Command 22.14.6 Flash memory SUM output command (0x90) Next command RXD (0x55) or (0xAA) [15:8] [7:0] (0x90) TXD FF check CMfsm Checksum CMnx Figure 22-11 Flash Memory SUM Output Command 22.14.7 Product ID code output command (0xC0) Next command RXD (0xC0) TXD Product ID code Figure 22-12 Product ID Code Output Command Page 389 RA003 CMnx 22. Serial PROM Mode 22.14 AC Characteristics (UART) 22.14.8 TMP89FM42 Flash memory status output command (0xC3) Next command RXD (0xC3) TXD Status code CMnx Figure 22-13 Flash Memory Status Output Command 22.14.9 Mask ROM emulation setting command (0xD0) Set value Next command RXD (0xD0) (0xD1) TXD CMtr3 CMem2 Echo back CMnx Figure 22-14 Mask ROM Emulation Setting Command 22.14.10 Flash memory security setting command (0xFA) PNSA PCSA Password string [23:16] [15:8] [7:0] [23:16] [15:8] [7:0] RXD (0xFA) TXD CMtr3 Next command RXD 0xFB TXD Echo back CMnx CMrp Figure 22-15 Flash Memory Security Setting Command Page 390 RA003 TMP89FM42 22.15 Revision History Rev Description Added P20 and P21 description to TXD0 and RXD0 pin. RA002 "Table 22-24 UART Timing-1", "Table 22-25 UART Timing-2" Deleted VDD and Topr condition. These condition is defined in Electrical Characteristics. RA003 "22.14.5 RAM loader command (0x60)" Revised Timing. Page 391 RA003 22. Serial PROM Mode 22.15 Revision History TMP89FM42 Page 392 RA003 TMP89FM42 23. On-chip Debug Function (OCD) The TMP89FM42 has an on-chip debug function. Using a combination of this function and the TOSHIBA on-chip debug emulator RTE870/C1, the user is able to perform software debugging in the on-board environment. This emulator can be operated from a debugger installed on a PC so that the emulation and debugging functions of an application program can be used to modify a program or for other purposes. This chapter describes the control pins needed to use the on-chip debug function and how a target system is connected to the on-chip debug function. For more detailed information on how to use the on-chip debug emulator RTE870/C1, refer to the emulator operating manual. 23.1 Features The on-chip debug function of the TMP89FM42 has the following features: ・ Debugging can be performed in much the same way as when a microcontroller packaged with the MCU is used. ・ The debugging function can be realized using two communication control pins. ・ Useful on-chip debug functions include the following: - 8 breaks function are provided (one of which can also be used as an event function). - A trace function that allows the newest two branch instructions to be stored in real time is provided. - Functions to display active memory and to overwrite active memory are provided. ・ Built-in flash memory can be erased and written. 23.2 Control Pins The on-chip debug function uses two pins for communication and four pins for power supply, reset and mode control. The pins used for the on-chip debug function are shown in Table 23-1. Ports P20 and P21 are used as communication control pins of the on-chip debug function. If the RTE870/C1 OnChip Debug Emulator is used, therefore, Ports P20 and P21 cannot be debugged as port pins or UART0 and SIO0 pins. However, because the UART0 and SIO0 functions can be assigned to other ports by using SERSEL, these communication functions can also be used during on-chip debug operation. For details, refer to the section of I/ O ports. Table 23-1 Pins Used for the On-chip Debug Function Pin name (during on-chip debugging) OCDCK Input/output Input Communication control pin (clock control) OCDIO I/O Communication control pin (data control) RESET Input Reset control pin Input Mode control pin MODE VDD 4.5 V to 5.5 V (Note 1) VSS Power supply 0V XIN XOUT I/O Input Output P20 / TXD0 / SO0 (Note 1) P21 / RXD0 / SI0 RESET Can be used for an application in a target system To be connected to an oscillator to put these pins in a state of self-oscillation Page 393 RA000 (in MCU mode) MODE Power supply Input and output ports other than P20 and P21 Pin name Function 23. 23.2 On-chip Debug Function (OCD) Control Pins TMP89FM42 Note 1: To use all on-chip debug functions, the power supply voltage must be within the range 4.5 V to 5.5 V. If it is within the range 2.2 V to 4.5 V, functional limitations occur with some of the debug functions. For more detailed information, refer to the emulator operating manual. Page 394 RA000 TMP89FM42 23.3 How to Connect the On-chip Debug Emulator to a Target System To use the on-chip debug function, the specific pins on a target system must be connected to an external debugging system. The on-chip debug emulator RTE870/C1 can be connected to a target system via an interface control cable. TOSHIBA provides a connector for this interface control cable as an accessory tool. Mounting this connector on a target system will make it easier to use the on-chip debug function. The connection between the on-chip debug emulator RTE870/C1 and a target system is shown in Figure 23-1. Level Shifter (provided power supply by target system) Control Circuit (provided power supply by bus power) VDD (Note 3) VDD OCDCK (P20) OCDIO (P21) (Note 2) Other parts TMP89FM42 RESET control (Note 1) RESET Interface control cable USB connection During on-chip debugging MODE MCU mode XIN (Note 3) XOUT VSS Target system Connectors On-chip debug emulator RTE870/C1 PC (host system) Figure 23-1 How the On-chip Debug Emulator RTE870/C1 Is Connected to a Target System Note 1: Ports P20 and P21 are used as communication control pins of the on-chip debug function. If the on-chip debug emulator RTE870/C1 is used, therefore, the port functions and the functions of UART0 and SIO0, which are also used as ports, cannot be debugged. If the emulator is disconnected to be used as a single MCU, the functions of ports P20 and P21 can be used. To use the on-chip debug function, however, P20 and P21 should be disconnected using a jumper, switch, etc. if there is the possibility of other parts affecting the communication control. Note 2: If the reset control circuit on an application board affects the control of the on-chip debug function, it must be disconnected using a jumper, switch, etc. Note 3: The power supply voltage VDD must be provided by a target system. The VDD pin is connected to the emulator so that the level of voltage appropriate for driving communication pins can be obtained by using the power supply of a target system. The connection of the VDD pin is for receiving the power supply voltage, not for supplying it from the emulator side to a target system. 23.4 Security The TMP89FM42 provides two security functions to prevent the on-chip debug function from being used through illegal memory access attempted by a third person: a password function and a Security Program function. If a password is set on the TMP89FM42, it is necessary to authenticate the password for using the on-chip debug function. By setting both a password and the Security Program on the TMP89FM42, it is possible to prohibit the use of all on-chip debug functions. Furthermore, by using the option code, the on-chip debug function only can be used even if the Security Program is enabled. However, to use the on-chip debug function in this setting, a password authentication process is required. For information on how to set a password and to enable the read protection and option code, refer to "Serial PROM Mode". Page 395 RA000 23. 23.4 On-chip Debug Function (OCD) Security TMP89FM42 Page 396 RA000 TMP89FM42 24. Input/Output Circuit 24.1 Control Pins The input/output circuitries of the TMP89FM42 control pins are shown below. Control pin I/O XIN Input XOUT Output XTIN Input XTOUT Output RESET Input Circuitry Remarks Refer to the P0 ports in the chapter of Input/Output Ports. Refer to the P0 ports in the chapter of Input/Output Ports. Refer to the P1 ports in the chapter of Input/Output Ports. R MODE Input R = 100 Ω (typ.) Page 397 RA000 24. 24.1 Input/Output Circuit Control Pins TMP89FM42 Page 398 RA000 TMP89FM42 25. Electrical Characteristics 25.1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. (VSS = 0 V) Parameter Supply voltage Input voltage Output voltage Output current (per pin) Output current (total) Symbol Pins VDD Unit V VIN1 P0, P1, P2 (excluding P23 and P24), P4, P7, P8, P9, PB (tri-state port) −0.3 to VDD + 0.3 VIN2 P23, P24 (sink open drain port) −0.3 to VDD + 0.3 VIN3 AIN0 to AIN7 (analog input voltage) −0.3 to AVDD + 0.3 VOUT1 −0.3 to VDD + 0.3 IOUT1 P0, P1, P2 (excluding P23 and P24), P4, P7, P8, P9, PB (tri-state port) −1.8 IOUT2 P0, P1, P2, P4, P9 (pull-up resistor) −0.4 IOUT3 P0, P1, P2, P4, P74 to P77, P8, P9 (tri-state port) 3.2 IOUT4 P70 to P73, PB (large current port) 30 ΣIOUT1 P0, P1, P2 (excluding P23 and P24), P4, P7, P8, P9, PB (tri-state port) −30 ΣIOUT2 P0, P1, P2, P4, P9 (pull-up resistor) −4 ΣIOUT3 P0, P1, P2, P4, P74 to P77, P8, P9 (tri-state port) 60 ΣIOUT4 P70 to P73, PB (large current port) 120 PD 250 Soldering temperature (time) Tsld 260 (10 s) Storage temperature Tstg −55 to 125 Operating temperature Topr −40 to 85 Power dissipation (Topr = 85°C) Page 399 RA005 Ratings −0.3 to 6.0 V V mA mW °C 25. Electrical Characteristics 25.2 Operating Conditions 25.2 TMP89FM42 Operating Conditions The operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the operating conditions for the device are always adhered to. 25.2.1 MCU mode (Flash Programming or erasing) (VSS = 0 V, Topr = −10 to 40°C) VIH1 MODE pin VIH2 Hysteresis input VIL1 MODE pin VIL2 Hysteresis input Min Max 4.5 5.5 fc VDD × 0.70 VDD ≥ 4.5 V VDD × 0.75 VDD ≥ 4.5 V XIN, XOUT [V] [V] 5.5 5.5 4.5 4.5 [MHz] Gear clock(fcgck) frequency range 1.0 10.0 0.25 10.0 [MHz] High-frequency clock(fc) frequency range Page 400 V VDD × 0.25 Figure 25-1 Clock gear (fcgck) and High-frequency clock (fc) RA005 VDD Unit VDD × 0.30 0 VDD ≥ 4.5 V fcgck 0.250 Clock frequency Condition NORMAL1, 2 modes 10 Input low level Pins VDD 1 Input high level Symbol 10 Parameter Supply voltage MHz TMP89FM42 25.2.2 MCU mode (Except Flash Programming or erasing) (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Min fc = 10.0 MHz 5.5 V 2.2 NORMAL1, 2 modes fcgck = 10.0 MHz 4.3 IDLE0, 1, 2 modes fcgck = 4.2 MHz VDD Unit 2.7 fc = 8.0 MHz Supply voltage Max 2.7 fcgck = 2.0 MHz SLOW1, 2 modes fs = 32.768 kHz 2.2 SLEEP0, 1 modes STOP mode Input high level VIH1 MODE pin VIH2 Hysteresis input VIH3 Input low level VDD × 0.75 VDD < 4.5 V VIL1 MODE pin VIL2 Hysteresis input VDD × 0.30 0 VDD < 4.5 V XIN, XOUT VDD VDD × 0.90 VDD ≥ 4.5 V VIL3 fc VDD × 0.70 VDD ≥ 4.5 V VDD × 0.25 VDD × 0.10 VDD = 2.2 to 5.5 V 1.0 8.0 VDD = 2.7 to 5.5 V 1.0 10.0 VDD = 2.2 to 5.5 V Clock frequency 2.0 VDD = 2.7 to 5.5 V fcgck 0.25 VDD = 4.3 to 5.5 V [V] 5.5 4.3 4.3 30.0 (a) Gear clock(fcgck) frequency range 34.0 (c) [MHz] High-frequency clock(fc) frequency range (a) fc, fc/2 or fc/4 can be used as gear clock (fcgck). (b) Only fc/2 or fc/4 can be used as gear clock (fcgck). (c) Only fc/4 can be used as gear clock (fcgck). Figure 25-2 Clock gear (fcgck) and High-frequency clock (fc) Page 401 RA005 4.2 (c) 4 4.2 [MHz] 2 (b) 1 10 4.2 2.2 2 2.7 2.2 0.250 2.7 (b) 10 [V] 5.5 MHz 10.0 VDD = 2.2 to 5.5 V XTIN, XTOUT 8 8.4 fs V kHz 25. Electrical Characteristics 25.2 Operating Conditions 25.2.3 TMP89FM42 Serial PROM mode (VSS = 0 V, Topr = −10 to 40°C) Input low voltage VDD NORMAL1, 2 modes VIH1 MODE pin VIH2 Hysteresis input VIL1 MODE pin VIL2 Hysteresis input fc Min Max 4.5 5.5 VDD × 0.70 VDD ≥ 4.5 V XIN, XOUT [V] [V] 5.5 4.5 4.5 [MHz] Gear clock(fcgck) frequency range 1.0 10.0 0.25 10.0 [MHz] High-frequency clock(fc) frequency range Page 402 V VDD × 0.25 Figure 25-3 Clock gear (fcgck) and High-frequency clock (fc) RA005 Unit VDD × 0.30 0 VDD ≥ 4.5 V 5.5 VDD VDD × 0.75 VDD ≥ 4.5 V fcgck 0.250 Clock frequency Condition 10 Input high voltage Pins 1 Supply voltage Symbol 10 Parameter MHz TMP89FM42 25.3 DC Characteristics (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Min Typ. Max Unit − 0.9 − V − − ±2 μA 100 220 500 30 50 100 VDD = 5.5 V, VOUT = 5.5 V − − 2 VDD = 5.5 V, VOUT = 5.5 V/0 V − − ±2 4.1 − − VDD = 4.5 V, IOL = 1.6 mA − − 0.4 VDD = 4.5 V, VOL = 1.0 V − 20 − VHS Hysteresis input IIN1 MODE VDD = 5.5 V IIN2 P0, P1, P2, P4, P5, P7, P8, P9, PB VIN = VMODE = 5.5 V/0 V IIN3 RESET, STOP RIN2 RESET pull-up RIN3 P0, P1, P2 (excluding P23 and P24), P4, P9 pull-up ILO1 P23, P24 (skin open drain port) ILO2 P0, P1, P2 (excluding P23 and P24), P4, P5, P7, P8, P9, PB (tristate port) Output high voltage VOH Except P23, P24, XOUT, XTOUT VDD = 4.5 V, IOH = −0.7 mA Output low voltage VOL Except XOUT, XTOUT Output low current IOL P70 to P73, PB (Large current port) Hysteresis voltage Input current Input resistance Output leakage current VDD = 5.5 V, VIN = VMODE = 0 V kΩ μA V mA Note 1: Typical values show those at Topr = 25°C and VDD = 5.0 V. Note 2: Input current IIN3 : The current through pull-up resistor is not included. Note 3: VIN : The input voltage on the pin except MODE pin, VMODE : The input voltage on the MODE pin (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition VDD = 5.5 V Supply current in NORMAL 1, 2 modes VIN = 5.3 V/0.2 V (Note 7) VMODE=5.3V/0.1V fcgck = 10.0 MHz Supply current in IDLE0, 1, 2 modes VDD = 5.5 V VIN = 5.3 V/0.2 V (Note 7) Supply current in SLOW1 mode (Notes 5 and 7) Supply current in SLEEP1 mode VMODE=5.3V/0.1V IDD (Note 8) fcgck = 8.0 MHz VDD = 3.0 V VIN = 2.8 V/0.2 V VMODE=2.8V/0.1V fs = 32.768 kHz When a program operates on flash memory − 14.5 20.0 When a program operates on RAM − 9.5 12.5 − 5.5 7.5 VIN = 5.3 V/0.2 V VMODE=5.3V/0.1V Unit mA When a program operates on flash memory − 13 − When a program operates on RAM − 8 − − 4.5 − When a program operates on flash memory − 20 39 When a program operates on RAM − 11 30 − 10 24 − 9 22 − 10 20 VDD = 5.5 V Page 403 RA005 Max fs = 32.768 kHz Supply current in SLEEP0 mode Supply current in STOP mode Typ. fs = 32.768 kHz Supply current in NORMAL 1, 2 modes Supply current in IDLE0, 1, 2 modes Min μA 25. 25.3 Electrical Characteristics DC Characteristics TMP89FM42 (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Min Typ. Max − 10 − − 2 − − 26 − Unit VDD = 5.5 V VIN = 5.3 V/0.2 V Peak current of intermittent operation VMODE=5.3V/0.1V IDDRP-P VDD = 3.0V (Notes 7 and 9) VIN = 2.8 V/0.2 V When a program operates on flash memory or when data is being read from flash memory mA VMODE=2.8V/0.1V Current for writing to flash memory, erasing and security program VDD = 5.5 V IDDEW VIN = 5.3 V/0.2 V VMODE=5.3V/0.1V (Notes 4, 8 and 9) Note 1: Typical values shown are Topr = 25°C and VDD = 5.0 V, unless otherwise specified. Note 2: IDD does not include IREF. It is the electrical current in the state in which the peripheral circuitry has been operated. Note 3: VIN : The input voltage on the pin except MODE pin, VMODE : The input voltage on the MODE pin Note 4: When performing a write or erase on the flash memory or activating a security program in the flash memory, make sure that the operating temperature Topr is within the range −10°C to 40°C. If the temperature is outside this range, the resultant performance cannot be guaranteed. Note 5: In SLOW1 mode, the difference between the peak current and the average current becomes large. Note 6: Each supply current in SLOW2 mode is equivalent to that in IDLE0, IDLE1 and IDLE2 modes. Note 7: When a program operates in the flash memory or when data is being read from the flash memory, the flash memory operates intermittently, and a peak current flows, as shown in Figure 25-4. In this case, the supply current IDD (in NORMAL1, NORMAL2 and SLOW1 modes) is defined as the sum of the average peak current and MCU current. Note 8: If a write or erase is performed on the flash memory or a security program is enabled in the flash memory, an instantaneous peak current flows, as shown in Figure 25-5. Note 9: The circuit of a power supply must be designed such as to enable the supply of a peak current. This peak current causes the supply voltage in the device to fluctuate. Connect a bypass capacitor of about 0.1 μF near the power supply of the device to stabilize its operation. 1 machine cycle Program counter (PC) n n+1 n+2 n+3 Momentary flash current I DDP-P [mA] Maximum current Typical current MCU current Figure 25-4 Intermittent Operation of Flash Memory Page 404 RA005 Sum of average momentary flash current and MCU current TMP89FM42 1 machine cycle Program counter (PC) Internal data bus Internal write signal Last write cycle of each of the Byte Program, Security Program, Chip Erase and Sector Erase TBD, TSCE I DDEW [mA] Figure 25-5 Current When an Erase or Write is Being Performed on the Flash Memory Page 405 RA005 25. 25.4 Electrical Characteristics AD Conversion Characteristics 25.4 TMP89FM42 AD Conversion Characteristics (VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C) Parameter Symbol Analog reference voltage / Power supply voltage of analog control circuit VAREF / AVDD Analog input voltage range VAIN Power supply current of analog reference voltage IREF Condition Min Typ. Max VDD V VSS − VAREF − 0.6 1.0 − − − − Full scale error (Note4) − Total error (Note4) − VDD = AVDD / VAREF = 5.5 V VSS = 0.0 V Non-linearity error (Note4) VSS = 0.0V mA 89CM42 89FM42 89CH42 89FH42 ±4 ±3 ±4 ±3 − ±4 ±3 − ±4 ±3 VDD = AVDD / VAREF = 5.0 V Zero point error (Note4) Unit LSB (VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C) Parameter Symbol Analog reference voltage / Power supply voltage of analog control circuit VAREF / AVDD Analog input voltage range VAIN Power supply current of analog reference voltage IREF Condition Min Typ. Max VDD V VSS − VAREF − 0.5 0.8 − − − − Full scale error (Note4) − Total error (Note4) − VDD = AVDD / VAREF = 4.5 V VSS = 0.0 V Non-linearity error (Note4) VSS = 0.0V mA 89CM42 89FM42 89CH42 89FH42 ±4 ±3 ±4 ±3 − ±4 ±3 − ±4 ±3 VDD = AVDD / VAREF = 2.7 V Zero point error (Note4) Unit LSB (VSS = 0.0 V, 2.2 V ≤ VDD < 2.7 V, Topr = −40 to 85°C) Parameter Symbol Analog reference voltage / Power supply voltage of analog control circuit VAREF / AVDD Analog input voltage range VAIN Power supply current of analog reference voltage IREF Condition Min Typ. Max VDD VDD = AVDD / VAREF = 2.7 V VSS = 0.0 V Non-linearity error (Note4) V VSS − VAREF − 0.3 0.5 − − VDD = AVDD / VAREF = 2.2 V, Zero point error (Note4) Unit mA 89CM42 89FM42 89CH42 89FH42 ±5 ±4 − − ±5 ±4 Full scale error (Note4) − − ±5 ±4 Total error (Note4) − − ±5 ±4 VSS = 0.0 V LSB Note 1: The total error includes all errors except a quantization error, and is defined as the maximum deviation from the ideal conversion line. Note 2: Conversion times differ with variation in the power supply voltage. Note 3: The voltage to be input to the AIN input pin must be within the range VAREF to VSS. If a voltage outside this range is input, converted values will become indeterminate, and converted values of other channels will be affected. Note 4: AD conversion characteristics differ between TMP89FM42/FH42 and TMP89CM42/CH42. Note 5: If the AD converter is not used, fix the VAREF/AVDD pin to the VDD level. Page 406 RA005 TMP89FM42 25.5 Power-on Reset Circuit Characteristics Power supply voltage (VDD) Operating voltage VPROFF VPRON tPPW t VDD tPROFF tPRON Power-on reset signal Warm-up counter start Warm-up counter clock tPWUP CPU and peripheral circuit reset signal Figure 25-6 Power-on Reset Operation Timing Note:Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluctuations in the power supply voltage (VDD). (VSS=0 V, Topr = −40 to 85°C) Min. Typ. Max. VPROFF Symbol Power-on reset releasing voltageNote 1.85 2.02 2.19 VPRON Power-on reset detecting voltageNote 1.70 1.85 2.00 tPROFF Power-on reset releasing response time − 0.01 0.1 tPRON Power-on reset detecting response time − 0.01 0.1 tPRW Power-on reset minimum pulse width 1.0 − − tPWUP Warming-up time after a reset is cleared − 102 x 2 /fc − s Power supply rise time − − 5 ms tVDD Parameter 9 Unit V ms Note 1: Because the power-on reset releasing voltage and the power-on reset detecting voltage change relative to one another, the detected voltage will never become inverted. Note 2: A clock output by an oscillating circuit is used as the input clock for a warming-up counter. Because the oscillation frequency does not stabilize until an oscillating circuit stabilizes, some errors may be included in the warming-up time. Note 3: Boost the power supply voltage such that tVDD becomes smaller that tPWUP. Page 407 RA005 25. 25.6 Electrical Characteristics Voltage Detecting Circuit Characteristics 25.6 TMP89FM42 Voltage Detecting Circuit Characteristics Power supply voltage (VDD) Operating voltage Level of detected voltage tVLTPW tVLTOFF tVLTON Signal to request the voltage detection interrupt Voltage detection reset signal Figure 25-7 Operation Timing of the Voltage Detecting Circuit Note:Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluctuations in the power supply voltage (VDD). (VSS = 0 V, Topr = −40 to 85°C) Symbol Parameter Min. Typ. Max. Voltage detection releasing response time − 0.01 0.1 Voltage detecting detection response time − 0.01 0.1 1.0 − − tVLTOFF tVLTON tVLTPW Voltage detecting minimum pulse width Page 408 RA005 Unit ms TMP89FM42 25.7 AC Characteristics 25.7.1 MCU mode (Flash programming or erasing) (VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −10 to 40°C) Parameter Symbol Condition NORMAL1, 2 modes Machine cycle time tcy IDLE0, 1, 2 modes Typ. Max 0.100 − 4 Unit μs SLOW1, 2 modes SLEEP0, 1 modes High-level clock pulse width tWCH For external clock operation (XIN input). Low-level clock pulse width tWCL fc = 10.0 MHz High-level clock pulse width tWSH For external clock operation (XTIN input) Low-level clock pulse width tWSL fs = 32.768 kHz 25.7.2 Min 117.6 − 133.3 − 50.0 − ns − 15.26 − μs MCU mode (Except Flash Programming or erasing) (VSS = 0 V, VDD = 4.3 V to 5.5 V, Topr = −40 to 85°C) Parameter Symbol Condition NORMAL1, 2 modes Machine cycle time tcy IDLE0, 1, 2 modes SLOW1, 2 modes SLEEP0, 1 modes High-level clock pulse width tWCH For external clock operation (XIN input). Low-level clock pulse width tWCL fc = 10.0 MHz High-level clock pulse width tWSH For external clock operation (XTIN input) Low-level clock pulse width tWSL fs = 32.768 kHz Page 409 RA005 Min Typ. Max Unit 0.100 − 4 117.6 − 133.3 − 50.0 − ns − 15.26 − μs μs 25. 25.7 Electrical Characteristics AC Characteristics TMP89FM42 (VSS = 0 V, VDD = 2.7 V to 4.3 V, Topr = −40 to 85°C) Parameter Symbol Condition NORMAL1, 2 modes Machine cycle time tcy IDLE0, 1, 2 modes Min Typ. Max 0.238 − 4 Unit μs SLOW1, 2 modes SLEEP0, 1 modes High-level clock pulse width tWCH For external clock operation (XIN input). Low-level clock pulse width tWCL fc = 10.0 MHz High-level clock pulse width tWSH For external clock operation (XTIN input) Low-level clock pulse width tWSL fs = 32.768 kHz 117.6 − 133.3 − 50.0 − ns − 15.26 − μs (VSS = 0 V, VDD = 2.2 V to 2.7 V, Topr = −40 to 85°C) Parameter Symbol Condition NORMAL1, 2 modes Machine cycle time tcy IDLE0, 1, 2 modes Typ. Max Unit 0.500 − 4 117.6 − 133.3 − 62.5 − ns − 15.26 − μs μs SLOW1, 2 modes SLEEP0, 1 modes High-level clock pulse width tWCH For external clock operation (XIN input). Low-level clock pulse width tWCL fc = 8.0 MHz High-level clock pulse width tWSH For external clock operation (XTIN input) Low-level clock pulse width tWSL fs = 32.768 kHz 25.7.3 Min Serial PROM mode (VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −10 to 40°C) Parameter Symbol Condition NORMAL1, 2 modes Machine cycle time tcy IDLE0, 1, 2 modes SLOW1, 2 modes SLEEP0, 1 modes High-level clock pulse width tWCH For external clock operation (XIN input). Low-level clock pulse width tWCL fc = 10.0 MHz High-level clock pulse width tWSH For external clock operation (XTIN input) Low-level clock pulse width tWSL fs = 32.768 kHz Page 410 RA005 Min Typ. Max 0.100 − 4 Unit μs 117.6 − 133.3 − 50.0 − ns − 15.26 − μs TMP89FM42 25.8 Flash Characteristics 25.8.1 Write characteristics (VSS = 0 V, Topr = −10 to 40°C) Parameter Condition Number of guaranteed writes to flash memory Flash memory write time Flash memory erase time Typ. Max Unit − − 100 Times μs − − 40 Chip erase − − 30 Sector erase − − 30 Page 411 RA005 Min ms 25. 25.9 Electrical Characteristics Oscillating Condition 25.9 TMP89FM42 Oscillating Condition XIN C1 XOUT XTIN C2 (1) High-frequency oscillation C1 XTOUT C2 (2) Low-frequency oscillation Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. Note 2: The product numbers and specifications of the resonators supplied by Murata Manufacturing Co., Ltd. are subject to change. For up to date information, please refer to the following http://www.murata.com Page 412 RA005 TMP89FM42 25.10 Handling Precaution - The solderability test conditions are shown below. 1. When using the Sn-37Pb solder bath Solder bath temperature = 230°C Dipping time = 5 seconds Number of times = once R-type flux used 2. When using the Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245°C Dipping time = 5 seconds Number of times = once R-type flux used - The pass criteron of the above test is as follows: Solderability rate until forming ≥ 95% When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. Page 413 RA005 25. Electrical Characteristics 25.11 Revision History 25.11 TMP89FM42 Revision History Rev Description The maximum value of the operation frequency is changed from 8MHz to 10MHz. RA001 Added figure for "Clock gear (fcgck) and High-frequency clock (fc)". "25.4 AD Conversion Characteristics" Fixed spec. RA002 RA003 RA004 RA005 "25.5 Power-on Reset Circuit Characteristics" Revised table (IPWUP Unit) from "ms" to "s". "25.3 DC Characteristics" Revised supply current in STOP mode. (Maximum : from 25μA to 20μA) "25.4 AD Conversion Characteristics" Revised description for AD conversion error. "25.5 Power-on Reset Circuit Characteristics" Revised spec of Power-on reset detecting voltage (VPRON). "25.3 DC Characteristics" Added Note 3. "25.10 Handling Precaution" Revised mark of lead-free. Page 414 RA005 TMP89FM42 26. Package Dimensions LQFP44-P-1010-0.80B Rev 01 Unit: mm 12.0 0.2 0.08 0.07 0.2 0.6 0.15 Page 415 RA000 0.1 0.05 1.4 0.05 0.25 0.055 0.145 0.8 1.6MAX 0.37 1.0TYP 12.0 0.2 10.0 0.2 10.0 0.2 26. Package Dimensions TMP89FM42 Page 416 RA000 RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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