TMP91C630

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C630 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. TMP91C630 CMOS 16-Bit Microcontrollers TMP91C630F 1. Outline and Features TMP91C630 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. With 2 Kbytes of boot ROM included, it allows your programs to be erased and rewritten on board. TMP91C630 comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) • • • • • Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: Four-channels (444 ns/2 bytes at 36 MHz) (2) Minimum instruction execution time: 111 ns (at 36 MHz) (3) Built-in RAM: 6 Kbytes Built-in ROM: None Built-in Boot ROM: 2 Kbytes 91C630-1 2005-11-15 TMP91C630 (4) External memory expansion • • Expandable up to 16 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus Dynamic data bus sizing (5) 8-bit timers: 6 channels • Event counter :2 channels (6) 16-bit timer/event counter: 1 channel (7) Serial bus interface: 2 channels (8) 10-bit AD converter: 8 channels (9) Watchdog timer (10) Chip Select/Wait controller: 4 blocks (11) Interrupts: 35 interrupts • • • 9 CPU interrupts: Software interrupt instruction and illegal instruction 19 internal interrupts: 7 priority levels are selectable. 7 external interrupts: 7 priority levels are selectable. (Level mode, rising edge mode and falling edge mode are selectable.) (12) Input/output ports: 53 pins (13) Standby function Three halt modes: Idle2 (programmable), Idle1, Stop (14) Operating voltage • • VCC = 2.7 V to 3.6 V (fc max = 36 MHz) 100-pin QFP: P-LQFP100-1414-0.50F (15) Package 91C630-2 2005-11-15 TMP91C630 ADTRG (AN3/PA3) AN0~AN7 (PA0~PA7) VREFH VREFL AVCC AVSS CPU (TLCS-900L1) DVCC [4] DVSS [4] BOOT 10-bit 8-channel AD converter Port A XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits AM0/AM1 RESET OSC Clock gear Port 1 Port 2 X1 X2 EMU0 EMU1 (P10~P17) D8~D15 (P20~P27) A16~A23 SR RD F PC WR PZ2 ( HWR ) PZ3 Port Z Watchdog timer (WDT) Data bus Address bus Serial I/O (channel 0) Port 5 Serial I/O (channel 1) D0~D7 A0~A7 A8~A15 TXD0 (P80) RXD0 (P81) SCLK0/ CTS0 (P82) STS0 (P83) BUSRQ (P53) BUSAK (P54) TXD1 (P84) RXD1 (P85) SCK1/ CTS1 (P86) STS1 (P87) Port 8 WAIT (P55) TA0IN/INT1 (P70) TA1OUT (P71) 8-bit timer (TMRA0) 8-bit timer (TMRA1) 6-KB RAM 8-bit timer (TMRA2) CS/WAIT controller (4-block) CS0 (P60) CS1 (P61) CS2 (P62) CS3 (P63) Interrupt controller NMI INT0 (P56) TA3OUT/INT2 (P72) 8-bit timer (TMRA3) TB0IN0 (P93) TB0IN1 (P94) TB0OUT0 (P95) TB0OUT1 (P96) INT5 (P90) TA4IN/INT3 (P73) TA5OUT (P74) INT4 (P75) 8-bit timer (TMRA4) 8-bit timer (TMRA5) Port 7 2-KB boot ROM 16-bit timer (TMRB0) Port 9 Figure 1.1 TMP91C630 Block Diagram 91C630-3 2005-11-15 TMP91C630 2. 2.1 Pin Assignment and Pin Functions The Pin Assignment and Pin Functions of the TMP91C630F are showed in Figure 2.1.1. Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C630F. Pin No. Pin Name DVCC BOOT Pin Name P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 A15 A14 A13 A12 Pin No. 64 65 66 67 68 69 70 71 72 73 74 75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 TMP91C630F 40 86 39 87 38 88 37 89 Top view 36 90 35 91 34 92 P-LQFP100-1414-0.50F 33 93 32 94 31 95 30 96 29 97 28 98 27 99 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 63 62 61 60 59 58 57 56 55 54 53 52 51 DVSS P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 D7 D6 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RD WR DVCC PZ2/ HWR DVSS PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3/ ADTRG PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 100 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 D5 D4 D3 D2 D1 D0 P96/TB0OUT1 P95/TB0OUT0 P94/TB0IN1 P93/TB0IN0 P90/INT5 P75/INT4 P74/TA5OUT P73/TA4IN/INT3 P72/TA3OUT/INT2 P71/TA1OUT P70/TA0IN/INT1 RESET AM1 X1 DVSS X2 DVCC AM0 P63/ CS3 VREFH VREFL AVSS AVCC NMI DVSS P53/ BUSRQ DVCC P54/ BUSAK P55/ WAIT P56/INT0 PZ3 P80/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 25 24 23 22 21 20 19 18 17 16 15 14 P62/ CS2 P61/ CS1 P60/ CS0 EMU1 EMU0 P87/ STS1 P86/SCLK1/ CTS1 P85/RXD1 P84/TXD1 P83/ STS0 P82/SCLK0/ CTS0 P81/RXD0 Figure 2.1.1 Pin Assignment Diagram (100-Pin LQFP) 91C630-4 2005-11-15 TMP91C630 2.2 Pin Names and Functions The names of the Input/Output pins and their functions are described below. Table 2.2.1 to Table 2.2.3 show Pin name and functions. Table 2.2.1 Pin Names and Functions (1/3) Pin Names D0 to D7 P10 to P17 D8 to D15 P20 to P27 A16 to A23 A8 to A15 A0 to A7 RD WR Number of Pins 8 8 I/O I/O I/O I/O Functions Data (lower): Bits 0 to 7 of data bus Port 1: I/O port that allows I/O to be selected at the bit level (When used to the external 8-bit bus) Data (upper): Bits 8 to15 of data bus Port 2: Output port Address: Bits 16 to 23 of address bus Address: Bits 8 to 15 of address bus Address: Bits 0 to 7 of address bus Read: Strobe signal for reading external memory Write: Strobe signal for writing data to pins D0 to D7 Port 53: I/O port (with pull-up resistor) Bus request: Signal used to request bus release (high-impedance). Port 54: I/O port (with pull-up resistor) Bus acknowledge: Signal used to acknowledge bus release (high-impedance). Port 55: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait. ((1 + N) waits mode) Port 56: I/O port (with pull-up resistor) Interrupt request pin0: Interrupt request pin with programmable level/rising edge/falling edge Port 60: Output port Chip select 0: Outputs 0 when address is within specified address area. Port 61: Output port Chip select 1: Outputs 0 when address is within specified address area. Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area. Port 63: Output port Chip select 3: Outputs 0 when address is within specified address area. Port 70: I/O port 8-bit TMRA0 input Interrupt request pin 2: Interrupt request pin with programmable level/rising edge/falling edge Port 71: I/O port 8-bit TMRA0 or 8-bit TMRA1 output Port 72: I/O port 8-bit TMRA2 or 8-bit TMRA3 output Interrupt request pin 2: Interrupt request pin with programmable level/rising edge/falling edge 8 8 8 1 1 1 1 Output Output Output Output Output Output I/O Input I/O Output P53 BUSRQ P54 BUSAK P55 WAIT 1 1 I/O Input I/O Input P56 INT0 P60 CS0 1 1 1 1 1 Output Output Output Output Output Output Output Output I/O Input Input P61 CS1 P62 CS2 P63 CS3 P70 TA0IN INT1 P71 TA1OUT P72 TA3OUT INT2 1 1 I/O Output I/O Output Input 91C630-5 2005-11-15 TMP91C630 Table 2.2.2 Pin Names and Functions (2/3) Pin Names P73 TA4IN INT3 P74 TA5OUT P75 INT4 P80 TXD0 P81 RXD0 P82 SCLK0 CTS0 Number of Pins 1 I/O I/O Input Input Port 73: I/O port 8-bit TMRA4 input Functions Interrupt request pin 3: Interrupt request pin with programmable level/rising edge/falling edge. Port 74: I/O port 8-bit TMRA4 or 8-bit TMRA5 output Port 75: I/O port Interrupt request pin 4: Interrupt request pin with programmable Port 80: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin Port 81: I/O port (with pull-up resistor) Serial receive data 0 Port 82: I/O port (with pull-up resistor) Serial clock I/O 0 Serial data send enable 0 (Clear to send) Port 83: I/O port (with pull-up resistor) Serial data request signal 0 Port 84: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin Port 85: I/O port (with pull-up resistor) Serial receive data 1 Port 86: I/O port (with pull-up resistor) Serial clock I/O 1 Serial data send enable 1 (Clear to send) Port 87: I/O port (with pull-up resistor) Serial data request signal 1 Port 90: I/O port Interrupt request pin 5: Interrupt request pin with programmable level/rising edge/falling edge Port 93: I/O port Timer B0 input 0 Port 94: I/O port Timer B0 input 1 Port 95: I/O port Timer B0 output 0 Port 96: I/O port Timer B0 output 1 Port A0 to A7: Pins used to input port. Analog input 0 to 7: Pins used to input to AD converter. AD trigger: Signal used to request AD start (PA3). Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) 1 1 1 1 1 I/O Output I/O Input I/O Output I/O Input I/O Input I/O P83 STS0 1 1 1 1 I/O I/O Output I/O Input I/O Input I/O P84 TXD1 P85 RXD1 P86 SCLK1 CTS1 P87 STS1 1 1 I/O I/O Input P90 INT5 P93 TB0IN0 P94 TB0IN1 P95 TB0OUT0 P96 TB0OUT1 PA0 to PA7 AN0 to AN7 ADTRG 1 1 1 1 8 I/O Input I/O Input I/O Output I/O Output Input Input Input PZ2 HWR 1 1 I/O Output I/O PZ3 91C630-6 2005-11-15 TMP91C630 Table 2.2.3 Pin Names and Functions (3/3) Pin Names BOOT NMI Number of Pins 1 1 2 I/O Input Input Input Functions This pin sets boot mode (with pull-up resistor) Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Operation mode: AM1 = 0 and AM0 = 1: External 16-bit bus is fixed or external 8-/16-bit buses are mixed. AM1 = 0 and AM0 = 0: External 8-bit bus is fixed. AM0 to AM1 RESET 1 1 1 1 1 2 4 4 1 1 Input Input Input I/O Reset: Initializes TMP91C630F (with pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND supply pin for AD converter Oscillator connection pins Power supply pins GND pins (0 V) VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS EMU0 EMU1 Output Output Open pin Open pin Note 1: An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using the BUSRQ and BUSAK signals. 91C630-7 2005-11-15 TMP91C630 3. Operation This section describes the basic components, functions and operation of the TMP91C630. Notes and restrictions which apply to the various items described here are outlined in section 7. Precautions and restrictions at the end of this databook. 3.1 CPU The TMP91C630 incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a description of this CPU’s operation, please refer to the section of this databook which describes the TLCS-900/L1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP91C630; these functions are not covered in the section devoted to the TLCS-900/L1 CPU. 3.1.1 Reset When resetting the TMP91C630 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to Low level at least for 10 system clocks (8.89 μs at 36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by Reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). When the reset has been accepted, the CPU performs the following: • Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC PC PC • • • ← ← ← Data in location FFFF00H Data in location FFFF01H Data in location FFFF02H Sets the stack pointer (XSP) to 100H. Sets bits of the status register (SR) to 111 (thereby setting the interrupt level mask register to level 7). Sets the bit of the status register to 1 (MAX mode). (Note: As this product does not support MIN mode, do not program a 0 to the bit.) Clears bits of the status register to 000 (thereby selecting register bank 0). • When the reset is cleared, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is cleared. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. • • Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Note: The CPU internal register (except to PC, SR and XSP) and internal RAM data do not change by resetting. 91C630-8 2005-11-15 fFPH Sampling Sampling RESET A23 to A0 0FFFF00H CS0, CS1, CS3 CS2 D0 to D15 Data-in Data-in Read Figure 3.1.1 shows the timing of a reset for the TMP91C630. Figure 3.1.1 TMP91C630 Reset Timing Example 91C630-9 (PZ2 input mode) RD (After reset released, startting 2 waits read cycle) D0 to D15 Data-in Write WR HWR Note: Pull-up (internal) High-Z TMP91C630 2005-11-15 TMP91C630 3.2 Outline of Operation Modes There are multi-chip and multi-boot modes. Which mode is selected depends on the device’s pin state after a reset. • • Multi-chip mode: The device normally operations in this mode. After a reset, the device starts executing the external memory program. Multi-boot mode: This mode is used to rewrite the external flash memory by serial transfer (UART). After a reset, internal boot program starts up, executing an on-board rewrite program. Table 3.2.1 Operation Mode Setup Table Operation Mode Multi-chip mode Multi-boot mode Mode Setup Input Pin RESET BOOT H L 91C630-10 2005-11-15 TMP91C630 3.3 Memory Map Figure 3.3.1 is a memory map of the TMP91C630. Multi-chip mode 000000H 000100H Internal I/O (4 Kbytes) 000000H 000100H Multi-boot mode Internal I/O (4 Kbytes) Direct area (n) 001000H Internal RAM (6 Kbytes) 002800H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH 001000H Internal RAM (6 Kbytes) 002800H External memory 16-Mbyte area (r32) (−r32) (r32+) (r32 + d8/16) (r32 + r8/16) (nnn) External memory FFFF00H FFFFFFH Vector table (256 bytes) FFF800H FFFEFFH FFFF00H FFFFFFH Internal boot ROM (2 Kbytes) Vector table (256 bytes) ( = Internal area) Figure 3.3.1 TMP91C630 Memory Map 91C630-11 2005-11-15 TMP91C630 3.4 Triple Clock Function and Standby Function The TMP91C630 system clock block contains (1) Clock gearing system (2) Standby controller (3) Noise reducing circuit It can be used for low-power, low-noise systems. The system clock operating mode (single clock mode) is shown in Figure 3.4.1. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode ( only oscillator operate) Instruction Interrupt Instruction Interrupt Release Reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Clock mode transition figure Figure 3.4.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc. In case of TMP91C630, fc = fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is regarded to as one state. 91C630-12 2005-11-15 TMP91C630 3.4.1 Block Diagram of System Clock SYSCR2 SYSCR0 Warming up timer (High-frequency oscillator) φT φT0 fc/16 fFPH ÷2 ÷4 fFPH fc fc/2 fc/4 fc/8 fc/16 ÷2 fSYS X1 X2 High-frequency oscillator ÷2 ÷4 ÷8 ÷16 fOSCH SYSCR1 Clock gear fSYS TMRA01 to TMRA45 φT0 Prescaler CPU ROM RAM TMRB0 Prescaler Interrupt controller WDT I/O ports SIO0, SIO1 Prescaler Figure 3.4.2 Block Diagram of System Clock 91C630-13 2005-11-15 TMP91C630 3.4.2 SYSCR0 (00E0H) SFRs 7 6 − 0 Always write 0 5 − 1 Always write 1 4 − R/W 0 Always write 0 3 − 0 Always write 0 2 − 0 Always write 0 1 PRCK1 0 00: fFPH 01: Reserved 10: fc/16 11: Reserved 0 PRCK0 0 Bit symbol Read/Write After reset Function − 1 Always write 1 Select prescaler clock 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 − 0 Always write 0 2 GEAR2 R/W 0 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 1 GEAR1 0 0 GEAR0 0 Select gear value of high frequency (fc) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function 6 − R/W 0 Always write 0 5 WUPTM1 R/W 1 Warm-up timer 00: Reserved 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 1: Drive the pin during STOP mode 01: 2 /Input frequency 10: 2 /Input frequency 11: 2 /Input frequency 16 14 8 Figure 3.4.3 SFR for System Clock 91C630-14 2005-11-15 TMP91C630 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON EMCCR1 (00E4H) Bit symbol Read/Write After reset Function 6 − R/W 0 Always write 0 5 − R/W 1 Always write 1 4 − R/W 0 Always write 0 3 − R/W 0 Always write 0 2 EXTIN R/W 0 1: External clock 1 − R/W 1 Always write 1 0 − R/W 1 Always write 1 Writing 1FH turns protections off. Writing any value except 1FH turns protection on. Figure 3.4.4 SFR for Noise-Reducing 91C630-15 2005-11-15 TMP91C630 3.4.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The initialization = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after a reset. For example, fSYS is set to 1.125 MHz when the 36 MHz oscillator is connected to the X1 and X2 pins. Clock gear controller The fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example: Changing to a high-frequency gear SYSCR1 EQU LD X: Don’t care 00E1H (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. (Changing to high-frequency clock gear) To change the clock gear, write the appropriate value to the SYSCR1 register. The value of fFPH will not change until a period of time equal to the warm-up time has elapsed from the point at which the register is written to. There is a possibility that the instruction immediately following the instruction which changes the clock gear will be executed before the new clock setting comes into effect. To ensure that this does not happen, insert a dummy instruction (to execute a Write cycle) as follows. Example: SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed. 91C630-16 2005-11-15 TMP91C630 3.4.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA45, TMRB0 and SIO0, SIO1) there is a prescaler which can divide the clock. The φT clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 register determines which clock signal is input. The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0 register determines which clock signal is input. 3.4.5 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Single drive for high-frequency oscillator (2) Protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 and EMCCR1 registers. (1) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when the external-oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation (STOP + EMCCR0) X2 pin (Setting method) When a 1 is written to the EMCCR0, the oscillator is disabled and is operated as a buffer. The X2 pin always outputs a 1. is initialized to 0 by a reset. Note: Do not write EMCCR0 = “1” when using external resonator. 91C630-17 2005-11-15 TMP91C630 (2) Protection of register contents (Purpose) An item for mistake-operation by inputted noise. To execute the program certainty which is occurred mistake-operation, the protect-register can be disabled write-operation for the specific SFR. Write-disabled SFRs 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear (only EMCCR1 can be written to.) SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Block diagram) Protect register EMCCR0 To EMCCR1 Write value other than 1FH SQ Write 1FH R Write signal SFR Write signal to the disabled SFR Write signal to the other SFR (Setting method) Writing any value other than 1FH to the EMCCR1 register turns on protection, thereby preventing the CPU from writing to the specific SFR. Writing 1FH to EMCCR1 turns off protection. The protection status is set in EMCCR0. Resetting initializes the protection status to OFF. 91C630-18 2005-11-15 TMP91C630 3.4.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register. The subsequent actions performed in each mode are as follows: a. IDLE2: The CPU only is halted. In IDLE2 mode internal I/O operations can be performed by setting the following registers. Table 3.4.1 shows the registers of setting operation during IDLE2 mode. Table 3.4.1 The Registers of Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRB0 SIO0 SIO1 AD converter WDT SFR TA01RUN TA23RUN TA45RUN TB0RUN SC0MOD1 SC1MOD1 ADMOD1 WDMOD b. c. IDLE1: Only the oscillator to operate. STOP: All internal circuits stop operating. The operation of each different HALT mode is described in Table 3.4.2. Table 3.4.2 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO AD converter WDT Interrupt controller Operational Can be selected Stopped IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.4.5 and Table 3.4.6 Maintain same state as when HALT instruction was executed. Block 91C630-19 2005-11-15 TMP91C630 (2) How to clear a HALT mode The Halt state can be cleared by a reset or by an interrupt request. The combination of the value in of the interrupt mask register and the current HALT mode determine in which ways the HALT mode may be cleared. The details associated with each type of Halt state clearance are shown in Table 3.4.3. • Clearance by interrupt request Whether or not the HALT mode is cleared and subsequent operation depends on the status of the generated interrupt. If the interrupt request level set before execution of the HALT instruction is greater than or equal to the value in the interrupt mask register, the following sequence takes place: the HALT mode is cleared, the interrupt is then processed, and the CPU then resumes execution starting from the instruction following the HALT instruction. If the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is not cleared. (If a non-maskable interrupt is generated, the Halt mode is cleared and the interrupt processed, regardless of the value in the interrupt mask register.) However, for INT0 to INT4 only, even if the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is cleared. In this case, the interrupt is not processed and the CPU resumes execution starting from the instruction following the HALT instruction. The interrupt request flag remains set to 1. • Clearance by reset Any Halt state can be cleared by a reset. When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms) must be allowed after the reset for the operation of the oscillator to stabilize. When a HALT mode is cleared by resetting, the contents of the internal RAM remain the same as they were before execution of the HALT instruction. However, all other settings are re-initialized. (Clearance by an interrupt affects neither the RAM contents nor any other settings – the state which existed before the HALT instruction was executed is retained.) 91C630-20 2005-11-15 TMP91C630 Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of halt state clearance NMI INTWD INT0 to INT4 (Note) Interrupt Enabled Interrupt Disabled (Interrupt Level) ≥ (Interrupt Mask) (Interrupt Level) < (Interrupt Mask) IDLE2 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ IDLE1 STOP ♦ × ♦ × × × × × × ♦ ♦ *1 IDLE2 − − IDLE1 STOP − − − − × *1 ○ × × × × × × ○ × × × × × × ○* 1 × × × × × × Interrupt INT5 INTTA0 to INTTA5 INTTB00, INTTB01, INTTBOF0 INTRX0, INTTX0 INTRX1, INTTX1 INTAD RESET × × × × × × Reset initializes the LSI ♦: After clearing the HALT mode, CPU starts interrupt processing. ○: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. ×: Cannot be used to clear the HALT mode. −: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The HALT mode is cleared when the warm-up time has elapsed. Note: When the HALT mode is cleared by INT0 to INT4 interrupt of the level mode in the interrupt enabled status, hold the level until starting interrupt processing. Changing level before holding level, interrupt processing is correctly started. Example: Clearing IDLE1 mode An INT0 interrupt clears the Halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (P5FC), 40H (IIMC0), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; Sets P56 to INT0. ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91C630-21 2005-11-15 TMP91C630 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2 mode Halt state by an interrupt. X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release IDLE2 mode Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator continue to operate. The system clock in the MCU stops. In the Halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (i.e. restart of operation) is synchronous with it. Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode Halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE1 mode Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C630-22 2005-11-15 TMP91C630 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. Pin status in STOP mode depends on the settings in the SYSCR2 register. Table 3.4.5 and Table 3.4.6 shows state of these pins in STOP mode. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. See the sample warm-up times in Table 3.4.4. Figure 3.4.7 illustrates the timing for clearance of the STOP mode Halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data interrupt for release STOP mode Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.4.4 Sample Warm-up Times After Clearance of STOP Mode at fOSCH = 36 MHz SYSCR2 01 (2 ) 7.1 μs 8 10 (214) 0.455 ms 11 (216) 1.820 ms 91C630-23 2005-11-15 TMP91C630 Table 3.4.5 Input Buffer state Table When the CPU is operating When When used as used as function Input pin pin *1 ON – – Port Name Input Function Name During Reset Input Buffer State In HALT mode In HALT mode (STOP) (IDLE1/2) DRVE=1 DRVE=0 When When When used When When used When used used as used as as function used as as Input as Input pin function function pin Input pin pin pin pin OFF ON – – – P10-P17 P53 (*6) P54 (*6) P55 (*6) P56 (*6) P70 P71 P72 P73 P74 P75 P80 (*6) P81 (*6) P82 (*6) P83-P84 (*6) P85 (*6) P86 (*6) P87 (*6) P90 P93 P94 P95-P96 PA0-PA2 (*7) PA3 (*7) PA4-PA7 (*7) PZ2-PZ3 (*6) BOOT (*6) D0-D7 D8-D15 BUSRQ OFF ON OFF OFF ON – – – ON *2 OFF ON OFF OFF ON OFF OFF – – OFF WAIT INT0 TA0IN INT1 – INT2 TA4IN INT3 – INT4 – RXD0 SCLK0 CTS0 OFF ON ON ON ON *3 ON – – – – ON ON ON – ON – ON – *3 ON – ON – ON – ON – ON – ON ON – ON ON – ON ON – ON OFF – – RXD1 SCLK1 CTS1 OFF ON – ON – ON – OFF – – INT5 TB0IN0 TB0IN1 – AN0-2 AN3 ADTRG ON – ON – ON – OFF – *4 OFF *5 ON *4 *2 *4 ON *4 OFF *4 ON *4 OFF *4 ON *4 AN4-7 – – – – – – NMI RESET (*6) ON – ON – ON – ON – ON AM0, AM1 X1 OFF OFF ON: The buffer is always turned on. A current flow the input buffer if the input pin is not driven. OFF: The buffer is always turned off. –: No applicable. *1: The buffer is turned on when reading external. *2: The buffer is turned off when accessing port. *3: The buffer is turned off when FC register is “0”. The buffer is turned on when FC register is “1”. *4: The buffer is always input enable. *5: The buffer is turned on when reading port. *6: Port having a pull-up resistor.(Programmable) *7: AIN input does not cause a current to flow through the buffer. 91C630-24 2005-11-15 TMP91C630 Table 3.4.6 Output Buffer state Table Output Buffer State Port Name Output Function Name When the CPU is operating During Reset When used as function pin *1 When used as Output pin – In HALT mode (IDLE1/2) When used as function pin OFF When used as Output pin – In HALT mode (STOP) DRVE=1 When used as function pin OFF When used as Output pin – DRVE=0 When used as function pin When used as Output pin – – P10-P17 P20-P27 – – – – P53 P54 P55-P56 P60 P61 P62 P63 P70 P71 P72 P73 P74 P75 P80 P81 P82 P83 P84 P85 P86 P87 P90 P93-P94 P95 P96 PZ2 PZ3 X2 D0-D7 D8-D15 A16-A23 A8-A15 A0-A7 RD WR – ON ON ON OFF OFF ON ON – ON – ON – – – BUSAK – – – – – ON – ON – ON – OFF – – CS0 CS1 CS2 CS3 ON ON ON ON OFF – TA1OUT TA3OUT – TA5OUT – TXD0 – SCLK0 STS0 – – – – ON – ON – ON – OFF – ON – ON – ON – OFF – ON – ON ON – ON ON – ON OFF – OFF TXD1 – SCLK1 STS1 – ON – ON – ON – OFF – ON – ON – ON – OFF – – – TB0OUT0 TB0OUT1 HWR ON ON ON OFF – – ON – – – *3 – *3 ON: The buffer is always turned on. A current flow the input buffer if the input pin is not driven. OFF: The buffer is always turned off. –: No applicable. *1: The buffer is turned on when writing external. *2: Port having a pull-up resistor. (Programmable) *3: The buffer output High level. 91C630-25 2005-11-15 TMP91C630 3.5 Interrupts Interrupts are controlled by the CPU interrupt mask register SR and by the built-in interrupt controller. The TMP91C630 has a total of 35 interrupts divided into the following five types: • • • Interrupts generated by CPU: 9 sources (Software interrupts, Illegal instruction interrupt) Interrupts on external pins ( NMI and INT0 to INT5): 7 sources Internal I/O interrupts: 19 sources A (fixed) individual interrupt vector number is assigned to each interrupt. One of six (variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register . If the priority level of the interrupt is higher than the value of the interrupt mask register, the CPU accepts the interrupt. The interrupt mask register value can be updated using the value of the EI instruction (EI num sets data to num). For example, specifying “EI 3” enables the maskable interrupts which priority level set in the interrupt controller is 3 or higher, and also non-maskable interrupts. Operationally, the DI instruction ( = 7) is identical to the EI 7 instruction. DI instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 1 to 6. The EI instruction is vaild immediately after execution. In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes) automatically in micro DMA mode, therefore this mode is used for speed-up interrupt processing, such as transferring data to the internal or external peripheral I/O. Moreover, TMP91C630 has software start function for micro DMA processing request by the software not by the hardware interrupt. Figure 3.5.1 shows the overall interrupt processing flow. 91C630-26 2005-11-15 TMP91C630 Interrupt processing Interrupt specified by micro DMA start vector? No Yes Micro DMA Soft start request Clear interrupt requenst flag Interrupt vector calue “V” read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA Count ← Count − 1 PUSH PC PUSH SR SR ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA transfer and interrupt (INTTC0 to INTTC3) PC ← (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST ← INTNEST − 1 End Figure 3.5.1 Interrupt and Micro DMA Processing Sequence 91C630-27 2005-11-15 TMP91C630 3.5.1 General-Purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: the smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1(+1) to the interrupt mask register . However, if the priority level of the accepted interrupt is 7, the register’s value is set to 7. (4) The CPU increases the interrupt nesting counter INTNEST by 1(+1). (5) The CPU jumps to the address indicated by the data at address “FFFF00H + interrupt vector” and starts the interrupt processing routine. The above processing time is 18-states (1.0 μs at 36 MHz) as the best case (16 bits data-bus width and 0-wait). When the CPU compled the interrupt processing, use the RETI instruction to return to the main routine. RETI restores the contents of program counter (PC) and status register (SR) from the stack and decreases the interrupt nesting counter INTNEST by 1(−1). Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request which has a priority level equal to or greater than the value of the CPU interrupt mask register comes out, the CPU accepts its interrupt. Then, the CPU interrupt mask register is set to the value of the priority level for the accepted interrupt plus 1(+1). Therefore, if an interrupt is generated with a higher level than the current interrupt during its processing, the CPU accepts the later interrupt and goes to the nesting status of interrupt processing. Moreover, if the CPU receives another interrupt request while performing the said (1) to (5) processing steps of the current interrupt, the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine. Specifying DI as the start instruction disables maskable interrupt nesting. A reset initializes the interrupt mask register to 111, disabling all maskable interrupts. Table 3.5.1 shows the TMP91C630 interrupt vectors and micro DMA start vectors. The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector area. 91C630-28 2005-11-15 TMP91C630 Table 3.5.1 TMP91C630 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 − 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 − to − (Reserved) Maskable Non-mask able Type Interrupt Source or Source of Micro DMA Vector Value Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction NMI : NMI pin input Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H − FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48F FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H to FFFFFCH Micro DMA Start Vector − − − − − − − − − − − 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH − to − 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H − 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H to 00FCH INTWD: Watchdog timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input INT5: INT5 pin input (Reserved) (Reserved) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 (Reserved) (Reserved) INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) (Reserved) (Reserved) INTTBOF0: 16-bit timer 0 (overflow) (Reserved) INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial transmission (Channel 1) (Reserved) (Reserved) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) 91C630-29 2005-11-15 TMP91C630 3.5.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C630 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. Micro. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a stand-by mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored (pending) and DMA transfer is started after release HALT. (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source’s level. The micro DMA is ignored on = “7” The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of interrupts at any one time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. The data are automatically transferred once(1/2/4 bytes) from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decreased by 1(−1). If the decreased result is 0, the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA start vector register DMAnV is cleared to 0, the next micro DMA is disabled and micro DMA processing completes. If the decreased result is other than 0, the micro DMA processing completes if it isn’t specified the say later burst mode. In this case, the micro DMA transfer end interrupt (INTTC0 to INTTC3) aren’t generated. If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. Therefore, if only using the interrupt for starting the micro DMA (not using the interrupts as a general-purpose interrupt: level 1 to 6), first set the interrupts level to 0 (interrupt requests disabled). If using micro DMA and general-purpose interrupts together, first set the level of the interrupt used to start micro DMA processing lower than all the other interrupt levels. (Note) In this case, the cause of general interrupt is limited to the edge interrupt. The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined by the interrupt level and the default priority as the same as the other maskable interrupt. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA start vector” (in the Figure 3.5.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91C630-30 2005-11-15 TMP91C630 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (high) > channel 3 (low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (the upper eight bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one-word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see (4) Transfer Mode Register. As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 23 interrupts shown in the micro DMA start vectors of Figure 3.5.1 and by the micro DMA soft start, making a total of 24 interrupts. Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for Counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer source/transfer destination addresses both even-numberd values). 1 state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD Trasfer source address Trasger destination address WR / HWR D0 to D15 Input Output Figure 3.5.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (the address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91C630-31 2005-11-15 TMP91C630 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C630 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each bit, micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to 0. Only one-channel can be set for micro DMA once. (Do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read 1, micro aDMA transfer isn’t started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn’t change. Don’t use Read modify write instruction to avoid writing to other bits by mistake. Symbol Name DMA software request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 R/W 1 DMAR1 0 0 DMAR0 0 DMAR DMA request (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. Data setting for these registers is done by an “LDC cr, r” instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0: only use LSB 24 bits DMA destination address register 0: only use LSB 24 bits DMA counter register 0: 1 to 65536 DMA mode register 0 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3 DMA destination address register 3 DMA counter register 3 DMA mode register 3 91C630-32 2005-11-15 TMP91C630 (4) Detailed description of the transfer mode register 8 bits DMAM0 to 0 DMAM3 0 0 Mode Note: When setting a value in this register, clear 0 to the upper 3 bits. Minimum Number of Execution Time Execution States at fc = 36 MHz 8 states 444 ns Number of Transfer Bytes 000 (fixed) 000 00 Byte transfer Mode Description Transfer destination address INC mode ････････ I/O to memory (DMADn+) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode ････････ I/O to memory (DMADn−) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode ････････ Memory to I/O (DMADn) ← (DMASn+) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode ････････ Memory to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ････････ I/O to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444ns 12 states 667 ns 8 states 444ns 12 states 667 ns 8 states 444 ns 12 states 667 ns Counter mode ･･････ For counting number of times interrupt is generated DMASn ← DMASn + 1 DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. 5 states 278 ns Note 1: “n” is the corresponding micro DMA channels 0 to 3 DMADn +/DMASn+: Post-increment (increment register value after transfer) DMADn −/DMASn−: Post-decrement (decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (both translation and destination address area)/0 waits/ fc = 36 MHz/selected high frequency mode (fc × 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91C630-33 2005-11-15 TMP91C630 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 26 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: • • • • • when reset occurs when the CPU reads the channel vector after accepted its interrupt when executing an instruction that clears the interrupt (write DMA start vector to INTCLR register) when the CPU receives a micro DMA request (when micro DMA is set) when the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and Watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value in the Status register by the interrupt request signal with the priority value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1(+1) in the CPU SR . Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR. The interrupt controller also has registers (4 channels) used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (see Table 3.5.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter register (e.g. DMAS and DMAD) prior to the micro DMA processing. 91C630-34 2005-11-15 Interrupt controller Interrupt request F/F S R V = 20H V = 24H Priority encoder IFF2:0 3 3 INTRQ2 to 0 3 1 7 6 6 Interrupt request signal to CPU A B Interrupt level detect EI 1 to 7 DI Interrupt request signal Interrupt mask F/F RESET Q 1 CPU NMI RESET interrupt vector read INTWD Priority setting register Dn Dn + 1 D Q CLR Interrupt request F/F Q Interrupt request flag 26 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 4CH Interrupt vector generator Interrupt vector read D2 D3 D4 D5 D6 D7 D0 D1 Dn + 3 S R Interrupt vector read Micro DMA acknowledge Dn + 2 Decoder Y1 Y2 Y3 Y4 C Y5 Y6 if INTRQ2 to 0 ≥ IFF 2 to 0 then 1. INT0 Reset 1 2 Highest A B 3 priority interrupt C 4 level select 5 6 7 INT1 INT2 INT3 INT4 INT5 INTTA0 During IDLE1 During STOP Figure 3.5.3 Block Diagram of Interrupt Controller 91C630-35 V = 9CH V = A0H V = A4H V = A8H V = ACH 4-input OR Soft start 34 D Q CLR 6 INTTC S Selector 0 1 2 3 Micro DMA channel priority dncoder DMA0V DMA1V DMA2V DMA3V A B 2 4 HALT release RESET INT0, 1, 2, 3, 4 NMI Micro DMA request if IFF = 7 then 0 Micro DMA counter 0 interrupt INTAD INTTC0 INTTC1 INTTC2 INTTC3 Micro DMA start vector setting register D5 D4 D3 D2 D1 D0 RESET 2 Micro DMA channel specification TMP91C630 2005-11-15 TMP91C630 (1) Interrupt priority setting registers Symbol Name Address 7 IADC R 0 INT1 & INT2 enable I2C R 0 INT3 & INT4 enable I4C R 0 INT5 enable – – 0 – INTE5 93H – – – Always write “0” INTTA0 & INTETA01 INTTA1 enable INTTA2 & INTETA23 INTTA3 enable 96H 95H INTTA1 (TMRA1) ITA1C R 0 ITA3C R 0 INTTA4 & INTETA45 INTTA5 enable 97H ITA5C R 0 0 0 ITA5M2 0 ITA3M2 ITA1M2 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 0 0 ITA5M0 INTTA5 (TMRA5) ITA4C R 0 0 0 ITA3M0 INTTA3 (TMRA3) ITA2C R 0 0 ITA4M2 ITA1M0 ITA0C R 0 0 ITA2M2 – I5C R 0 0 ITA0M2 I5M2 0 INT4 INTE34 92H I4M2 I4M1 R/W 0 0 I4M0 I3C R 0 0 INT5 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 0 0 ITA4M0 INTTA4 (TMRA4) 0 ITA2M0 INTTA2 (TMRA2) 0 ITA0M0 INTTA0 (TMRA0) I5M0 I3M2 0 INT2 INTE12 91H I2M2 I2M1 R/W 0 0 I2M0 I1C R 0 0 INT3 I3M1 R/W 0 0 I3M0 I1M2 6 INTAD IADM2 5 IADM1 R/W 0 4 IADM0 0 3 I0C R 0 2 INT0 I0M2 0 INT1 1 I0M1 R/W 0 I1M1 R/W 0 0 I0M0 0 I1M0 0 INT0 & INTE0AD INTAD enable 90H lxxM2 0 0 0 0 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 1 1 1 1 91C630-36 2005-11-15 TMP91C630 Symbol Name Address 7 ITB01C 6 ITB01M2 5 ITB01M1 4 ITB01M0 3 ITB00C 2 ITB00M2 1 ITB00M1 0 ITB00M0 INTTB01 (TMRB0) INTTB00 & INTETB0 INTTB01 enable 99H R 0 INTTBOF0 INTETBOV enable (over flow) – – INTTX0 INTES0 INTTX0 & INTRX0 enable 9CH ITX0C R 0 INTTX1 & INTRX1 enable INTTC0 INTETC01 & INTTC1 enable INTTC2 INTETC23 & INTTC3 enable A1H ITC3C R 0 0 A0H ITC1C R 0 0 INTTC3 ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 ITX1C R 0 0 INTTC1 ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 0 INTTX1 INTES1 9DH ITX1M2 ITX1M1 R/W 0 0 ITX1M0 IRX1C R 0 ITX0M2 ITX0M1 R/W 0 0 ITX0M0 IRX0C R 0 0 – 9BH – – – Always write “0” – ITF0C R 0 R/W 0 0 R 0 INTTB00 (TMRB0) R/W 0 ITF0M2 0 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 ITC2M1 R/W 0 0 ITC2M0 ITC0M1 R/W 0 0 ITC0M0 IRX1M1 R/W 0 0 IRX1M0 IRX0M1 R/W 0 0 IRX0M0 0 ITF0M1 R/W 0 0 0 ITF0M0 INTTBOF0 (over flow) lxxM2 0 0 0 0 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 1 1 1 1 91C630-37 2005-11-15 TMP91C630 (2) External interrupt control Symbol Name Address 7 − Interrupt input mode control 0 0 8CH (Prohibit Always RMW) write 0 6 I2EDGE 0 0: Rising 1: Falling 5 I2LE 0 0: Edge 1: Level 4 I1DGE W 0 0: Rising 1: Falling 3 I1LE 0 0: Edge 1: Level 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE 0 0: Edge 1: Level 0 NMIREE 0 1: Operates even on rising + falling edge of NMI IIMC0 INT2EDGE INT2EDGE INT1EDGE INT1EDGE INT0EDGE INT0 INT2 Level Enable 0 1 0 1 0 1 0 1 Edge detect INT H Level INT Edge detect INT H Level INT Edge detect INT H Level INT INT request generation at falling edge INT request generation at rising/falling edge INT1 Level Enable INT0 Level Enable NMI Rising Edge Enable Symbol Name Interrupt input mode control1 Address 7 − W 6 I5EDGE 0 INT5EDGE INT5 0: Rising 1: Falling 5 I5LE 0 0: Edge 1: Level 4 I4EDGE W 0 INT4EDGE INT4 0: Rising 1: Falling 3 I4LE 0 0: Edge 1: Level 2 I3EDGE 0 INT3EDGE INT3 0: Rising 1: Falling 1 I3LE 0 0: Edge 1: Level 0 IIMC1 8DH 0 (Prohibit Always RMW) write 0 INT5 Level Enable 0 1 0 1 0 1 Edge detect INT H Level INT Edge detect INT H Level INT Edge detect INT H Level INT INT4 Level Enable INT3 Level Enable Note: When switching IIMC0 and 1 registers, first every FC registers in port which built-in INT function clear to 0. 91C630-38 2005-11-15 TMP91C630 Setting functions on external interrupt pins Interrupt Pin Mode NMI Falling edge Both falling and Rising edges Rising edge INT0 Falling edge High level Low level Rising edge INT1 Falling edge High level Low level Rising edge INT2 Falling edge High level Low level Rising edge INT3 Falling edge High level Low level Rising edge INT4 Falling edge High level Low level Rising edge INT5 Falling edge High level Low level Setting Method = 0 = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.5.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH Symbol Name Address Interrupt clear control Clears interrupt request flag INT0. 6 5 CLRV5 7 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR 88H 0 Interrupt vector 91C630-39 2005-11-15 TMP91C630 (4) Micro DMA start vector registers These registers assign micro DMA processing to sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel’s micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) Symbol Name DMA0 start vector Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 3 DMA0V3 0 DMA1V3 0 DMA2V3 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA0V0 0 DMA1V0 0 DMA2V0 DMA0V 80H 0 DMA1V5 DMA0 start vector DMA1 start vector R/W 0 DMA2V5 DMA2V DMA2 start vector 82H 0 DMA3V5 DMA3V DMA3 start vector 83H 0 0 0 0 DMA3V4 0 DMA3V3 DMA1 start vector R/W 0 DMA3V2 0 DMA3V1 0 DMA3V0 DMA2 start vector DMA1V 81H R/W 0 0 0 DMA3 start vector 91C630-40 2005-11-15 TMP91C630 (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name DMA software request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 DMAR 1: DMA software request DMAB DMA burst register 8AH 0 1: DMA request on burst mode 91C630-41 2005-11-15 TMP91C630 (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interurpt vector address FFFF08H. To avoid the above problem, place instruction that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1 instructions (e.g., “NOP” × 1 times). If placed EI instruction without waiting NOP instruction after execution of cleareing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, take care as the following 2 circuits are exceptional and demand special attention. INT0 to 5 level mode In Level mode INT0 is not an edge-triggered interrupt. Hence, in Level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from Edge mode to Level mode, the interrupt request flag is cleared automatically. (For example: in case of INT0) If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to Level mode so as to release a HALT state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the HALT state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the HALT state has been released.) When the mode changes from Level mode to Edge mode, interrupt request flags which were set in Level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC0), 00H; Switches interrupt input mode from Level mode to Edge mode. LD (INTCLR), 0AH; Clears interrupt request flag. NOP EI INTRX The interrupt request flip-flop can only be cleared by a Reset or by reading the Serial channel receive buffer. It cannot be cleared by an writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0 to 5: Instructions which switch to Level mode after an interrupt request has been generated in Edge mode. The pin input changes from High to Low after an interrupt request has been generated in Level mode (H → L). INTRX: Instructions which read the Receive buffer 91C630-42 2005-11-15 TMP91C630 3.6 Port Functions The TMP91C630 features 53-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin. Table 3.6.2 lists I/O registers and their specifications. Table 3.6.1 Port Functions (R: ↑ = with programmable pull-up resistor) Direction Setting Unit Bit (Fixed) Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Port Name Port 1 Port 2 Port 5 Pin Name P10 to P17 P20 to P27 P53 P54 P55 P56 Number of Pins 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 Direction I/O Output I/O I/O I/O I/O Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O R − − ↑ ↑ ↑ ↑ − − − − − − − − − − ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ − − − − − − ↑ ↑ Pin Name for Internal Function D8 to D15 A16 to A23 BUSRQ BUSAK WAIT INT0 CS0 CS1 CS2 CS3 Port 6 P60 P61 P62 P63 Port 7 P70 P71 P72 P73 P74 P75 TA0IN/INT1 TA1OUT TA3OUT/INT2 TA4IN/INT3 TA5OUT INT4 TXD0 RXD0 SCLK0/ CTS0 STS0 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 TXD1 RXD1 SCLK1/ CTS1 STS1 Port 9 P90 P93 P94 P95 P96 INT5 TB0IN0 TB0IN1 TB0OUT0 TB0OUT1 AN0 to AN7, ADTRG (PA3) HWR Port A Port Z PA0 to 7 PZ2 PZ3 91C630-43 2005-11-15 TMP91C630 Table 3.6.2 (a) I/O Registers and Their Specifications Port Port 1 X: Don’t care I/O Registers PnCR 0 1 1 None 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 None 1 1 1 0 1 0 0 1 1 0 0 0 1 0 0 0 None 1 1 1 1 None 1 1 1 None 0 0 0 1 1 0 0 0 1 None Name P10 to P17 Input port Output port D8 to D15 bus Specification Pn × × × × × 0 1 × × 0 1 × 0 1 × 0 1 0 1 × × 0 1 × 0 1 × × × × × × × × × × × × × × × × × PnFC 0 0 1 0 1 0 0 0 1 Port 2 Port Z P20 to P27 PZ2 Output port A16 to A23 output Input port (without PU) Input port (with PU) Output port HWR output PZ3 Input port (without PU) Input port (with PU) Output port Port 5 P53 Input port (without PU) Input port (with PU) Output port BUSRQ Input (without PU) BUSRQ Input (with PU) P54 Input port (without PU) Input port (with PU) Output port BUSAK output P55 Input port/WAIT input (without PU) Input port/WAIT input (with PU) Output port P56 Input port/INT0 input (without PU) Input port/INT0 input (with PU) Output port Port 6 P60 to P63 P60 P61 P62 P63 Output port CS0 output CS1 output CS2 output CS3 output Port 7 P70 to P75 P70 P71 P72 P73 P74 P75 Input port Output port TA0IN input INT1 input TA1OUT output TA3OUT output INT2 input TA4IN input INT3 input TA5OUT output INT4 input 91C630-44 2005-11-15 TMP91C630 Table 3.6.2 (b) I/O Registers and Their Specifications Port Port 8 P80 X: Don’t care I/O Registers PnCR 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 None 1 1 None 0 0 0 1 0 0 0 1 0 0 1 None 0 0 0 1 0 0 0 1 0 0 0 1 None Name Specification Input port (without PU) Input port (with PU) Output port TXD0 output (Note1) Pn 0 1 × × 0 1 × 0 1 × × 0 1 × × 0 1 × × 0 1 × 0 1 × × 0 1 × × × × × × × × × × × × × × PnFC 0 0 0 1 P81 Input port/RXD0 input (without PU) Input port/RXD0 input (with PU) Output port P82 Input port/SCLK0/CTS0 input (without PU) Input port/SCLK0/CTS0 input (with PU) Output port SCLK0 output P83 Input port (without PU) Input port (with PU) Output port STS0 output P84 Input port (without PU) Input port (with PU) Output port TXD1 output (Note1) P85 Input port/RXD1 input (without PU) Input port/RXD1 input (with PU) Output port P86 Input port/SCLK1/CTS1 input (without PU) Input port/SCLK1/CTS1 input (with PU) Output port SCLK1 output P87 Input port (without PU) Input port (with PU) Output port STS1 output Port 9 P90 Input port Output port INT5 input P93 to P96 P93 P94 P95 P96 Port A PA0 to PA7 PA3 Input port Output port TB0IN0 input TB0IN1 input TB0OUT0 output TB0OUT1 output Input port AN0 to AN7 (Note 2) ADTRG input (Note 3) Note 1: If P80 and P84 are used as open-drain output port, they are need to set registers ODE. Note 2: When PA0 to PA7 are used as AD converter input channels, a 3-bit field in the AD mode control register ADMOD1 is used to select the channel. Note 3: When PA3 is used as the ADTRG input, ADMOD1 is used to enable external trigger input. 91C630-45 2005-11-15 TMP91C630 After a Reset the port pins listed below function as general-purpose I/O port pins. A Reset sets I/O pins which can be programmed for either input or output to be input port pins. Setting the port pins for internal function use must be done in software. Note about bus release and programmable pull-up I/O port pins When the bus is released (i.e. when BUSAK = 0), the output buffers for D0 to D15, A0 to A23, and the control signals ( RD , WR , HWR and CS0 to CS3 ) are off and are set to High-impedance. However, the output of built-in programmable pull-up resistors are kept before the bus is released. These programmable pull-up resistors can be selected ON/OFF by programmable when they are used as the input ports. When they are used as output ports, they cannot be turned ON/OFF in software. Table 3.6.3 shows the pin states after the bus has been released. Table 3.6.3 Pin States (after Bus Release) Pin Names D0 to D7 P10 to P17 (D8 to D15) A0 to A15 P20 to P27 (A16 to 23) RD WR Pin State (after Bus Release) Used as port Unchanged (i.e. not set to High-impedance (High-Z)) Used for function High-Impedance (High-Z) ↑ First all bits are set High, then they are set to High-Impedance (High-Z). Unchanged (i.e. not set to High-impedance (High-Z)) ↑ ↑ ↑ ↑ The output buffer is set to OFF. The programmable pull-up resistor is set to ON irrespective of the output latch. PZ2 ( HWR ) P60 ( CS0 ) P61 ( CS1 ) P62 ( CS2 ) P63 ( CS3 ) ↑ ↑ 91C630-46 2005-11-15 TMP91C630 Figure 3.6.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate. As a result, the watchdog timer also continues to run. Therefore, the bus release time must be taken into account and care must be taken when setting the detection time for the WDT. RD WR PZ2 ( HWR ) System control bus P60 ( CS0 ) P61 ( CS1 ) P62 ( CS2 ) P63 ( CS3 ) P20 (A16) to P27 (A23) Address bus (A23 to A16) Figure 3.6.1 Interface Circuit Example (Using Bus Release Function) The above circuit is necessary to set the signal level when the bus is released. A reset sets ( RD ) and ( WR ), P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 ), P63 ( CS3 ) to output, and PZ2 ( HWR ) and P54 ( BUSAK ) to input with pull-up resistor. 91C630-47 2005-11-15 TMP91C630 3.6.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting, the control register P1CR to 0 and sets Port 1 to input mode. In addition to functioning as a general-purpose I/O port, Port 1 can also function as an address data bus (D8 to 15). In case of AM1 = 0, and AM = 1 (outside 16-bit data bus), port 1 always functions as the data bus (D8 to D15) irrespective of the setting in P1CR control register. Reset Direction control (on bit basis) P1CR write Output latch Internal data bus Output buffer P1 write Port 1 P10 to P17 (D8 to D15) P1 read Figure 3.6.2 Port 1 7 P1 (0001H) Read/Write After reset Bit symbol P17 6 P16 Port 1 Register 5 4 P15 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (output latch register is cleared to 0.) 7 Bit symbol P1CR (0004H) Read/Write After reset Function P17C 0 6 P16C 0 Port 1 Control Register 5 4 P15C 0 P14C W 0 0: In 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 1: Out Note: Read-modify-write is prohibited for P1CR. Port 1 I/O Setting 0 Input 1 Output Figure 3.6.3 Register for Port 1 91C630-48 2005-11-15 TMP91C630 3.6.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, Port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets Port 2 to address bus. Reset S Function control (on bits basis) Internal data bus P2FC write S latch B P2 write Selector Output A Output buffer Port 2 P20 to P27 (A16 to A23) P2 read Internal A16 to A23 Figure 3.6.4 Port 2 Port 2 Register 5 4 P25 1 P24 R/W 1 1 1 1 1 1 1 7 Bit symbol P2 (0006H) Read/Write After reset P27 6 P26 3 P23 2 P22 1 P21 0 P20 7 Bit symbol P2FC (0009H) Read/Write After reset Function Note: P27F 1 6 P26F 1 Port 2 Function Register 5 4 3 P25F 1 0: Port P24F W 1 1 P23F 2 P22F 1 1 P21F 1 0 P20F 1 1: Address bus (A23 to A16) Read-modify-write is prohibited for P2FC. Figure 3.6.5 Register for Port 2 91C630-49 2005-11-15 TMP91C630 3.6.3 Port 5 (P53 to P56) Port 5 is an 4-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and the function register P5FC to 0 and sets P52 to P56 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port, Port 5 also functions as I/O for the CPU’s control/status signal. Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Output Latch P5 write P-channel (Programmable pull-up) P53 ( BUSRQ ) P5 read Internal BUSRQ Figure 3.6.6 Port 53 91C630-50 2005-11-15 TMP91C630 Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Selector P-channel (Programmable pull-up) P54 ( BUSAK ) Output buffer S Output latch P5 write A B BUSAK P5 read Figure 3.6.7 Port 54 Reset Direction control (on bit basis) P5CR write Internal data bus P-channel (Programmable pull-up) P55 ( WAIT ) Output buffer S Output latch P5 write P5 read Internal WAIT Figure 3.6.8 Port 55 91C630-51 2005-11-15 TMP91C630 Reset Direction control (on bit basis) P5CR write Internal data bus Function control (on bit basis) P5FC write S Output latch P5 write Output buffer S P5 write B P-channel (Programmable pull-up) P56 (INT0) Selector A Level or edge & rising edge or falling edge IIMC0 INT0 Figure 3.6.9 Port 56 91C630-52 2005-11-15 TMP91C630 Port 5 Register 5 4 P55 R/W Data from external port (Output latch register is set to 1) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON P54 7 Bit symbol Read/Write P5 (000DH) After reset Function 6 P56 3 P53 2 1 0 7 P5CR (0010H) Read/Write After reset Function Bit symbol 6 P56C 0 Port 5 Control Register 5 4 P55C W 0 0: In 0 1: Out P54C 3 P53C 0 2 1 0 I/O Setting 0 Input 1 Output 7 Bit symbol P5FC (0011H) Read/Write After reset Function 6 P56F W 0 0: Port 1: INT0 input Port 5 Function Register 5 4 3 P54F W 0 0: Port 1: BUSAK 0 0: Port 1: BUSRQ P53F 2 1 0 Note 1: Read-modify-write are prohibited for registers P5CR and P5FC. Note 2: When port 5 is used in the input mode, P5 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When P55 pin is used as a WAIT pin, clear P5CR to 0 and Chip select/WAIT control register to 010. Figure 3.6.10 Register for Port 5 91C630-53 2005-11-15 TMP91C630 3.6.4 Port 6 (P60 to P63) Port 6 is a 4-bit output port. When reset, the P62 output latch is cleared to 0 while the P60 to P63 output latches are set to 1. In addition to functioning as an output port, this port can output standard chip select signals ( CS0 to CS3 ). These settings are made by using the P6FC register. When reset, the P6FC register has all of its bits cleared to 0, so that the port is set for output mode. Reset Internal data bus Funtion control (on bit basis) P6FC write S S Output lacth P6 write A B Selector Output buffer P60 ( CS0 ), P61 ( CS1 ), P63 ( CS3 ) P6 read CS0 , CS1 , CS3 Figure 3.6.11 Port 60, 61 and 63 Reset Function control Internal data bus (on bit basis) P6FC write S Selector R Output latch P6 write CS2 A B P62 ( CS2 ) Output buffer P6 read Figure 3.6.12 Port 62 91C630-54 2005-11-15 TMP91C630 Port 6 Register 5 4 7 P6 Bit symbol (0012H) Read/Write After reset 6 3 P63 1 2 P62 R/W 0 1 P61 1 0 P60 1 7 Bit symbol P6FC (0015H) Read/Write After reset Function Note: 6 Port 6 Function Register 5 4 3 P63F 0 2 P62F W 0 0: Port 1 P61F 0 1: CS 0 P60F 0 Read-modify-write is prohibited for the registers P6FC. 0 1 0 1 0 1 0 1 Port (P60) CS0 Port (P61) CS1 Port (P62) CS2 Port (P63) CS3 Figure 3.6.13 Register for Port 6 91C630-55 2005-11-15 TMP91C630 3.6.5 Port 7 (P70 to P75) Port 7 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port 7 to be an input port. In addition to functioning as a general-purpose I/O port, the individual port pins can also have the following functions: port pins 70 and 73 can function as the inputs TA0IN and TA4IN to the 8-bit timer, and port pins 71, 72 and 74 can function as the 8-bit timer outputs TA1OUT, TA3OUT and TA5OUT. For each of the output pins, timer output can be enabled by writing a 1 to the corresponding bit in the Port 7 function register (P7FC). Resetting clears all bits of the registers P7CR and P7FC to 0, and sets all bits to be input port pins. Reset Direction control (on bit basis) P7CR write Function control (on bit basis) Internal data bus P7FC write S Output latch SB P7 write Selector INT1 INT3 INT4 P70 (TA0IN/INT1) P73 (TA4IN/INT3) P75 (INT4) P7 read A Level or edge and rising edge or falling edge TA0IN TA4IN IIMC0 IIMC1 IIMC1 Figure 3.6.14 Ports 70, 73 and 75 91C630-56 2005-11-15 TMP91C630 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus S Output latch P7 write AS Selector Timer F/F out B B Selector P7 read SA P71 (TA1OUT) P74 (TA5OUT) TA1OUT: TMRA1 TA5OUT: TMRA5 Figure 3.6.15 Ports 71 and 74 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus Function control (on bit basis) P7FC write S Output latch Timer F/F out AS Selector B B Selector P72 (TA3OUT/INT2) P7 write (TA3OUT: TMRA3) P7 read SA INT2 Edge or level & Rising edge or falling edge IIMC0 Figure 3.6.16 Port 72 91C630-57 2005-11-15 TMP91C630 Port 7 Register 5 4 P75 P74 7 P7 Bit symbol (0013H) Read/Write After reset 6 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output register is set to 1) 7 P7CR Bit symbol (0016H) Read/Write After reset 6 Port 7 Control Register 5 4 P75C 0 P74C 0 3 P73C W 0 2 P72C 0 1 P71C 0 0 P70C 0 Port 7 I/O Setting 0 Input 1 Output 7 P7FC (0017H) Read/Write After reset Function Bit symbol 6 P72F2 W 0 0: Port 1: INT2 input Port 6 Function Register 5 4 3 P75F W 0 0: Port 1: INT4 input 0 0: Port P74F P73F W 0 0: Port 2 P72F1 W 0 0: Port 1 P71F 0 0: Port 0 P70F W 0 0: Port 1: TA5OUT 1: INT3 input 1: TA3OUT 1: TA1OUT 1: INT1 input Note: Read-modify-write are prohibited for the registers P7CR and P7FC. Setting P71 as Timer Output 1 P7FC P7CR Setting P72 as Timer Output 3 P7FC P7CR Setting P74 as Timer Output 5 P7FC P7CR 1 1 1 1 1 1 Figure 3.6.17 Port 7 Registers 91C630-58 2005-11-15 TMP91C630 3.6.6 Port 8 (P80 to P87) • Port pins 80 to 87 Port pins 80 to 87 constitute a 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets P80 to P87 to be an input port. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port pins, P80 to P87 can also function as the I/O for serial channel 0. These function can be enabled for I/O by writing a 1 to the corresponding bit of the Port 8 Function Register (P8FC). Resetting clears all bits of the registers P8CR and P8FC to 0 and sets all bits to be input port pins. (with pull-up resistors). (1) Port pins 80 (TXD0) and 84 (TXD1) As well as functioning as I/O port pins, port pins 80 and 84 can also function as serial channel TXD output pins. These port pins feature a programmable open-drain function. Reset Direction control (Each bit can be set individually.) P8CR write Internal data bus Function control (Each bit can be set individually.) P8FC write S Output latch P8 write TXD0 or TXD1 A S P80 (TXD0) P84 (TXD1) P-channel (Programmable pull-up) Selector B S B Open-drain possible ODE Output buffer Selector P8 read A Figure 3.6.18 Port Pins 80 and 84 91C630-59 2005-11-15 TMP91C630 (2) Port pins 81 (RXD0) and 85 (RXD1) Port pins 81 and 85 are I/O port pins and can also be used as RXD input pin for the serial channels. Reset Direction control (Each bit can be set individually.) Internal data bus P8CR write S Output latch Output buffer P8 write P8 read RXD0 or RXD1 S B Selector A P81 (RXD0) P85 (RXD1) P-channel (Programmable pull-up) Figure 3.6.19 Port pins 81 and 85 (3) Port pins 82 ( CTS0 /SCLK0) and 86 ( CTS1 /SCLK1) Port pins 82 and 86 are I/O port pins and can also be used as the CTS input pins or SCLK I/O pins for the serial channels. Reset Direction control (Each bit can be set individually.) P-channel P8CR write Function contorl (Each bit can be set individually.) P8FC write S Output latch P8 write SCLK0 SCLK1 (Programmable pull-up) Internal data bus A S P82 (SCLK0/ CTS0 ) P86 (SCLK1/ CTS1 ) Selector B SB Selector P8 read SCLK0, CTS0 input SCLK1, CTS1 input A Figure 3.6.20 Ports 82 and 86 91C630-60 2005-11-15 TMP91C630 (4) Port pins 83 ( STS0 ) and 87 ( STS1 ) Port pins 83 and 87 are I/O port pins and can also be used as STS output pin for the received data request signal. Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch P8 write STS0 or STS1 Internal data bus P-channel (Programmable pull-up) S A Y Selector B S Selector Y B A P83 ( STS0 ) P87 ( STS1 ) P8 read Figure 3.6.21 Port Pins 83 and 87 91C630-61 2005-11-15 TMP91C630 Port 8 Register 5 4 P85 P84 R/W Data from external port (Output latch register is set to 1) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register): Pull-up resistor ON 7 Bit symbol P8 Read/Write (0018H) After reset Function P87 6 P86 3 P83 2 P82 1 P81 0 P80 7 Bit symbol P8CR (001AH) Read/Write After reset Function P87C 0 6 P86C 0 Port 8 Control Register 5 4 P85C 0 P84C W 0 3 P83C 0 2 P82C 0 1 P81C 0 0 P80C 0 0: Input 1: Output Port 8 I/O Setting 0 Input 1 Output 7 Bit symbol P8FC (001BH) Read/Write After reset Function P87F W 0 0: Port 1: STS1 output 6 P86F W 0 0: Port 1: SCLK1 output Port 8 Function Register 5 4 3 P84F W 0 0: Port 1: TXD1 output P83F W 0 0: Port 1: STS0 output 2 P82F W 0 0: Port 1: SCLK0 output 1 0 P80F W 0 0: Port 1: TXD0 input To Set P80 and 84 for TXD0 and TXD1 Outputs P8FC 1 P8CR 1 To Set P82 and P86 for SCLK0 and SCLK1 Outputs P8FC P8CR 1 1 To set P83 and P87 for STS0 and STS1 Outputs P8FC 1 P8CR 1 7 Bit symbol ODE (002FH) Read/Write After reset Function 6 5 4 ODE84 W 0 1: P84ODE 3 2 1 0 ODE80 W 0 1: P80ODE Note 1: Read-modify-write are prohibited for the registers P8CR and P8FC. Note 2: Writing ODE register sets the TXD0, 1 pin to be open-drain. No register is provided for switching between the I/O port and RXD input functions of the P81/RXD0, P85/RXD1 pin. Hence, when Port 8 is used as an input port, the serial data input signals received on those pins are also input to the SIO. Figure 3.6.22 Port 8 Register 91C630-62 2005-11-15 TMP91C630 3.6.7 Port 9 (P90, P93 to P96) Port 9 is an 5-bit general-purpose I/O port. Each bit can be set individually for input or output, Resetting sets port 9 to be an input port, It also sets all bits in the output latch register P9 to 1. In addtion to functioning as a general-purpose I/O port, the various pins of Port 9 can also function as the clock input for the 16-bit timer flipflop putput, on as input INT5. These functions cn be enabled by writing a 1 to the corresponding bits in the Port 9 function registers (P9FC). (1) P90 Reset Direction control (on bit basis) P9CR write Internal data bus S Output latch P90 (INT5) P9 write S B Selector Y A P9 read INT5 Level or edge and rising edge or falling edge IIMC1 P9FC Figure 3.6.23 Port 90 91C630-63 2005-11-15 TMP91C630 (2) P93 to P96 Reset Direction control (on bit basis) P9CR write S Output latch P9 write P9 read TB0IN0 TB0IN1 Internal data bus A Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch A P9 write Timer F/F OUT TB0OUT0: TMRB0 TB0OUT1: TMRB0 P93 (TB0IN0) P94 (TB0IN1) S B Selector S P95 (TB0OUT0) P96 (TB0OUT1) Selector B B Selector P9 read SA Figure 3.6.24 Port Pins P93 to P96 91C630-64 2005-11-15 TMP91C630 Port 9 Register 5 4 P95 R/W P94 7 Bit symbol Read/Write P9 (0019H) After reset 6 P96 3 P93 2 1 0 P90 R/W Data from external port (Output latch register is set to 1) Data from external port (Output latch register is set to 1) 7 Bit symbol P9CR Read/Write (001CH) After reset Function 6 P96C 0 Port 9 Control Register 5 4 P95C W 0 0 P94C 3 P93C 0 2 1 0 P90C W 0 0: Input 1: Output 0: Input 1: Output Port 9 I/O Setting 0 Input 1 Output 7 P9FC (001DH) Read/Write After reset Function Bit symbol 6 P96F W 0 0: Port Port 9 Function Register 5 4 P95F W 0 0: Port 3 2 1 0 P90F W 0 0: Port 1: INT5 input 1: TB0OUT1 1: TB0OUT0 To Set P95 for TMRB0OUT0 Output 1 P9FC 1 P9CR To Set P96 for TMRB0OUT1 Output 1 1 Note: Read-modify-write are prohibited for the registers P9CR and P9FC. P9FC P9CR Figure 3.6.25 Port 9 Registers 91C630-65 2005-11-15 TMP91C630 3.6.8 Port A (PA0 to PA7) Port A is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. Internal data bus Port A read PA0 to PA7 ( ADTRG , AN0 to AN7) Conversion result register AD read AD converter Channel selector ADTRG (for PA3 only) Figure 3.6.26 Port A Port A Register 5 4 PA5 PA4 R Data from external port 7 Bit symbol PA (001EH) Read/Write After reset Note: PA7 6 PA6 3 PA3 2 PA2 1 PA1 0 PA0 The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.6.27 Port A Register 91C630-66 2005-11-15 TMP91C630 3.6.9 Port Z (PZ2, PZ3) Port Z is a 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting clears all bits of the output latch PZ to 1, the control register PZCR and the function register PZFC to 0 and sets PZ2 and PZ3 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port. Port Z also functions as I/O for the CPU’s control/status signal. Reset Direction control (on bit basis) PZCR write Function control Internal data bus (on bit basis) PZFC write S Selector S Output latch PZ write HWR P-channel (Programmable pull-up) PZ2 ( HWR ) Output buffer A B PZ read Figure 3.6.28 Port Z2 Reset Direction control (on bit basis) Internal data bus PZCR write S Output latch PZ write S Output buffer B P-channel (Purogrammable pull-up) PZ3 Selector PZ read A Figure 3.6.29 Port Z3 91C630-67 2005-11-15 TMP91C630 7 Bit symbol Read/Write PZ After reset (007DH) Function 6 Port Z Register 5 4 3 PZ3 R/W 2 PZ2 1 0 Data from external port (Note) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON Note: Output latch register is set to 1. 7 Bit symbol PZCR (007EH) Read/Write After reset Function 6 Port Z Control Register 5 4 3 PZ3 W 0 0: In 1: Out 2 PZ2 0 1 0 Setting Port Z as I/O 0 1 Input Output 7 PZFC (007FH) Read/Write After reset Function Bit symbol 6 Port Z Control Register 5 4 3 2 PZ2F W 0 0: Port 1: HWR 1 0 Figure 3.6.30 Port Z Registers 91C630-68 2005-11-15 TMP91C630 3.7 Chip Select/Wait Controller On the TMP91C630, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the Port 6 function register P6FC must be set. External connection of ROM and SRAM is supported. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin which controls these states is the bus wait request pin ( WAIT ). 3.7.1 Specifying an Address Area The address areas CS0 to CS3 are specified using the memory start address registers (MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3). During each bus cycle, a compare operation is performed to determine whether or not the address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the result of the comparison is a match, it indicates that the corresponding CS area is to be accessed. If so, the corresponding CS0 to CS3 pin outputs the chip select signal and the bus cycle proceeds according to the settings in the corresponding B0CS to B3CS chip select/wait control register. See 3.7.2, chip select/wait control registers. 91C630-69 2005-11-15 TMP91C630 (1) Memory start address registers Figure 3.7.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The eight most significant bits (A23 to A16) of the start address should be set in . The 16 least significant bits of the start address (A15 to A0) are fixed to 0. Thus the start address can only be set to lie on a 64-Kbyte boundary, starting from 000000H. Figure 3.7.2 shows the relationship between the value set in the start address register and the start address. Memory Start Address Registers (for Areas CS0 to CS3) 7 6 5 4 3 2 MSAR0 (00C8H)/ MSAR1 (00CAH) MSAR2 (00CCH)/ MSAR3 (00CEH) Bit symbol Read/Write After reset Function 1 1 1 1 S23 S22 S21 S20 R/W 1 1 1 1 Determines A23 to A16 of start address. S19 S18 1 S17 0 S16 Sets start addresses for areas CS0 to CS3. Figure 3.7.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Value in start address register (MSAR0 to MSAR3) 000000H ······················· 00H 010000H ······················· 01H 020000H ······················· 02H 030000H ······················· 03H 040000H ······················· 04H 050000H ······················· 05H 060000H ······················· 06H to to FF0000H ······················ FFH FFFFFFH Figure 3.7.2 Relationship between Start Address and Start Address Register Value 91C630-70 2005-11-15 TMP91C630 (2) Memory address mask registers Figure 3.7.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0 to MAMR3) which is set to 1 masks the corresponding bit of the start address which has been set in the corresponding memory start address register (MSAR0 to MSAR3). The compare operation used to determine whether or not a bus address is in one of the areas CS0 to CS3 only compares address bits for which a 0 has been set in the corresponding bit position in the corresponding memory address mask register. Also, the address bits which each memory address mask register can mask vary from register to register; hence, the possible size settings for the areas CS0 to CS3 differ accordingly. Memory Address Mask Register (for CS0 Area) 7 6 5 4 3 MAMR0 (00C9H) Read/Write After reset Function Bit symbol V20 1 V19 1 V18 1 V17 R/W 1 1 1 1 1 Sets size of CS0 area 0: used for address compare V16 2 V15 1 V14 to 9 0 V8 Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes. 7 MAMR1 Bit symbol (00CBH) Read/Write After reset Function V21 1 Memory Address Mask Register (CS1) 6 5 4 3 V20 1 V19 1 V18 R/W 1 1 V17 2 V16 1 1 V15 to 9 1 0 V8 1 Sets size of CS0 area 0: used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2 and CS3) 7 6 5 4 3 MAMR2 (00CDH)/ Bit symbol MAMR3 (00CFH) Read/Write After reset Function V22 1 V21 1 V20 1 V19 R/W 1 1 V18 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area 0: used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.7.3 Memory Address Mask Registers 91C630-71 2005-11-15 TMP91C630 (3) Setting memory start addresses and address areas Figure 3.7.4 shows an example in which CS0 is specified to be a 64-Kbyte address area starting at 010000H. First, MSAR0, the eight most significant bits of the start address register and which correspond to the memory start address, are set to 01H. Next, based on the desired CS0 area size, the difference between the start address and the end address (01FFFFH) is calculated. Bits 20 to 8 of this result constitute the mask value for the desired CS0 area size. Setting this value in MAMR0 (bits 20 to 8 of the memory address mask register) sets the desired area size for CS0. In this example 07H is set in MAMR0, specifying an area size of 64 Kbytes. 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CSO area size (64 Kbytes) Memory start address S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 to V9 V8 MSMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.7.4 Example Showing How to Set the CS0 Area A reset sets MSAR0 to MSAR3 and MAMR0 to MAMR3 to FFH. In addition, B0CS, B1CS and B3CS are reset to 0, disabling the CS0, CS1 and CS3 areas. However, since a reset resets B2CS to 0 and sets B2CS to 1, CS2 is enabled with the address range 002800H to 01F7FFH, 020000H to FFFFFFH. When addresses outside the areas specified as CS0 to CS3 are accessed, the bus width and number of waits specified in BEXCS are used. (See 3.7.2, Chip Select/Wait Control Registers.) 91C630-72 2005-11-15 TMP91C630 (4) Address area size specification Table 3.7.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A Δ indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register. If an area size for a CS area marked Δ in the table is to be set, the start address must either be set to 000000H or to a value that is greater than 000000H by an integer multiple of the desired area size. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the lowest-numbered CS area has highest priority (e.g. CS0 has a higher priority than any other area). Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. b. Invalid start addresses 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. 000000H 010000H 030000H 050000H Table 3.7.1 Valid Area Sizes for Each CS Area Size (bytes) CS area 256 512 32 K 64 K 128 K Δ Δ Δ Δ 256 K Δ Δ Δ Δ 512 K Δ Δ Δ Δ 1M Δ Δ Δ Δ 2M Δ Δ Δ Δ 4M 8M CS0 CS1 CS2 CS3 Δ Δ Δ Δ Δ 91C630-73 2005-11-15 TMP91C630 3.7.2 Chip Select/Wait Control Registers Figure 3.7.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 plus any other) are set in the respective chip select/wait control registers, B0CS to B3CS or BEXCS. Chip Select/Wait Control Register 7 B0CS (00C0H) Bit symbol Read/Write Read-modify After reset -write Function instructions are prohibited. 6 5 B0OM1 4 B0OM0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B2BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits B1W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits B2W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits B3W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits BEXW2 W 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 1 B0W1 0 0 B0W0 0 B0E W 0 0: Disable 1: Enable 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: B1OM1 B1OM0 1xx: Reserved B1CS (00C1H) Bit symbol Read/Write B1E W 0 0: Disable 1: Enable B1W1 0 B1W0 0 Read-modify After reset -write Function instructions are prohibited. 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area B2OM1 B2OM0 1xx: Reserved B2CS (00C2H) Bit symbol Read/Write After reset B2E 1 0: Disable 1: Enable B2W1 0 B2W0 0 Read-modify Functions -write instructions are prohibited. 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: B3OM1 B3OM0 1xx: Reserved B3CS (00C3H) Bit symbol Read/Write After reset B3E W 0 0: Disable 1: Enable B3W1 0 B3W0 0 Read-modify Functions -write instructions are prohibited. 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: 1xx: Reserved BEXCS (00C7H) Read-modify -write instructions are prohibited. Bit symbol Read/Write After reset Functions BEXW1 0 BEXW0 0 1xx: Reserved Master Enable Bit 0 1 CS area disable CS area enable Chip Select Output Waveform Selection 00 For ROM/SRAM 01 10 Don’t care 11 Number of address area waits (See 3.7.2 (3) Wait Control.) Data Bus width Selection 0 1 16-bit data bus 8-bit data bus CS2 Area Selection 0 1 16-Mbyte area Specified address area Figure 3.7.5 Chip Select/Wait Control Registers 91C630-74 2005-11-15 TMP91C630 (1) Master enable bits Bit 7 (, , or ) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables the settings. A Reset disables , and (i.e sets them to 0) and enables (i.e. sets it to 1). Hence after a Reset only the CS2 area is enabled. (2) Data bus width selection Bit 3 (, , , or ) of a chip select/wait control register specifies the width of the data bus. This bit should be set to 0 when memory is to be accessed using a 16-bit data bus, and to 1 when an 8-bit data bus is to be used. This process of changing the data bus width according to the address being accessed is known as dynamic bus sizing. For details of this bus operation see Figure 3.7.2. Table 3.7.2 Dynamic Bus Sizing Operand Data Operand Start Memory Data Bus Width Address Bus Width 8 bits 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 32 bits 2n + 0 (Even number) 8 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 1 (Odd number) 8 bits 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 16 bits 2n + 1 2n + 2 2n + 4 Input data in bit positions marked xxxxx is ignored during a read. During a write, the bus lines corresponding to these bit positions go high-impedance and the write strobe signal for the bus remains inactive. 91C630-75 2005-11-15 TMP91C630 (3) Wait control Bits 0 to 2 (, , , or ) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits. Bit settings other than those listed in the table should not be made. Table 3.7.3 Wait Operation Settings 000 001 010 No. of Waits 2 waits 1 wait (1 + N) waits Wait Operation Inserts a wait of two states, irrespective of the WAIT pin state. Inserts a wait of one state, irrespective of the WAIT pin state. Inserts one wait state, then continuously samples the state of the WAIT pin. While the WAIT pin remains Low, the wait continues; the bus cycle is prolonged until the pin goes High. Ends the bus cycle without a wait, regardless of the WAIT pin state. Do not set. 011 1xx 0 waits Reserved A Reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS (bit 6 of the chip select/wait control register for CS2) to 0 designates the 16-Mbyte area 002800H to 01F7FFH, 020000H to FFFFFFH as the CS2 area. Setting B2CS to 1 designates the address area specified by the start address register MSAR2 and the address mask register MAMR2 as CS2 (i.e. if B2CS = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are). A Reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area. 91C630-76 2005-11-15 TMP91C630 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: a. b. c. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 . The CS0 to CS3 pins can also function as pins P60 to P63. To output a chip select signal using one of these pins, set the corresponding bit in the Port 6 function register P6FC to 1. If a CS0 to CS3 address is specified which is actually an internal I/O, RAM or ROM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is clear to 0. MSAR0 = 01H ............Start address: 010000H MAMR0 = 07H...........Address area: 64 Kbytes B0CS = 83H ...............ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled 91C630-77 2005-11-15 TMP91C630 3.7.3 Connecting External Memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91C630. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C630 CS0 CS1 CS2 Address bus A0 to A23 D8 to D15 D0 to D7 RD WR CS CS CS CS Upper byte ROM OE OE Lower byte ROM 8-bit RAM OE WE 8-bit I/O OE WE Figure 3.7.6 Example of External Memory Connection (ROM uses 16-bit bus; RAM and I/O use 8-bit bus.) A reset clears all bits of the Port 4 control register P6CR and the Port 6 function register P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91C630-78 2005-11-15 TMP91C630 3.8 8-Bit Timers (TMRA) The TMP91C630 features six built-in 8-bit timers. These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module consists of two channels and can operate in any of the following four operating modes. • • • • 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG − variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM − variable duty cycle with constant period) Figure 3.8.1 to Figure 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45. Each channel consists of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (special-function registers). Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. Table 3.8.1 Registers and Pins for Each Module Module Input pin for external clock Output pin for timer flip-flop Timer run register Timer register SFR (address) Timer mode register Timer flip-flop control register TMRA01 TA0IN (shared with P70) TA1OUT (shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 No TA3OUT (shared with P72) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TMRA45 TA4IN (shared with P73) TA5OUT (shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) External pin 91C630-79 2005-11-15 3.8.1 Prescaler 2 φT1 φT16 Timer flip-flop TA1FF Selector Selector φT1 φT16 φT256 TA01MOD 8-bit up-counter (UC1) 8-bit up-counter (UC0) n Prescaler clock: φT0 4 φT4 φT256 8 16 32 64 128 256 512 Run/clear TA01RUN Block Diagrams Timer flip-flop output: TA1OUT TA01RUN TA01RUN External input clock: TA0IN φT1 φT4 φT16 TA01MOD 2 Over flow TA01MOD TA1FFCR Figure 3.8.1 TMRA01 Block Diagram 91C630-80 8-bit up-counter (CP0) Match detect TA0TRG TA01MOD 8-bit timer register TA0REG TA01RUN Register buffer 0 Internal bus TMRA0 interrupt output: INTTA0 TMRA0 match output: TA0TRG Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG Internal bus TMRA1 interrupt output: INTTA1 TMP91C630 2005-11-15 Prescaler Prescaler clock: φT0 2 φT1 φT256 Timer flip-flop TA3FF TA23RUN Selector Selector 8-bit up-counter (UC2) 2 Over flow TA23MOD n 4 φT4 φT16 8 16 32 64 128 256 512 Run/clear TA23RUN Timer flip-flop output: TA3OUT TA23RUN>6 ← WA Enable INTAD and set it to interrupt level 4. Set pin AN3 to be the analog input channel. Start conversion in Channel fixed single conversion mode. Interrupt routine processing example: WA WA (0800H) Read value of ADREG37L and ADREG37H into 16-bit general-purpose register WA. Shift contents read into WA six times to right and zero-fill upper bits. Write contents of WA to memory address 0800H. b. This example repeatedly converts the analog input voltages on the three pins AN0, AN1 and AN2, using channel scan repeat conversion mode. INTE0AD ADMOD1 ADMOD0 Note: ←X000−−−− ←11XX0010 ←XX000111 Disable INTAD. Set pins AN0 to AN2 to be the analog input channels. Start conversion in Channel scan repeat conversion mode. X = Don’t care, “−” = No change 91C630-154 2005-11-15 TMP91C630 3.12 Watchdog Timer (runaway detection timer) The TMP91C630 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset. (The level of external RESET pin is not changed.) 3.12.1 Configuration Figure 3.12.1 is a block diagram of he watchdog timer (WDT). WDMOD RESET Reset control Internal reset INTWD interrupt WDMOD 2 fSYS (fFPH/2) 15 Selector 21 2 17 219 2 Binary counter (22 stages) Reset R Q S Internal reset Write 4EH Write B1H WDMOD WDT control register WDCR Internal data bus Figure 3.12.1 Block Diagram of Watchdog Timer Note: The watchdog timer cannot operate by disturbance noise in some case. Take care when design the device. 91C630-155 2005-11-15 TMP91C630 The watchdog timer consists of a 22-stage binary counter which uses the system clock (fSYS) as the input clock. The binary counter can output fSYS/215, fSYS/217, fSYS/219 and fSYS/221. WDT counter n Overflow 0 WDT interrupt Clear write code WDT clear (Soft ware) Figure 3.12.2 Normal Mode The runaway is detected when an overflow occurs, and the watchdog timer can reset device. In this case, the reset time will be between 22 and 29 states (19.6 to 25.8 μs at fFPH = 36MHz, fOSCH = 2.25 state )is fFPH/2, where fFPH is generated by dividing the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function. Overflow WDT counter n WDT interrupt Internal reset 22 to 29 states (19.6 to 25.8 μs at fOSCH = 36 MHz, fFPH = 2.25 MHz) Figure 3.12.3 Reset Mode 91C630-156 2005-11-15 TMP91C630 3.12.2 Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a reset this register is initialized to WDMOD = 00. The detection times for WDT are shown in Figure 3.12.4. b. Watchdog timer enable/disable control register On a reset WDMOD is initialized to 1, enabling the watchdog timer. To disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (B1H) to the watchdog timer control register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting to 1. c. Watchdog timer out reset connection This register is used to connect the output of the watchdog timer with the RESET terminal internally. Since WDMODis initialized to 0 on a reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear the binary counter for the watchdog timer. • Disable control The watchdog timer can be disabled by clearing WDMOD to 0 and then writing the disable code (B1H) to the WDCR register. WDMOD WDCR ←0 − − − − − − − ←1 0 1 1 0 0 0 1 Clear WDMOD to 0. Write the disable code (B1H). • Enable control Set WDMOD to 1. • Watchdog timer clear control To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR register. WDCR ←0 1 0 0 1 1 1 0 Write the clear code (4EH). Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please refer to setting example.) Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once. 91C630-157 2005-11-15 TMP91C630 7 WDMOD Bit symbol (0300H) Read/Write After reset Function WDTE R/W 1 6 WDTP1 R/W 0 5 WDTP0 0 4 − 3 − 2 I2WDT R/W 0 IDLE2 0: Stop 1: Operate 1 RESCR 0 1: Internally connects WDL out to the reset pin 0 − R/W 0 Always write 0 R/W 0 Always write 0 R/W 0 Always write 0 WDT control Select detecting time 15 1: Enable 00: 2 /fSYS 17 01: 2 /fSYS 19 10: 2 /fSYS 21 11: 2 /fSYS Watchdog Timer out Control 0 1 − Connects WDT out to a reset IDLE2 Control 0 1 Watchdog timer detection time Stop Operation fc = 36 MHz SYSCR1 Gear Value 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) Watchdog Timer Detection Time WDMOD 00 1.82 ms 3.64 ms 7.28 ms 14.56 ms 29.13 ms 01 7.28 ms 14.56 ms 29.13 ms 58.25 ms 116.51 ms 10 29.13 ms 58.25 ms 116.51 ms 233.02ms 466.03 ms 11 116.51 ms 233.02 ms 466.03 ms 932.07 ms 1864.14 ms Watchdog Timer Enable/Disable Control 0 1 Disabled Enabled Figure 3.12.4 Watchdog Timer Mode Register 7 WDCR (0301H) Read -modify -write instruction is prohibited Bit symbol Read/Write After reset Function 6 5 4 − 3 W − 2 1 0 B1H: WDT disable code 4EH: WDT clear code Disable/Clear WDT B1H 4EH Others Disable code Clear code Don’t care Figure 3.12.5 Watchdog Timer Control Register 91C630-158 2005-11-15 TMP91C630 3.12.3 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD has elapsed. The watchdog timer must be zero-cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti-mulfunction program. By connecting the watchdog timer out pin to a peripheral device’s reset input, the occurrence of a CPU malfunction can also be relayed to other devices. The watch dog timer works immediately after reset. The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter continues counting during bus release (When BUSAK goes Low). When the device is in IDLE2 mode, the operation of WDT depends on the WDMOD setting. Ensure that WDMOD is set before the device enters IDLE2 mode. Example: a. Clear the binary counter. WDCR ←01001110 Write the clear code (4EH). b. Set the watchdog timer detection time to 217/fSYS. WDMOD ← 1 0 1 − − − − − c. Disable the watchdog timer. WDMOD ← 0 − − − − − X X WDCR ← 1 0 1 1 0 0 0 1 Clear WDTE to 0. Write the disable code (B1H). 91C630-159 2005-11-15 TMP91C630 3.13 Multi-Vector Control 3.13.1 Multi-Vector Controller (1) Outline By rewriting the value of multi-vector control resister (MVEC0 and MVEC1), a vector table is arbitrarily movable. (2) Control resister The amount of 228 bytes becomes an interruption vector area from the value set as vector control resister (MVEC0 and MVEC1). Vector Control Resister Composition 7 MVEC0 Bit symbol (00AEH) Read/Write After reset Function VEC7 R/W 1 6 VEC6 R/W 1 5 VEC5 R/W 1 4 VEC4 R/W 1 3 VEC3 R/W 1 2 VEC2 R/W 1 1 VEC1 R/W 1 0 VEC0 R/W 1 Vector address A15 to A8 7 MVEC1 Bit symbol (00AFH) Read/Write After reset Function VEC15 R/W 1 6 VEC14 R/W 1 5 VEC13 R/W 1 4 VEC12 R/W 1 3 VEC11 R/W 1 2 VEC10 R/W 1 1 VEC9 R/W 1 0 VEC8 R/W 1 Vector address A23 to A16 Circuit composition CPU output address AL23 to AL8 AL23 to AL8 CS circuit form FFFF28H to FFFFFFH CS AL8 Resister (MVEC0) S A Y B A8 Internal address A23 to A8 Resister (MVEC1) AL23 A23 Note: Write MVEC1 and MVEC0 after Making an Interruption Prohibition State. 91C630-160 2005-11-15 TMP91C630 3.13.2 Multi-Boot Mode (1) Outline The TMP91C630 has multi-boot mode available as an on-board programming operation mode. When in multi-boot mode, the boot ROM is mapped into memory space. This boot ROM is a mask ROM that contains a program to rewrite the flash memory on-board. Rewriting is accomplished by connecting the TMP91C630’s SIO and the programming tool (controller) and then sending commands from the controller to the target board. The boot program included in the boot ROM only has the function of a loader for transferring program data from an external source into the device’s internal RAM. Rewriting can be performed by UART. From 1000H to 105FH in device’s internal RAM is work area of boot program. Don’t transfer program data in this work area. Figure 3.13.1 shows an example of how to connect the programming controller and the target board. (When ROM has 16-bit data bus.) UART 3 pins Programming controller TXD0 (Output) RXD0 (Input) RTS0 (P83) (Output) CS2 RD CS OE WE TMP91C630 WR ROM DT0 to DT15 AD0 to AD15 Boot/Normal BOOT D0 to D15 A1 to A16 Figure 3.13.1 Example for Connecting Units for On-Board Programming (2) Mode setting To execute on-board programming, start the TMP91C630 in multi-boot mode. Settings necessary to start up in multi-boot mode are shown below. BOOT = = L RESET After setting the BOOT pin each to the above conditions and a RESET , the TMP91C630 start up in multi-boot mode. 91C630-161 2005-11-15 TMP91C630 (3) Memory map Figure 3.13.2 shows memory maps for multi-chip and multi-boot modes. When start up in multi-boot mode, internal boot ROM is mapped in FFF800H address, the boot program starts up. When start up in multi-chip mode, internal boot ROM is mapped in 1F800H address, it can be made to operate arbitrarily by the user. Program starting address is 1F800H. Multi-chip mode 000000H 000100H Internal I/O (4 Kbytes) 000000H 000100H Multi-boot mode Internal I/O (4 Kbytes) Direct area (n) 001000H Internal RAM (6 Kbytes) 002800H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH 001000H Internal RAM (6 Kbytes) 002800H External memory 16-Mbyte area (r32) (−r32) (r32+) (r32 + d8/16) (r32 + r8/16) (nnn) External memory FFFF00H FFFFFFH Vector table (256 bytes) FFF800H FFFEFFH FFFF00H FFFFFFH Internal boot ROM (2 Kbytes) Vector table (256 bytes) ( = Internal area) Figure 3.13.2 TMP91C630 Memory Map 91C630-162 2005-11-15 TMP91C630 (4) SIO interface specifications The following shows the SIO communication format in multi-boot mode. Before on-board programming can be executed, the communication format on the programming controller side must also be set up in the same way as for the TMP91C630. Note that although the default baud rate is 9600 bps, it can be changed to other values as shown in Table 3.13.3. Serial transfer mode: UART (asynchronous communication) mode, full-duplex communication Data length: 8 bits Parity bit: None STOP bit: 1 bit Handshake: Micro-controller (P83) → Programming controller Baud rate (default): 9600 bps (5) SIO data transfer format Table 3.13.1 through 3.13.6 show supported frequencies, data transfer format, baud rate modification commands, operation commands, version management information, and frequency measurement result with data store location, respectively. Also refer to the description of boot program operation in the latter pages of this manual as you read these tables. Table 3.13.1 Supported Frequencies 16.000 MHz 20.000 MHz 22.579 MHz 25.000 MHz 32.000 MHz 33.868 MHz 36.000 MHz Table 3.13.2 Transfer Format Number of Bytes Transfer Data from Controller Transferred to TMP91C630 Boot ROM 1st byte 2nd byte 3rd byte : 6th byte 7th byte 8th byte 9th byte 10th byte : n’th -4 byte n’th -3 byte n’th -2 byte n’th -1 byte n’th byte RAM − Baud Rate 9600 bps 9600 bps 9600 bps Transfer Data from TMP91C630 to Controller − (Frequency measurement and baud rate auto set) OK: Echoback data (5AH) NG: Nothing transmitted Matching data (5AH) − − Version management information (See Table 3.13.5) Frequency information (See Table 3.13.6) − OK: Echoback data NG: Error code X 3 − 9600 bps 9600 bps 9600 bps Baud rate modification command (See Table 3.13.3) − User program Extended Intel Hex format(binary) − − Changed new baud rate NG: Operation stop by checksum error Changed new baud rate OK:SUM(High) (See (6) (iii) Notes on SUM) Changed new baud rate OK:SUM(Low) Changed new baud rate − Changed new baud rate OK: Echoback data (C0H) NG: Error code X 3 User program start command (C0H) (See Table 3.13.4) − JUMP to user program start address Note: Error code X 3 means sending an error code three times. Example, when error code is 62H, TMP91C630 sends 62H three times. About error code, see (6)(ii) Error Code. 91C630-163 2005-11-15 TMP91C630 Table 3.13.3 Baud Fate Modification Command Baud rate (bps) Modification command 9600 28H 19200 18H 38400 07H 57600 06H 115200 03H Table 3.13.4 Operation Command Operation command C0H Operation Start user program Table 3.13.5 Version Management Information Version information FRM1 ASCII code 46H, 52H, 4DH, 31H Table 3.13.6 Frequency Measurement Result Data Frequency of resonator (MHz) 1000H (RAM store address) 16.000 00H 20.000 01H 22.579 02H 25.000 03H 32.000 04H 33.868 05H 36.000 06H (6) Description of SIO boot program operation When you start the TMP91C630 in multi-boot mode, the boot program starts up. The boot program provides the RAM loader function described below. RAM loader The RAM loader transfers the data sent from the controller in extended intel hex format into the internal RAM. When the transfer has terminated normally, the RAM loader calculates the SUM and sends the result to the controller before it starts executing the user program. The execution start address is the first address received. This RAM loader function provides the user’s own way to control on-board programming. To execute on-board programming in the user program, you need to use the flash memory command sequence to be connected. (Must be matched to the flash memory addresses in multi-boot mode). a. Operational procedure of RAM loader 1. 2. 3. Connect the serial cable. Make sure to perform connection before resetting the microcontroller. Set the BOOT pin to “Boot” and reset the micro-controller. The receive data in the 1st byte is the matching data. When the boot program starts in multi-boot mode, it goes to a state in which it waits for the matching data to receive. Upon receiving the matching data, it automatically adjusts the serial channels’ initial baud rate to 9600 bps. The matching data is 5AH. The 2nd byte is used to echo back 5AH to the controller upon completion of the automatic baud rate setting in the first byte. If the device fails in automatic baud rate setting, it goes to an idle state. The 3rd byte through 6th byte are used to send the version management information of the boot program in ASCII code. The controller should check that the correct version of the boot program is used. 4. 5. 91C630-164 2005-11-15 TMP91C630 6. The 7th byte is used to send information of the measured frequency. The controller should check that the frequency of the resonator is measured correctly. The receive data in the 8th byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table 3.13.3 are available. Even when you do not change the baud rate, be sure to send the initial baud rate data (28H;9600 bps). Baud rate modification becomes effective after the echoback transmission is completed. The 9th byte is used to echo back the received data to the controller when the data received in the 8th byte is one of the baud rate modification data corresponding to the device’s operating frequency. Then the baud rate is changed. If the received baud rate data does not correspond to the device’s operating frequency, the device goes to an idle state after sending 3 bytes of baud rate modification error code (62H). The receive data in the 10th byte through n’th - 4 byte is received as binary data in Extended Intel Hex format. No received data is echoed back to the controller. The RAM loader processing routine ignores the received data until it receives the start mark (3AH for “:”) in extended intel hex format. Nor does it send error code to the controller. After receiving the start mark, the routine receives a range of data from the data length to checksum and writes the received data to the specified RAM addresses successively. After receiving one record of data from start mark to checksum, the routine goes to a start mark waiting state again. If a receive error or checksum error of extended hex format occurs, the device goes to an idle state without returning error code to the controller. Because the RAM loader processing routine executes a SUM calculation routine upon detecting the end record, the controller should be placed in a SUM waiting state after sending the end record to the device. 7. 8. 9. 10. The n’th - 3 byte and the n’th - 2 byte are the SUM value that is sent to the controller in order of upper byte and lower byte. For details on how to calculate the SUM, refer to “Notes on SUM” in the latter page of this manual. The SUM calculation is performed only when no write error, receive error, or extended intel hex format error has been encountered after detecting the end record. Soon after calculation of SUM, the device sends the SUM data to the controller. The controller should determine whether writing to the RAM has terminated normally depending on whether the SUM value is received after sending the end record to the device. 11. After sending the SUM, the device goes to a state waiting for the user program start code. If the SUM value is correct, the controller should send the user program start command to the n’th - 1 byte. The user program start command is C0H. 12. The n’th byte is used to echo back the user program start code to the controller. After sending the echoback to the controller, the stack pointer is set to 105FH and the boot program jumps to the first address that is received as data in extended intel hex format. 13. If the user program start code is wrong or a receive error occurs, the device goes to an idle state after returning three bytes of error code to the controller. 91C630-165 2005-11-15 TMP91C630 b. Error code The boot program sends the processing status to the controller using various code. The error code is listed in the table below. Table 3.13.7 Error Code Error code 62H 64H A1H A3H Meaning of error code Baud rate modification error occurred. Operation command error occurred. Framing error in received data occurred. Overrun error in received data occurred. *1: When a receive error occurs when receiving the user program, the device does not send the error code to the controller. *2: After sending the error code, the device goes to an idle state. c. Notes on SUM 1. Calculation method SUM consists of byte + byte….. + byte, the sum of which is returned in word as the result. Namely, data is read out in byte and sum of which is calculated, with the result returned in word. Example: A1H B2H C3H D4H If the data to be calculated consists of the four bytes shown to the left, SUM of the data is: A1H + B2H + C3H + D4H = 02EAH SUM (HIGH) = 02H SUM (LOW) = EAH 2. Calculation data The data from which SUM is calculated is the RAM data from the first address received to the last address received. The received RAM write data is not the only data to be calculated for SUM. Even when the received addresses are noncontiguous and there are some unwritten areas, data in the entire memory area is calculated. The user program should not contain unwritten gaps. d. Notes on extended intel hex format (binary) 1. After receiving the checksum of a record, the device waits for the start mark (3AH for “:”) of the next record. Therefore, the device ignores all data received between records during that time unless the data is 3AH. Make sure that once the controller program has finished sending the checksum of the end record, it does not send anything and waits for two byes of data to be received (upper and lower bytes of SUM). This is because after receiving the checksum of the end record, the boot program calculates the SUM and returns the calculated SUM in two bytes to the controller. It becomes the cause of incorrect operation to write to areas out of device’s internal RAM. Therefore, when an extended record is transmitted, be sure to set a paragraph address to 0000H. Always make sure the first record type is an extended record. Because the initial value of the address pointer is 00H. 2. 3. 4. 91C630-166 2005-11-15 TMP91C630 5. Transmit a user program not by the ASCII code but by binary. However, start mark “:” is 3AH (ASCII code). Example: Transmit data in the case of writing in 16 bytes data from address 1060H Data Record 3A 10 1060 00 0607F100030000F201030000B1F16010 77 Data Record type Address Number of data “:” (Start mark) Check sum End Record 3A 00 0000 01 FF Check sum Record type Address Number of data “:” (Start mark) e. Error when receiving user program If the following errors occur in extended intel hex format when receiving the user program, the device goes to an idle state. • • When the record type is not 00H, 01H, 02H When a checksum error occurs f. Error between frequency measurement and baud rate The boot program measures the resonator frequency when receiving matching data. If an error is under 3%, the boot program decides on that frequency. Since there is an overlap between the margin of 3% for 32.000 MHz and 33.868 MHz, the boundary is set at the intermediate value between the two. The baud rate is set based on the measured frequency. Each baud rate includes a set error shown in Table 3.13.8. For example, in the case of 20.000 MHz and 9600 bps, the baud rate is actually set at 9615.38 bps with an error of 0.2%. To establish communication, the sum of the baud rate set error shown in Table 3.13.8 and the frequency error need to be under 3%. Table 3.13.8 Set Error of Each Baud Rate (%) 9600 bps 19200 bps 0.2 0.2 0.7 0.5 0.2 0.2 0.2 38400 bps 0.2 0.2 0 −0.1 57600 bps −0.6 −0.2 115200 bps −0.8 16.000 MHz 20.000 MHz 22.579 MHz 25.000 MHz 32.000 MHz 33.868 MHz 36.000 MHz 0.2 0.2 0 −0.2 0.9 0 0.5 0.6 0.7 0.2 0 0.5 0 0 0.2 0.1 0.2 0.2 0.2 0.2 −0.7 91C630-167 2005-11-15 TMP91C630 (7) Ports setup of the boot program Only ports shown in Table 3.13.9 are set up in the boot program. At the time of boot program use, be careful of the influence on a user system. Do not use CS0 space and P60 in the system which uses the boot program. Other ports are not setting up, and are the reset state or the state of boot program starting. Table 3.13.9 Ports Setting List Ports P60 P61 P62 P63 P80 P81 P82 P83 P84 P85 P86 P87 Function CS0 Input/Output Output Output Output Output Input Input Input Input Input Input Input Input High/Low − − Notes CS0 space is 20000H to 201FFH Port Port Port Port RxD0 Port Port Port Port Port Port High − High High − Not open drain port. This port becomes TxD0 after matching data reception. Low − − − − This port is set as the output and becomes RTS0 after matching data reception. −: Un-setting up (8) Setting method of microcontroller peripherals Although P83 has the RTS0 function, it is initially in a high impedance state and not set as RTS0 . To establish serial communication, attach a pull-down resister to P83. 91C630-168 2005-11-15 TMP91C630 4. 4.1 Electrical Characteristics Maximum Ratings Parameter Power supply voltage Input voltage Output current (per pin) Output current (per pin) Output current (total) Output current (total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature Symbol Vcc VIN IOL IOH ΣIOL ΣIOH PD TSOLDER TSTG TOPR Rating −0.5 to 4.0 −0.5 to Vcc + 0.5 2 −2 80 −80 600 260 −65 to 150 −40 to 85 Unit V V mA mA mA mA mW °C °C °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Parameter Power supply voltage (AVCC = DVCC) (AVSS = DVSS = 0 V) Vcc VIL VIL1 fc = 10 MHz to 36 MHz Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V 2.7 3.6 0.6 0.3 Vcc V Symbol Condition Min Typ. (Note) Max Unit D0 to D7, P10 to P17 (D8 to D15) Input Low Voltage The other ports RESET , NMI , BOOT P56 (INT0), P70 (INT1) P72 (INT2), P73 (INT3) P75 (INT4), P90 (INT5) AM0, 1 X1 D0 to D7, P10 to P17 (D8 to D15) VIL2 Vcc = 2.7 V to 3.6 V −0.3 0.25 Vcc VIL3 VIL4 VIH VIH1 Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V 2.0 0.7 Vcc 0.3 0.2 Vcc V Input High Voltage The other ports RESET , NMI , BOOT P56 (INT0), P70 (INT1) P72 (INT2), P73 (INT3) P75 (INT4), P90 (INT5) AM0, 1 X1 VIH2 Vcc = 2.7 V to 3.6 V 0.75 Vcc Vcc + 0.3 VIH3 VIH4 VOL VOH Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V IOL = 1.6 mA IOH = −400 μA Vcc − 0.3 0.8 Vcc 0.45 2.4 V Output low voltage Output high voltage Note: Typical measurement Condition is Ta = 25°C, Vcc = 3.0 V unless otherwise noted. 91C630-169 2005-11-15 TMP91C630 DC Characteristics (2/2) Parameter Input leakage current Output leakage current Power down voltage (at STOP, RAM back-up) RESET pull-up resistor BOOT pull-up resistor Symbol ILI ILO VSTOP RRST RBT CIO VTH RKH Min Typ. (Note 1) 0.02 0.05 Max ±5 ±10 3.6 400 400 10 Condition 0.0 ≤ VIN ≤ Vcc 0.2 ≤ VIN ≤ Vcc − 0.2 VIL2 = 0.2 Vcc, VIH2 = 0.8 Vcc Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V fc = 1 MHz Vcc = 2.7 V to 3.6 V Unit μA V kΩ kΩ pF V kΩ 2.0 80 80 Pin capacitance Schmitt width RESET , NMI , BOOT , INT0 to 5 0.4 80 1.0 400 17 25 8 3.5 10 Programmable pull-up resistor NORMAL (Note 2): (Note 3) IDLE2 (Note 3) IDLE1 (Note 3) STOP Vcc = 2.7 V to 3.6 V Vcc = 2.7 V to 3.6 V fc = 36 MHz Vcc = 2.7 V to 3.6 V Icc 4 1.5 0.1 mA μA Note 1: Typical measurement condition is Ta = 25°C, Vcc = 3.0 V unless otherwise noted. Note 2: Icc measurement conditions (NORMAL): All functions operate; output pins are open and input pins are fixed. Note 3: Power supply current from AVCC pin is included in power supply current (Icc) of DVCC pin. 91C630-170 2005-11-15 TMP91C630 4.3 AC Characteristics (1) Vcc = 2.7 to 3.6 V No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter fFPH period ( = x ) A0 to 23 valid → RD / WR fall RD rise → A0 to A23 hold WR rise → A0 to A23 hold Symbol tFPH tAC tCAR tCAW tAD tRD tRR tHR tWW tDW tWD tAW tCW tAPH tAPH2 tAPO Variable Min 27.6 x − 26 0.5x − 13.8 x − 13 3.5x − 40 2.5x − 34 2.5x − 25 0 2.0x − 25 1.5x − 35 x − 25 3.5x − 60 2.5x + 0 3.5x − 76 3.5x 3.5x + 60 fFPH = 36 MHz Min 27.6 1.6 0.0 14.6 56.6 35.0 44.0 0 30.2 6.4 2.6 36.6 69.0 20.6 96.6 156.6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 100 Max A0 to A23 valid → D0 to D15 input RD fall → D0 to D15 input RD low width RD rise → D0 to D15 hold WR low width D0 to D15 valid → WR rise WR rise → D0 to D15 hold (1 + N) waits mode A0 to A23 valid → WAIT input (1 + N) waits mode RD / WR fall → WAIT hold A0 to A23 valid → PORT input A0 to A23 valid → PORT hold A0 to A23 valid → PORT valid AC Measuring Conditions • • Output Level : High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF Input Level : High = 0.9 Vcc, Low = 0.1Vcc Note: Symbol x in the above table means the period of clock fFPH, it’s half period of the system clock fSYS for CPU core. The period of fFPH depends on the clock gear setting. 91C630-171 2005-11-15 TMP91C630 (2) Read cycle tFPH fFPH A0 to A23 CSn tAW tCW WAIT tAP Port input (Note) tAPH2 tAD RD tCAR tRR tAC tRD D0 to D15 tHR D0 to D15 Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91C630-172 2005-11-15 TMP91C630 (3) Write cycle fFPH A0 to A23 CSn WAIT tAPO Port output (Note) WR , HWR tCAW tWW tDW tWD D0 to D15 D0 to D15 Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91C630-173 2005-11-15 TMP91C630 4.4 AD Conversion Characteristics AVCC = DVCC, AVSS = DVSS Parameter Analog reference voltage (+) Analog reference voltage (−) Analog input voltage range Analog current for analog Reference voltage = 1 = 0 Error (not including quantizing errors) − Symbol VREFH VREFL VAIN IREF (VREFL = 0V) Min Vcc − 0.2 V Vss VREFL Typ. Vcc VSS Max Vcc Vss + 0.2 V VREFH Unit V 0.94 0.02 ±1.0 1.35 5.0 ±4.0 mA μA LSB Note 1: 1 LSB = (VREFH − VREFL)/1024 [V] Note 2: The value of Icc includes the current which flows through the AVCC pin. 91C630-174 2005-11-15 TMP91C630 4.5 Serial Channel Timing (I/O Internal Mode) Note: Symbol x in the below table means the period of clock fFPH, it’s half period of the system clock fSYS for CPU core. The period of fFPH depends on the clock gear setting. (1) SCLK input mode Variable Parameter Symbol Min Max tSCY tOSS tOHS tHSR tSRD tRDS 0 16X tSCY/2 − 4X − 85 tSCY/2 + 2X + 0 3 X + 10 tSCY − 0 0 36 MHz (Note) Min Max 0.44 25 276 92 440 Unit μs ns ns ns ns ns SCLK period Output data → SCLK rising/falling edge* SCLK rising/falling edge* → Output data hold SCLK rising/falling edge* → Input data hold SCLK rising/falling edge* → Valid data input Valid data input → SCLK rising/falling edge* *) SCLK rinsing/falling edge: Note: at tSCY = 16X (2) SCLK output mode The rising edge is used in SCLK rising mode. The falling edge is used in SCLK falling mode. Variable Parameter SCLK period (programable) Output data →SCLK rising/falling edge* SCLK rising/falling edge* → Output data hold SCLK rising/falling edge* → Input data hold SCLK rising/falling edge* → Valid data input Valid data input → SCLK rising/falling edge* Symbol Min tSCY tOSS tOHS tHSR tSRD tRDS 1 X + 90 16X tSCY/2 − 40 tSCY/2 − 40 0 tSCY − 1X − 90 Max 8192X 36 MHz (Note) Min Max 0.44 180 180 0 324 117 Unit μs ns ns ns ns ns *) SCLK rinsing/falling edge: Note: at tSCY = 16X The rising edge is used in SCLK rising mode. The falling edge is used in SCLK falling mode. tSCY SCLK SCLK tOSS Output data TXD Input data RXD 0 tSRD 0 Valid tOHS 1 tRDS 1 Valid tHSR 2 Valid 3 Valid 2 3 91C630-175 2005-11-15 TMP91C630 4.6 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1) Parameter Clock perild Clock low level width Clock high level width Symbol tVCK tVCKL tVCKH Variable Min 8X + 100 4 X + 40 4 X + 40 36 MHz Min 320 150 150 Max Max Unit ns ns ns Note: Symbol x in the above table means the period of clock fFPH, it’s half period of the system clock fSYS for CPU core. The period of fFPH depends on the clock gear setting. 4.7 Interrupts Note: Symbol x in the above table means the period of clock fFPH, it’s half period of the system clock fSYS for CPU core. The period of fFPH depends on the clock gear setting. (1) NMI , INT0 to INT5 interrupts Parameter NMI , INT0 to INT5 low level width Symbol tINTAL tINTAH Variable Min 4 X + 40 4 X + 40 36 MHz Min 150 150 Max Max Unit ns ns NMI , INT0 to INT5 high level width 91C630-176 2005-11-15 TMP91C630 4.8 Bus Request/Bus Acknowledge BUSRQ (Note 1) BUSAK tCBAL tBAA D0 to D15 A0 to A23, RD , WR CS0 to CS3 , HWR tABA (Note 2) (Note 2) Parameter Output buffer to BUSAK low BUSAK high to output buffer on Symbol tABA tBAA Variable Min 0 0 fFPH = 36 MHz Min 0 0 Unit ns ns Max 80 80 Max 80 80 Note 1: Even if the BUSRQ signal goes Low, the bus will not be released while the WAIT signal is Low. The bus will only be released when BUSRQ goes Low while WAIT is High. Note 2: This line shows only that the output buffer is in the Off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the Active and Non-Active states by the internal signal. 91C630-177 2005-11-15 TMP91C630 5. Table of SFRs (SFR; special function register) The SFRs include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) Chip select/wait control (5) Clock gear (6) 8-bit timer (7) 16-bit timer (8) UART/Serial channel (9) AD converter (10) Watchdog timer (11) Multi vector control Table layout Symbol Name Address 7 6 1 0 Bit symbol Read/Write Initial value after reset Remarks Note: “Prohibit RMW” in the a table means that you cannot use RMW instructions on these register. Example: When setting bit 0 only of the register PxCR, the instruction “SET 0, (PxCR)” cannot be used. The LD (transfer) instruction must be used to write all eight bits. Read/Write R/W: Both read and write are possible. R: Only read is possible. W: Only write is possible. W*: Both read and write are possible (when this bit is read as 1) Prohibit RMW: Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are read-modify-write instructions.) R/W*: Read-modify-write is prohibited when controlling the pull-up resistor. 91C630-178 2005-11-15 TMP91C630 Table 5.1 Address Map SFRs [1] Port Address 0000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P1 Name Address 0010H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P5CR P5FC P6 P7 P6FC P7CR P7FC P8 P9 P8CR P8FC P9CR P9FC PA Name Address 0020H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH ODE Name P1CR P2 P2FC P5 Address 0070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH PZ EH PZCR FH PZFC Name [2] INTC Address 0080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name DMA0V DMA1V DMA2V DMA3V Address 0090H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name INTE0AD INTE12 INTE34 INTE5 INTETA01 INTETA23 INTETA45 INTETB0 INTETBOV INTES0 INTES1 Address 00A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name INTETC01 INTETC23 INTCLR DMAR DMAB IIMC0 IIMC1 MVEC0 MVEC1 Note: Do not access to the unnamed addresses, i.e. addresses to which no register has been allocated. 91C630-179 2005-11-15 TMP91C630 [3] CS/WAIT Address 00C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH B0CS B1CS B2CS B3CS Name [4] CGEAR, DFM Address 00E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name SYSCR0 SYSCR1 SYSCR2 EMCCR0 EMCCR1 BEXCS MSAR0 MAMR0 MSAR1 MAMR1 MSAR2 MAMR2 MSAR3 MAMR3 [5] TMRA Address 0100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name TA01RUN TA0REG TA1REG TA01MOD TA1FFCR Address 0110H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name TA45RUN TA4REG TA5REG TA45MOD TA5FFCR TA23RUN TA2REG TA3REG TA23MOD TA3FFCR Note: Do not access to the unnamed addresses, i.e. addresses to which no register has been allocated. 91C630-180 2005-11-15 TMP91C630 [6] TMRB0 Address 0180H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH TB0RUN TB0MOD TB0FFCR Name [7] UART/SIO Address 0200H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name SC0BUF SC0CR SC0MOD0 BR0CR BR0ADD SC0MOD1 TB0RG0L TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H TB0CP1L TB0CP1H SC1BUF SC1CR SC1MOD0 BR1CR BR1ADD SC1MOD1 [8] 10-bit ADC Address 02A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name ADREG04L ADREG04H ADREG15L ADREG15H ADREG26L ADREG26H ADREG37L ADREG37H Address 02B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name ADMOD0 ADMOD1 Note: Do not access to the unnamed addresses i.e. addresses to which no register has been allocated. [9] WDT Address 0300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name WDMOD WDCR Note: Do not access to the unnamed addresses, i.e. addresses to which no register has been allocated. 91C630-181 2005-11-15 TMP91C630 (1) I/O port Symbol P1 Name Port 1 Address 01H P27 P2 Port 2 06H 1 1 P56 P5 Port 5 0DH 1 P55 R/W Data from external port (Output latch register is set to 1) 7 P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is clear to 0) P26 P25 P24 R/W 1 P54 1 P53 1 1 1 P23 P22 P21 P20 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON P63 P6 Port 6 12H 1 P75 P7 Port 7 13H P87 P8 Port 8 18H P86 P85 P84 R/W Data from external port (Output latch register is set to 1) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON P96 P9 Port 9 19H Data from external port (Output latch register is set to 1) PA7 PA Port A 1EH PA6 PA5 PA4 R Data from external port PZ3 R/W Data from external port (Output latch register is set to 1) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON PZ2 PA3 PA2 PA1 P95 R/W P94 P93 P90 R/W Data from external port (Output latch register is set to 1) P62 R/W 0 P72 R/W P61 1 P71 P60 1 P70 P74 P73 Data from external port (Output latch register is set to 1) P83 P82 P81 P80 PA0 PZ Port Z 7DH 91C630-182 2005-11-15 TMP91C630 (2) I/O port control (1/2) Symbol P1CR Name Address 7 P17C Port 1 control 04H (Prohibit RMW) P27F P2FC Port 2 function 09H (Prohibit RMW) P56C P5CR Port 5 control 10H (Prohibit RMW) P56F P5FC Port 5 function 11H (Prohibit RMW) P6FC Port 6 function 15H (Prohibit RMW) P75C P7CR Port 7 control 16H (Prohibit RMW) P72F2 P7FC Port 7 function 17H (Prohibit RMW) 1AH P8CR Port 8 control (Prohibit RMW) P87C 0 P87F W 0 (Prohibit 0: Port RMW) 1: STS1 W 0 0: Port 1: INT2 P86C 0 P86F W 0 0: Port 1: SCLK1 P75F W 0 0: Port 1: INT4 P85C 0 P74F W 0 0: Port P84C W 0 0: In P84F W 0 0: Port 1: TXD1 0 1: Out P83F W 0 0: Port 1: STS0 P82F W 0 0: Port 1: SCLK0 P80F W 0 0: Port 1: TXD0 0 0 0 P73F W 0 0: Port P83C 0 0 0 0: In P74C 0 0: Port 1: CS3 P73C W 0 1: Out P72F1 W 0 0: Port P82C P71F W 0 0: Port P81C P70F W 0 0: Port P80C 0 0 0 0: Port 1: CS2 P72C W 0 0: Port 1: INT0 0 0: Port 1: BUSAK 0 0 0: In 1 1 1 P55C W 0 1: Out P54F W 0 0: Port 1: BUSRQ P63F P62F W 0 0: Port 1: CS1 P71C 0 0: Port 1: CS0 P70C P61F P60F P53F 0 1 P54C P26F P25F 0 0 0 0 0: In P24F W 1 P53C 1 1 1 0: Port, 1: Address bus (A23 to A16) 6 P16C 5 P15C 4 P14C W 0 1: Out P23F P22F P21F P20F 0 0 0 3 P13C 2 P12C 1 P11C 0 P10C 1: TA5OUT 1: INT3 1: TA3OUT 1: TA1OUT 1: INT1 P8FC Port 8 function 1BH 91C630-183 2005-11-15 TMP91C630 I/O port control (2/2) Symbol Name Address 7 6 P96C P9CR Port 9 control 1CH (Prohibit RMW) P96F P9FC Port 9 function 1DH (Prohibit RMW) W 0 0: Port 5 P95C W 0 0: In P95F W 0 0: Port 4 P94C 0 1: Out 3 P93C 0 2 1 0 P90C W 0 0: In 1:Out P90F W 0 0: Port 1: INT5 0 1: TB0OUT1 1: TB0OUT0 PZ3C PZCR Port Z control 7EH (Prohibit RMW) 0 0: In W PZ2C 0 1: Out PZ2F W 0 0: Port 1: HWR PZFC Port Z function 7FH (Prohibit RMW) ODE84 ODE80 W 0 1: P80ODE ODE 2FH Serial open drain (Prohibit RMW) W 0 1: P84ODE 91C630-184 2005-11-15 TMP91C630 (3) Interrupt control (1/3) Symbol Name Address 7 IADC 90H R 0 1: INTAD I2C 91H R 0 1: INT2 I4C 92H R 0 1: INT4 – 93H – – – – 0 – INTE5 INT5 enable – – – Always write “0” INTTA1 (TMRA1) INTTA0 & INTETA01 INTTA1 enable ITA1C 95H R 0 1: INTTA1 ITA3C 96H R 0 1: INTTA3 ITA5C 97H R 0 1: INTTA5 ITB01C 99H R 0 1: INTTB01 INTTBOF0 INTETBOV enable (Over flow) – 9BH – – – – 0 – – – – Always write “0” – – ITF0C R 0 1: INTTBOF0 6 INTAD IADM2 0 INT2 5 IADM1 R/W 0 Interrpt request level 4 IADM0 0 3 I0C R 0 1: INT0 I1C R 0 1: INT1 I3C R 0 1: INT3 2 INT0 I0M2 0 INT1 1 I0M1 R/W 0 Interrpt request level 0 I0M0 0 INT0 & INTE0AD INTAD enable INTE12 INT1 & INT2 enable I2M2 0 INT4 I2M1 R/W 0 I2M0 0 I1M2 0 INT3 I1M1 R/W 0 I1M0 0 Interrupt request level I4M2 I4M1 R/W 0 Interrupt request level – – 0 I4M0 Interrpt request level I3M2 0 INT5 I3M1 R/W 0 Interrpt request level I5M2 0 I5M1 R/W 0 Interrpt request level INTTA0 (TMRA0) ITA0M2 0 ITA0M1 R/W 0 Interrpt request level INTTA2 (TMRA2) ITA2M2 0 ITA2M1 R/W 0 Interrpt request level INTTA4 (TMRA4) ITA4M2 0 ITA4M1 R/W 0 Interrpt request level INTTB00 (TMRB0) ITB00M2 0 ITB00M1 R/W 0 Interrpt request level ITF0M2 0 ITF0M1 R/W 0 Interrpt request level 0 ITF0M0 0 ITB00M0 0 ITA4M0 0 ITA2M0 0 ITA0M0 0 I5M0 0 I3M0 INTE34 INT3 & INT4 enable I5C R 0 1: INT5 ITA1M2 0 ITA1M1 R/W 0 ITA1M0 0 ITA0C R 0 1: INTTA0 ITA2C R 0 1: INTTA2 ITA4C R 0 1: INTTA4 ITB00C R 0 1: INTTB00 Interrpt request level INTTA3 (TMRA3) ITA3M2 0 ITA3M1 R/W 0 Interrpt request level INTTA5 (TMRA5) ITA5M2 0 ITA5M1 R/W 0 Interrpt request level INTTB01 (TMRB0) ITB01M2 ITB01M1 R/W 0 Interrpt request level 0 ITB01M0 0 ITA5M0 0 ITA3M0 INTTA2 & INTETA23 INTTA3 enable INTTA4 & INTETA45 INTTA5 enable INTTC00 & INTETB0 INTTB01 enable INTTBOF0 (TMRB0 overflow) 91C630-185 2005-11-15 TMP91C630 Interrupt control (2/3) Symbol Name Address 7 ITX0C 9CH R 0 1: INTTX0 ITX1C 9DH R 0 1: INTTX1 INTTC0& INTETC01 INTTC1 enable ITC1C R 0 INTTC2& INTETC23 INTTC3 enable ITC3C R 0 0 0 INTTC3 A1H ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 0 0 INTTC1 A0H ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 0 INTTC2 ITC2M2 ITC2M1 R/W 0 0 ITC2M0 0 INTTX1 INTES1 INTRX1 & INTTX1 enable ITX1M2 ITX1M1 R/W 0 Interrpt request level 0 ITX1M0 IRX1C R 0 1: INTRX1 0 INTTC0 ITC0M2 ITC0M1 R/W 0 0 ITC0M0 6 INTTX0 INTES0 INTRX0 & INTTX0 enable ITX0M2 ITX0M1 R/W 0 Interrpt request level 0 ITX0M0 IRX0C R 0 1: INTRX0 0 INTRX1 IRX1M2 IRX1M1 R/W 0 Interrpt request level 0 IRX1M0 5 4 3 2 INTRX0 IRX0M2 IRX0M1 R/W 0 Interrpt request level 0 IRX0M0 1 0 91C630-186 2005-11-15 TMP91C630 Interrupt control (3/3) Symbol Name DMA0 DMA0V start vector Address 80H (Prohibit RMW) 7 6 5 DMA0V5 0 DMA1V5 0 DMA2V5 0 DMA3V5 0 CLRV5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 CLRV4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 CLRV3 W 0 DMAR3 R/W 0 DMAB3 8AH R/W 0 – W Interrupt IIMC0 input mode control 0 8CH 0 (Prohibit Always RMW) write 0 I2EDGE W 0 INT2 edge 0: Rising 1: Falling – Interrupt IIMC1 input mode control 1 W 8DH 0 INT5 edge 0: Rising 1: Falling (Prohibit Always RMW) write 0 INT2 0: Edge 1: Level I2LE W 0 I1EDGE W 0 INT1 edge 0: Rising 1: Falling INT1 0: Edge 1: Level I1LE W 0 0 DMAR2 R/W 0 DMAB2 R/W 0 I0EDGE W 0 INT0 edge 0: Rising 1: Falling INT0 0: Edge 1: Level 0 DMAR1 R/W 0 DMAB1 R/W 0 I0LE W 0 0 DMAR0 R/W 0 DMAB0 R/W 0 NMIREE W 0 1: NMI operation even on NMI rising edge Clear interrupt request DMA flag by writing to DMA start vector 89H (Prohibit RMW) R/W 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 CLRV2 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 CLRV1 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 CLRV0 DMA0 start vector 81H (Prohibit RMW) R/W DMA1 start vector 82H (Prohibit RMW) R/W DMA2 start vector 83H (Prohibit RMW) R/W DMA3 start vector 88H (Prohibit RMW) 2 DMA0V2 1 DMA0V1 0 DMA0V0 DMA1 DMA1V start vector DMA2 DMA2V start vector DMA3 DMA3V start vector Interrupt INTCLR clear control DMA DMAR software request register DMA DMAB burst request register 1: DMA request in software (Note) 1 : DMA request on burst mode I5EDGE W 0 I5LE W 0 INT5 0: Edge 1: Level I4EDGE W 0 INT4 edge 0: Rising 1: Falling I4LE W 0 INT4 0: Edge 1: Level I3EDGE W 0 INT3 edge 0: Rising 1: Falling I3LE W 0 INT3 0: Edge 1: Level Note: Only one-channel can be set once for DMAR register. (Don’t write “1” to plural bits.) 91C630-187 2005-11-15 TMP91C630 (4) Chip select/Wait control (1/2) Symbol Name Address 7 B0E Block 0 CS/WAIT control register C0H W 0 (Prohibit 0: Disable RMW) 1: Enable 6 5 B00M1 W 0 00: ROM/SRAM 01: 10: Reserved 11: B10M1 W 0 00: ROM/SRAM 01: 10: Reserved 11: B2M W 0 B20M1 W B20M0 W B10M0 W 0 4 B00M0 W 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B2BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits BEXBUS External CS/WAIT control register C7H (Prohibit RMW) W 0 Data bus width 0: 16 bits 1: 8 bits S23 C8H 1 1 1 1 S22 S21 S20 R/W 1 1 1 1 S19 2 B0W2 W 0 1 B0W1 W 0 0 B0W0 W 0 B0CS 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B1W2 W B1W1 W B1W0 W B1E Block 1 CS/WAIT control register C1H W 0 (Prohibit 0: Disable RMW) 1: Enable B1CS 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B2W2 W B2W1 W B2W0 W B2E Block 2 CS/WAIT control register C2H W 1 (Prohibit 0: Disable RMW) 1: Enable B2CS 0 0 00: ROM/SRAM 0: 16-MB 01: area 1: CS area 10: Reserved 11: B30M1 W 0 00: ROM/SRAM 01: 10: Reserved 11: B30M0 W 0 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B3W2 W B3W1 W B3W0 W B3E Block 3 CS/WAIT control register C3H W 0 (Prohibit 0: Disable RMW) 1: Enable B3CS 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits BEXW2 W BEXW1 W BEXW0 W BEXCS 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits S18 S17 S16 MSAR0 Memory start address register 0 Start address A23 to A16 V20 C9H 1 1 1 CS0 area size S23 CAH 1 1 1 1 S22 S21 1 V19 V18 V17 R/W 1 1 1 1 V16 V15 V14~9 V8 Memory address MAMR0 mask register 0 Memory start address register 1 0: Enable to address comparision S20 R/W 1 1 1 1 S19 S18 S17 S16 MSAR1 Stat address A23 to A16 V21 CBH 1 1 1 CS1 area size 1 V20 V19 V18 R/W 1 1 1 V17 V16 V15~9 V8 Memory address MAMR1 mask register 1 0: Enable to address comparsion 91C630-188 2005-11-15 TMP91C630 Chip select /Wait control (2/2) Symbol Name Memory start address register 2 Address 7 S23 CCH 1 1 1 1 6 S22 5 S21 4 S20 R/W 1 1 1 1 3 S19 2 S18 1 S17 0 S16 MSAR2 Start address A23 to A16 V22 CDH 1 1 1 CS2 area size S23 CEH 1 1 1 1 S22 S21 1 V21 V20 V19 R/W 1 1 1 1 V18 V17 V16 V15 Memory address MAMR2 mask register 2 Memory start address register 3 0: Enable address comparsion S20 R/W 1 1 1 1 S19 S18 S17 S16 MSAR3 Start address A23 to A16 V22 CFH 1 1 1 CS3 area size 1 V21 V20 V19 R/W 1 1 1 1 V18 V17 V16 V15 Memory address MAMR3 mask register 3 0: Enable to address comparsion 91C630-189 2005-11-15 TMP91C630 (5) Clock gear Symbol Name Address 7 − SYSCR0 System clock control register 0 E0H 1 Always write 1 0 Always write 0 1 Always write 1 0 Always write 0 6 − 5 − 4 − R/W 0 Always write 0 0 Always write 0 0 00: fFPH 01: Reserved 10: fc/16 11: Reserved − SYSCR1 System clock control register 1 E1H 0 Always write 0 1 GEAR2 R/W 0 0 High-frequency gear value selection (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) − SYSCR2 System clock control register 2 E2H R/W 0 Always write 0 WUPTM1 R/W 1 Warming-up time 00: Reserved 01: 2 /input frequency 10: 2 /input frequency 11: 2 /input frequency PROTECT EMCCR0 EMC control register 0 E3H R 0 Protection flag 0: OFF 1: ON EMC EMCCR1 control register 1 Protection is turned OFF by writing 1FH. E4H Protection is turned ON by writing any value other than 1FH. − R/W 0 Always write 0 − R/W 1 Always write 1 − R/W 0 Always write 0 16 14 8 3 − 2 − 1 PRCK1 0 PRCK0 0 Prscaler clock seleciton GEAR1 GEAR0 WUPTM0 R/W 0 HALTM1 R/W 1 HALT mode 00: Reserved HALTM0 R/W 1 DRVE R/W 0 1: Drive the pin in STOP mode − R/W 1 − R/W 1 Always write 1 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode − R/W 0 Always wirte 0 EXTIN R/W 0 01: fc is Always external write 1 clock. Note: EMCCR1 If protection is on by writing except “1FH” code to EMCCR1 register, write operations to the following SFRs are not possible. 1. CS/WAIT control B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, and MAMR3 2. Clock gear (only EMCCR1 can be written to) SYSCR0, SYSCR1, SYSCR2 and EMCCR0 91C630-190 2005-11-15 TMP91C630 (6) 8-bit timer (1/3) (6−1) TMRA01 Symbol Name Address 7 TA0RDE R/W 0 100H Double buffer 0: Disable 1: Enable TA0REG TMRA0 register 0 TMRA1 register 1 102H (Prohibit RMW) 103H (Prohibit RMW) TA01M1 TMRA01 source CLK & MODE TA01M0 PWM01 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 − W Undefined − W Undefined PWM00 0 TA1CLK1 R/W TA1CLK0 TA0CLK1 TA0CLK0 6 5 4 3 I2TA01 R/W 0 IDLE2 0: Stop 2 1 0 TA0RUN R/W 0 TA01RUN TMRA01 RUN TA01PRUN TA1RUN R/W R/W 0 0 0: Stop & clear 8-bit timer run/stop control 1: Operate 1: Run (count up) TA1REG TA01MOD 104H 0 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 Source clock for TMRA1 00: TA0TRG 01: φT1 10: φT16 11: φT256 TA1FFC1 TA1FFC0 R/W 1 1 0 0 Source clock for TMRA0 00: TA0IN pin 01: φT1 10: φT4 11: φT16 TA1FFIE 0 1: TA1FF invert enable TA1FFIS R/W 0 0: TMRA0 1: TMRA1 inversion TA1FFCR TMRA01 flip-flop control 105H 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care 91C630-191 2005-11-15 TMP91C630 8-bit timer (2/3) (6−2) TMRA23 Symbol Name Address 7 TA2RDE R/W 0 108H Double buffer 0: Disable 1: Enable TA2REG TMRA2 register 0 TMRA3 register 1 10AH (Prohibit RMW) 10BH (Prohibit RMW) TA23M1 TMRA23 source TA23MOD CLK & MODE TA23M0 PWM21 − W Undefined − W Undefined PWM20 0 TA3CLK1 R/W TA3CLK0 TA2CLK1 TA2CLK0 6 5 4 3 I2TA23 R/W 0 IDLE2 0: Stop 2 1 0 TA2RUN R/W 0 TA23RUN TMRA23 RUN TA23PRUN TA3RUN R/W R/W 0 0 8-bit timer run/stop control 0: Stop & clear 1: Operate 1: Run (count up) TA3REG 10CH 0 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 0 0 Source clock for TMRA3 00: TA2TRG 01: φT1 10: φT16 11: φT256 TA3FFC1 TA3FFC0 R/W 1 1 0 0 Source clock for TMRA2 00: Reserved 01: φT1 10: φT4 11: φT16 TA3FFIE TA3FFIS R/W 0 0 1: TA3FF invert enable 0: TMRA2 1: TMRA3 inversion TA3FFCR TMRA23 flip-flop control 10DH 00: Invert TA3FF 01: Set TA3FF 10: Clear TA1FF 11: Don’t care 91C630-192 2005-11-15 TMP91C630 8-bit timer (3/3) (6-3) TMRA45 Symbol Name Address 7 TA4RDE R/W TA45RUN TMRA45 RUN 0 110H Double buffer 0: Disable 1: Enable TA4REG TMRA4 register 0 112H (Prohibit RMW) 113H (Prohibit RMW) TA45M1 0 114H Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM TA45M0 0 PWM41 0 PWM cycle 00: Reserved 01: 2 6 7 8 6 5 4 3 I2TA45 R/W 0 IDLE2 0: Stop 2 TA45PRUN R/W 0 0: Stop & clear 1 TA5RUN R/W 0 0 TA4RUN R/W 0 8-bit timer run/stop control 1: Operate 1: Run (count up) − W Undefined − W Undefined PWM40 0 TA5CLK1 R/W 0 00: TA4TRG 01: φT1 10: φT16 11: φT256 TA5FFC1 TA5FFC0 1 R/W TA5CLK0 0 TA4CLK1 0 00: TA4IN pin 01: φT1 10: φT4 11: φT16 TA5FFIE 0 1: TA5FF invert enable TA5FFIS 0 0: TMRA4 1: TMRA5 inversion R/W TA4CLK0 0 TA5REG TMRA5 register 1 TMRA45 source TA45MOD CLK & MODE Source clock for TMRA5 Source clock for TMRA4 10: 2 11: 2 TA5FFCR TMRA45 flip-flop control 1 115H 00: Invert TA5FF 01: SET TA5FF 10: Clear TA5FF 11: Don’t care 91C630-193 2005-11-15 TMP91C630 (7) 16-bit timer (7-1) TMRB0 Symbol Name Address 7 TB0RDE R/W 0 Double buffer 0: Disable 1: Enable TB0CT1 R/W 0 6 − R/W 0 Always write 0. 5 4 3 I2TB0 R/W 0 IDLE2 0: Stop 1: Operate 2 TB0PRUN 1 0 TB0RUN TB0RUN TMRB0 control 180H R/W R/W 0 0 16-bit timer run/stop control 0: Stop & clear 1: Run (count up) TB0CLE R/W 0 1: UC0 clear enable TB0CLK1 0 Source clock 00: TB0IN0 pin 01: φT1 10: φT4 11: φT16 TB0FF0C1 TB0FF0C0 W* 1 01: Set TB0FF0 10: Clear TB0FF0 1 00: Invert TB0FF0 TB0CLK0 0 TB0ET1 0 TB0CP0I W* 1 TB0CPM1 0 TB0CPM0 0 TB0MOD TMRB0 source CLK & MODE TB0FF1 inversion (Prohibit trigger RMW) 0: TRG disable 1: TRG enable Capture to TB0RG1 TB0CP1 matching TB0FF1C1 TB0FF1C0 W* 1 1 00: Invert TB0FF1 182H 0: Soft Capture timing capture 00: Disable 1: Undefined 01: ↑, ↑ (TB0IN0, TB0IN1) 10: ↑, ↓ (TB0IN0, TB0IN1) 11: ↑, ↓ (TA1OUT) TB0C0T1 0 TB0E1T1 0 TB0C1T1 0 TB0E0T1 0 R/W TB0FF0 invert trigger 0: Trigger disable 1: Trigger enable Invert when the UC value is loaded in to TB0CP1 Invert when the UC value is loaded in to TB0CP0 Invert when the UC value matches the value in TB0RG1 TB0FFCR TMRB0 flip-flop control 01: Set 183H (Prohibit 10: Clear RMW) 11: Don’t care Always read as 11 11: Don’t care Invert when the Always read as 11 UC value matches the value in TB0RG0 TB0RG0L TMRB0 register 0L 188H (Prohibit RMW) 189H (Prohibit RMW) 18AH (Prohibit RMW) 18BH (Prohibit RMW) 18CH − W Undefined − W Undefined − W Undefined − W Undefined − R Undefined − R Undefined − R Undefined − R Undefined TMRB0 TB0RG0H register 0H TB0RG1L TMRB0 register 1L TMRB0 TB0RG1H register 1H TB0CP0L Capture register 0L Capture register 0H Capture register 1L Capture register 1H TB0CP0H 18DH TB0CP1L 18EH TB0CP1H 18FH 91C630-194 2005-11-15 TMP91C630 (8) UART/Serial channel control (8-1) UART/SIO channel 0 Symbol SC0BUF Name Serial Address 200H 7 RB7/TB7 6 RB6/TB6 5 RB5/TB5 4 RB4/TB4 3 RB3/TB3 2 RB2/TB2 1 RB1/TB1 0 RB0/TB0 channel 0 (Prohibit RMW) buffer RB8 Serial R 201H Undefined Receiving data bit 8 TB8 0 202H Transfer data bit 8 0 Parity 0: Odd 1: Even CTSE 0 1: CTS enable 0: CTS disable − 0 203H Always write 0 EVEN R/W 0 1: Parity Enable RXE 0 PE R (receiving)/W (transmission) Undefined OERR 0 Over run WU R/W 0 PERR 0 1: Error Parity SM1 0 Framing SM0 0 FERR 0 SCLKS R/W 0 0 0:SCLK0↑ 1: Input 1:SCLK0↓ SCLK0 pin SC1 0 00: TA0TRG 01: Baud rate generator 10: Internal clock fSYS 11: External clock SCLK0 BR0S1 0 BR0S0 0 SC0 0 IOC R (cleared to 0 by reading) SC0CR channel 0 control Serial SC0MOD0 channel 0 mode 0 1: Receive 1: Wake-up 00: I/O interface enable enable 01: UART 7-bit 0: Receive 0: Wake-up 10: UART 8-bit disable disable 11: UART 9-bit BR0CK1 0 00: φT0 01: φT2 10: φT8 11: φT32 BR0K3 BR0K2 BR0CK0 R/W BR0S3 0 BR0S2 0 BR0ADD 0 1:(16 − K)/16 divided enable BR0CR Baud rate control Set of the Divided frequency BR0K1 R/W 0 BR0K0 0 BR0ADD Serial channel 0 K setting register 204H 0 0 Set frequency divisor K (divided by N + (16-K)/16) I2S0 FDPX0 R/W 0 Duplex 0: Half STSEN0 W 1 STS0 1: Disable 0: Enable R/W 205H 0 IDLE2 0: Stop Serial SC0MOD1 channel 0 mode 1 1: Operate 1: Full 91C630-195 2005-11-15 TMP91C630 (8-2) UART/SIO Channel 1 Symbol SC1BUF Name Serial channel 1 buffer Address 208H (Prohibit RMW) 7 RB7/TB7 6 RB6/TB6 5 RB5/TB5 4 RB4/TB4 3 RB3/TB3 2 RB2/TB2 1 RB1/TB1 0 RB0/TB0 R (receiving)/W (transmission) Undefined RB8 EVEN R/W 0 0 Parity 0: Disable 1: Enable RXE 0 WU R/W 0 SM1 0 SM0 0 SC1 0 00: TA0TRG 01: Baud rate generator 10: Internal clock fSYS 11: External clock SCLK1 BR1S1 0 BR1S0 0 SC0 0 Over run PE OERR 0 PERR 0 1: Error Parity Framing FERR 0 SCLKS R/W 0 0 0:SCLK1↑ 1: Input 1:SCLK1↓ SCLK1 pin IOC R R (cleared to 0 by reading) Serial SC1CR channel 1 control 209H Undefined Receiving Parity data bit 8 0: Odd 1: Even TB8 CTSE 0 1: CTS enable Serial 0 20AH Transfer data bit 8 SC1MOD0 channel 1 mode 0 1: Receive 1: Wake-up 00: I/O interface enable enable 01: UART 7-bit 10: UART 8-bit 11: UART 9-bit − 0 20BH Always write 0 BR1ADD 0 BR1CK1 0 BR1CK0 R/W BR1S3 0 BR1S2 0 BR1CR Baud rate control 1: (16 − K)/16 00: φT0 divided 01: φT2 enable 10: φT8 Set of the Divided frequency F 11: φT32 BR1K3 BR1ADD Serial channel 1 K setting register BR1K2 R/W 0 BR1K1 0 BR1K0 0 20CH 0 Set frequency divisor K (divided by N + (16-K)/16) I2S1 FDPX1 R/W 0 Duplex 0: Half STSEN1 W 1 STS1 1: Disable 0: Enable R/W 20DH 0 IDLE2 0: Stop Serial SC1MOD1 channel 1 mode 1 1: Operate 1: Full 91C630-196 2005-11-15 TMP91C630 (9) AD converter Symbol Name Address 7 EOCF R AD ADMOD0 MODE register 0 2B0H 0 0 6 ADBF 5 − R/W 0 4 − R/W 0 Always write 0 3 ITM0 R/W 0 Interrupt in repeat mode ADTRGE R/W 0 External trigger start 0: Disable 1: Enable 0 2 REPEAT R/W 0 1 SCAN R/W 0 0 ADS R/W 0 AD conversion start 1: Start AD AD Always conversion conversion write 0 end flag bust flag 1: End VREFON R/W 0 VREF 0: Off 1: Busy I2AD R/W 0 IDLE2 0: Stop 1: Operation Repeat Scan mode mode Specification specification 1: Scan 1: Repeat ADCH2 ADCH1 R/W 0 ADCH0 0 Input channel selection fixed/scan 000: AN0 AN0 001: AN1 AN0 →AN1 010: AN2 AN0 → AN1 → AN2 011: AN3 AN0 → AN1 → AN2 → AN3 100: AN4 AN4 101: AN5 AN4 →AN5 110: AN6 AN4 → AN5 → AN6 111: AN7 AN4 → AN5 → AN6 → AN7 AD ADMOD1 MODE register 1 2B1H 1: On ADREG04L AD result register 0/4 Low AD result ADR01 2A0H ADR09 2A1H ADR11 2A2H ADR19 2A3H ADR21 2A4H ADR29 2A5H ADR31 2A6H ADR39 2A7H R R R R ADR00 ADR0RF R 0 ADR07 ADR06 R Undefined ADR05 ADR04 ADR03 ADR02 Undefined ADR08 ADREG04H register 0/4 High AD result register 1/5 Low AD result ADREG15H register ADR10 ADR1RF R 0 ADR17 ADR16 R Undefined ADR15 ADR14 ADR13 ADR12 ADREG15L Undefined ADR18 1/5 High AD result register 2/6 Low AD result ADREG26H register ADR20 ADR2RF R 0 ADR27 ADR26 R Undefined ADR25 ADR24 ADR23 ADR22 ADREG26L Undefined ADR28 2/6 High AD result register 3/7 Low AD result ADREG37H register ADR30 ADR3RF R 0 ADR37 ADR36 R Undefined ADR35 ADR34 ADR33 ADR32 ADREG37L Undefined ADR38 3/7 High Note: 1. ADMOD0 is always read as “0”. 2. When using ADTRG with ADMOD1 = “1”, do not set ADMOD1 = “011”. 3. When clear ADMOD1 to “0”, operation is different by AD conversion mode after released Halt mode. 91C630-197 2005-11-15 TMP91C630 (10) Watchdog timer control Symbol Name Address 7 WDTE R/W 1 WDT WDMOD MODE register 300H 1: WDT enable 6 WDTP1 R/W 0 00: 2 /fSYS 01: 2 /fSYS 10: 2 /fSYS 11: 2 /fSYS 21 19 17 15 5 WDTP0 R/W 0 4 − R/W 0 Always write 0 3 − R/W 0 Always write 0 2 I2WDT R/W 0 IDLE2 0: STOP 1 RESCR R/W 0 0 − R/W 0 Always write 0 1: Internally connects 1: Operate WDT out to the Reset pin − WDCR WDT control 301H W − B1H: WDT disable 4EH: WDT clear (11) Multi vector control Symbol Name Multi MVEC0 vector control 00AEH Address 7 VEC7 R/W 1 6 VEC6 R/W 1 5 VEC5 R/W 1 4 VEC4 R/W 1 3 VEC3 R/W 1 2 VEC2 R/W 1 1 VEC1 R/W 1 0 VEC0 R/W 1 Vector address A15 to A8 Symbol Name Multi Address 7 VEC15 R/W 1 6 VEC14 R/W 1 5 VEC13 R/W 1 4 VEC12 R/W 1 3 VEC11 R/W 1 2 VEC10 R/W 1 1 VEC9 R/W 1 0 VEC8 R/W 1 MVEC1 vector control 00AFH Vector address A23 to A16 Note: Write MVEC1 and MVEC0 after making an interruption prohibition state. 91C630-198 2005-11-15 TMP91C630 6. Port Section Equivalent Circuit Diagrams • Reading the circuit diagrams The gate symbols used are essentially the same as those used for the standard CMOS logic IC [74HCXX] Series. The dedicated signal is described below. STOP: This signal becomes Active (1) when the Halt mode setting register is set to STOP mode (i.e. when SYSCR2 = 0, 1) and the CPU executes the HALT instruction. When the drive enable bit SYSCR2 is set to 1, however, STOP will remains at 0. • The input protection resistances range from several tens of ohms to several hundreds of ohms. D0 to D7, P10 to P17 (D8 to D15), P71, P74, P93 to P96 VCC Output data Output enable Stop Input data P-channel N-channel I/O ■ Input enable ■ A0 to A15, P20 to P27 (A16 to A23), RD , WR , P60 to P63 VCC Output data Output Stop ■ P53 to P55, P81 to P83, P85 to P87, PZ2, PZ3 VCC Output VCC Output enable Stop Input data Programmable pull-up resistance I/O Input enable 91C630-199 2005-11-15 TMP91C630 ■ PA0 to PA7 (AN0 to AN7) Analog input Channel select Analog input Input Input data Input enable ■ P56 (INT0) VCC Output data Output enable Stop Input data Schmitt VCC Programmable pull-up resistance I/O ■ P70 (INT1), P72 (INT2), P73 (INT3), P75 (INT4) and P90 (INT5) VCC Output data Output enable Stop Input data Schmitt I/O ■ P80 (TXD0) and P84 (TXD1) VCC Output data Open-drain output enable Stop Input data Input enable VCC Programmable pull-up resistance I/O ■ NMI NMI Schmitt Input 91C630-200 2005-11-15 TMP91C630 ■ AM0 to AM1 Input data Input ■ BOOT VCC P-channel BOOT Input Schmitt ■ RESET VCC P-channel Reset Schmitt WDTOUT Reset enable Input ■ X1 and X2 Oscillator X2 High-frequency oscillation enable P-channel N-channel X1 Clock ■ VREFH and VREFL VREFON P-channel VREFH String resistance VREFL 91C630-201 2005-11-15 TMP91C630 7. Points to Note and Restrictions (1) Notation a. b. The notation for built-in/I/O registers is as follows register symbol e.g.) TA01RUN denotes bit TA0RUN of register TA01RUN. Read-modify-write instructions An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. Example 1) Example 2) • SET 3, (TA01RUN) INC 1, (100H) Set bit 3 of TA01RUN. Increment the data at 100H. Examples of read-modify-write instructions on the TLCS-900 Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# ADC SUB (mem), R/# SBC INC #3, (mem) DEC Logic operations AND (mem), R/# OR XOR (mem), R/# (mem), R/# (mem), R/# (mem), R/# #3, (mem) Bit manipulation operations STCF #3/A, (mem) RES #3, (mem) SET #3, (mem) CHG #3, (mem) TSET #3, (mem) Rotate and shift operations RLC RL SLA SLL RLD c. (mem) (mem) (mem) (mem) (mem) RRC RR SRA SRL RRD (mem) (mem) (mem) (mem) (mem) fOSCH, fc, fFPH, fSYS and one state The clock frequency input on pin X1 and X2 is called fOSCH. TMP91C630 have not DFM. Therefore, fc equal fOSCH. The clock selected by SYSCR1 is called fFPH. The clock frequency give by fFPH divided by 2 is called fSYS. One cycle of fSYS is referred to as one state. 91C630-202 2005-11-15 TMP91C630 (2) Points to note a. AM0 and AM1 pins Those pins are connected to the VCC or VSS pin Do not alter the voltage level of those pins when theTMP91C630 is processing b. c. d. EMU0and EMU1 Open pins. Reserved address areas The TMP91C630 has not any reserved areas. Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request and output of the system clock. e. Programmable pull-up resistance The programmable pull-up resistor can be turned ON/OFF by a program when the ports are set for use as input ports. When the ports are set for use as output ports, they cannot be turned ON/OFF by a program. The data registers (e.g. P8) are used to turn the pull-up/-down resistors ON/OFF. Consequently read-modify-write instructions are prohibited. f. Bus releasing function Please refer to the Note about bus release in Section 3.5, Functions of Ports. The pin state is written when the bus is released. g. Watchdog timer The watchdog timer starts operation immediately after a Reset is released. When the watchdog timer is not to be used, disable it. h. Watchdog timer When the bus is released, neither internal memory nor internal I/O can be accessed. However, the internal I/O continues to operate. Hence the watchdog timer continues to run. Therefore be careful about the bus releasing time and set the detection timer of watchdog timer. i. AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption. When STOP mode is used, disable the resistor using the program before the HALT instruction is executed. j. CPU (micro DMA) Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers in the CPU (e.g. the Transfer Source Address Register (DMASn)). k. l. Undefined SFR The value of an undefined bit in an SFR is undefined when read. POP SR instruction Please execute the POP SR instruction during DI condition. 91C630-203 2005-11-15 TMP91C630 8. Diversity of TMP91C630 and TMP91C829 TMP91C630 is based on TMP91C829, the significant different points of TMP91C630 and TMP91C829 are shown below. Because power supply is different, the electrical characteristics specification is changed, please refer to Chapter 4. Electrical characteristics. The significant different points of TMP91C630 and TMP91C829: (1) Power Supply TMP91C630 needs only 3-V power supply. TMP91C829 needs two power supplies (3 V and 5 V) (2) Internal RAM TMP91C630 built in RAM size is 6 Kbytes TMP91C829 built in RAM size is 8 Kbytes (3) AD conversion time TMP91C630 AD conversion time is 84 states TMP91C829 AD conversion time is 202 states 91C630-204 2005-11-15 TMP91C630 9. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 91C630-205 2005-11-15 TMP91C630 91C630-206 2005-11-15