POWER DRIVER FOR STEPPER MOTORS
INTEGRATED CIRCUITS
TMC2130-LA DATASHEET
Universal high voltage driver for two-phase bipolar stepper motor. stealthChop™ for quiet
movement. Integrated MOSFETs for up to 2.0A motor current per coil. With Step/Dir Interface and SPI.
APPLICATIONS
Textile, Sewing Machines
Factory & Lab Automation
3D printers
Liquid Handling
Medical
Office Automation
CCTV, Security
ATM, Cash recycler
POS
Pumps and Valves
FEATURES
AND
DESCRIPTION
BENEFITS
The TMC2130 is a high performance driver
IC for two phase stepper motors. Standard
SPI and STEP/DIR simplify communication.
TRINAMICs
sophisticated
stealthChop
chopper ensures noiseless operation
combined with maximum efficiency and
best motor torque. coolStep allows
reducing energy consumption by up to
75%. dcStep drives high loads as fast as
possible without step loss. Integrated
power MOSFETs handle motor currents up
to 1.2A RMS (QFN package) / 1.4A RMS
(TQFP) or 2.5A short time peak current per
coil. Protection and diagnostic features
support robust and reliable operation.
Industries’ most advanced stepper motor
driver enables miniaturized designs with
low external component count for costeffective and highly competitive solutions.
2-phase stepper motors up to 2.0A coil current (2.5A peak)
Step/Dir Interface with microstep interpolation microPlyer™
SPI Interface
Voltage Range 4.75… 46V DC
Highest Resolution 256 microsteps per full step
stealthChop™ for extremely quiet operation and smooth
motion
spreadCycle™ highly dynamic motor control chopper
dcStep™ load dependent speed control
stallGuard2™ high precision sensorless motor load detection
coolStep™ current control for energy savings up to 75%
Integrated Current Sense Option
Passive Braking and freewheeling mode
Full Protection & Diagnostics
Small Size 5x6mm2 QFN36 package or TQFP48 package
BLOCK DIAGRAM
Step/Dir
Power
Supply
+5V Regulator
INT
Interrupt
IREF optional current scaling
Charge
Pump
TMC2130
Step Multiplyer
Standstill Current
Reduction
DAC Reference
Motor
SPI
CLK
SPI Control,
Config & Diags
Control
Register
Set
CLK Oscillator /
Selector
spreadCycle
Programmable
256 µStep
Sequencer
DRIVER
stealthChop
Protection
& Diagnostics
stallGuard2
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
coolStep
dcStep
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
2
APPLICATION EXAMPLES: HIGH VOLTAGE – MULTIPURPOSE USE
The TMC2130 scores with power density, integrated power MOSFETs, and a versatility that covers a
wide spectrum of applications from battery systems up to embedded applications with 2.0A motor
current per coil. Based on stallGuard2, coolStep, dcStep, spreadCycle, and stealthChop, the TMC2130
optimizes drive performance and keeps costs down. It considers velocity vs. motor load, realizes
energy savings, smoothness of the drive and noiselessness. Extensive support at the chip, board, and
software levels enables rapid design cycles and fast time-to-market with competitive products.
MINIATURIZED DESIGN
FOR ONE
STEPPER MOTOR
In this application, the CPU initializes the
TMC2130 motor driver via SPI interface and
controls motor movement by sending step
and direction signals. A real time software
realizes motion control.
0A+
High-Level
Interface
CPU
S/D
TMC2130
FOR
N
0B+
0B-
SPI
DESIGN
S
0A-
DEMANDING APPLICATIONS
WITH
S-SHAPED RAMP PROFILES
0A+
High-Level
Interface
CPU
SPI
TMC4361
SPI
Motion
Controller
S/D
TMC2130
0A-
S
N
0B+
0B-
SPI
COMPACT DESIGN
FOR UP TO
THREE STEPPER MOTORS
0A+
High-Level
Interface
CPU
SPI
TMC429
Motion
Controller
STEP/
DIR
TMC2130
0A-
S
N
0B+
0B-
SPI
STEP/
DIR
0A+
TMC2130
0A-
S
The CPU initializes the TMC4361 motion
controller and the TMC2130. Thereafter, it
sends target positions to the TMC4361. Now,
the TMC4361 takes control over the TMC2130.
Combining the TMC4361 and the TMC2130
offers diverse possibilities for demanding
applications including servo drive features.
Here, an application with up to three stepper
motors is shown. A single CPU combined
with a TMC429 motion controller manages
the whole stepper motor driver system. This
design is highly economical and space
saving if more than one stepper motor is
needed.
N
0B+
0BSPI
STEP/
DIR
0A+
TMC2130
0A-
S
N
0B+
0BSPI
ORDER CODES
Order code
TMC2130-LA
TMC2130-TA
TMC2130-EVAL
TMC4361-EVAL
STARTRAMPE
ESELSBRÜCKE
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Description
1-axis dcStep, coolStep, and stealthChop driver; QFN36
1-axis dcStep, coolStep, and stealthChop driver; TQFP48
Evaluation board for TMC2130 two phase stepper motor
controller/driver
Motion controller board (part of evaluation board system)
Baseboard for TMC2130-EVAL and further evaluation boards
Connector board for plug-in evaluation board system
Size [mm2]
5x6
9x9
85 x 55
85 x 55
85 x 55
61 x 38
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
3
Table of Contents
1
2
PRINCIPLES OF OPERATION ......................... 5
8
ANALOG CURRENT CONTROL AIN ............. 54
1.1
KEY CONCEPTS ................................................ 7
1.2
SPI CONTROL INTERFACE ............................... 7
1.3
SOFTWARE ...................................................... 7
1.4
MOVING THE MOTOR ...................................... 7
1.5
STEALTHCHOP DRIVER ..................................... 8
1.6
STALLGUARD2 – MECHANICAL LOAD SENSING8
1.7
COOLSTEP – LOAD ADAPTIVE CURRENT
CONTROL ...................................................................... 8
1.8
DCSTEP – LOAD DEPENDENT SPEED CONTROL 9
9
SELECTING SENSE RESISTORS.................... 55
PIN ASSIGNMENTS .........................................10
2.1
2.2
3
PACKAGE OUTLINE ........................................10
SIGNAL DESCRIPTIONS .................................11
SAMPLE CIRCUITS ..........................................13
3.1
STANDARD APPLICATION CIRCUIT ................13
3.2
REDUCED NUMBER OF COMPONENTS .............14
3.3
INTERNAL RDSON SENSING..........................14
3.4
EXTERNAL 5V POWER SUPPLY ......................15
3.5
PRE-REGULATOR FOR REDUCED POWER
DISSIPATION..............................................................16
3.6
5V ONLY SUPPLY..........................................17
3.7
HIGH MOTOR CURRENT .................................18
3.8
DRIVER PROTECTION AND EME CIRCUITRY ...20
4
SPI INTERFACE ................................................21
4.1
4.2
4.3
5
SPI DATAGRAM STRUCTURE .........................21
SPI SIGNALS ................................................22
TIMING .........................................................23
REGISTER MAPPING .......................................24
5.1
GENERAL CONFIGURATION REGISTERS ..........25
5.2
VELOCITY DEPENDENT DRIVER FEATURE
CONTROL REGISTER SET .............................................27
5.3
SPI MODE REGISTER ....................................29
5.4
DCSTEP MINIMUM VELOCITY REGISTER .........29
5.5
MOTOR DRIVER REGISTERS ...........................30
6
STEALTHCHOP™ ..............................................39
6.1
6.2
6.3
6.4
6.5
6.6
7
TWO MODES FOR CURRENT REGULATION ......39
AUTOMATIC SCALING ....................................40
VELOCITY BASED SCALING ............................42
COMBINING STEALTHCHOP AND SPREADCYCLE
44
FLAGS IN STEALTHCHOP................................45
FREEWHEELING AND PASSIVE MOTOR BRAKING
46
SPREADCYCLE AND CLASSIC CHOPPER ...47
7.1
7.2
7.3
7.4
SPREADCYCLE
CHOPPER ................................48
CLASSIC CONSTANT OFF TIME CHOPPER.......51
RANDOM OFF TIME .......................................52
CHOPSYNC2 FOR QUIET 2-PHASE MOTOR .....53
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10
INTERNAL SENSE RESISTORS ................. 57
11
VELOCITY BASED MODE CONTROL ....... 59
12
DRIVER DIAGNOSTIC FLAGS .................. 61
12.1
12.2
12.3
14
14.1
14.2
14.3
14.4
15
15.1
15.2
15.3
16
TEMPERATURE MEASUREMENT ....................... 61
SHORT TO GND PROTECTION ....................... 61
OPEN LOAD DIAGNOSTICS ........................... 61
STALLGUARD2 LOAD MEASUREMENT ... 62
TUNING STALLGUARD2 THRESHOLD SGT ..... 63
STALLGUARD2 UPDATE RATE AND FILTER .... 65
DETECTING A MOTOR STALL ......................... 65
LIMITS OF STALLGUARD2 OPERATION .......... 65
COOLSTEP OPERATION ............................. 66
USER BENEFITS............................................. 66
SETTING UP FOR COOLSTEP .......................... 66
TUNING COOLSTEP........................................ 68
STEP/DIR INTERFACE ................................ 69
16.1 TIMING ......................................................... 69
16.2 CHANGING RESOLUTION ............................... 70
16.3 MICROPLYER STEP INTERPOLATOR AND STAND
STILL DETECTION ....................................................... 71
17
DIAG OUTPUTS ........................................... 72
18
DCSTEP .......................................................... 73
18.1
18.2
18.3
18.4
19
19.1
19.2
USER BENEFITS............................................. 73
DESIGNING-IN DCSTEP ................................. 73
DCSTEP WITH STEP/DIR INTERFACE ........... 74
STALL DETECTION IN DCSTEP MODE ............ 77
SINE-WAVE LOOK-UP TABLE................... 78
USER BENEFITS............................................. 78
MICROSTEP TABLE ........................................ 78
20
EMERGENCY STOP ...................................... 79
21
DC MOTOR OR SOLENOID ....................... 80
21.1
SOLENOID OPERATION.................................. 80
22
QUICK CONFIGURATION GUIDE ............ 81
23
GETTING STARTED ..................................... 84
23.1
INITIALIZATION EXAMPLE ............................. 84
24
STANDALONE OPERATION ...................... 85
25
EXTERNAL RESET ........................................ 88
26
CLOCK OSCILLATOR AND INPUT ........... 88
26.1
27
CONSIDERATIONS ON THE FREQUENCY .......... 88
ABSOLUTE MAXIMUM RATINGS ............ 89
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
28
28.1
28.2
28.3
29
29.1
29.2
29.3
29.4
30
ELECTRICAL CHARACTERISTICS .............89
4
30.1
30.2
30.3
DIMENSIONAL DRAWINGS QFN36 5X6 ....... 97
DIMENSIONAL DRAWINGS TQFP-EP48 ....... 99
PACKAGE CODES ......................................... 100
OPERATIONAL RANGE ...................................89
DC AND TIMING CHARACTERISTICS ..............90
THERMAL CHARACTERISTICS ..........................93
31
DISCLAIMER ............................................... 101
LAYOUT CONSIDERATIONS .....................94
32
ESD SENSITIVE DEVICE.......................... 101
EXPOSED DIE PAD ........................................94
WIRING GND ...............................................94
SUPPLY FILTERING ........................................94
LAYOUT EXAMPLE (QFN36) ..........................95
33
TABLE OF FIGURES .................................. 102
34
REVISION HISTORY ................................. 103
35
REFERENCES ............................................... 103
PACKAGE MECHANICAL DATA ................97
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
1
5
Principles of Operation
THE TMC2130 OFFERS THREE BASIC MODES OF OPERATION:
In Step/Direction Driver Mode, the TMC2130 is the microstep sequencer and power driver between a
motion controller and a two phase stepper motor. Configuration of the TMC2130 is done via SPI. A
dedicated motion controller IC or the CPU sends step and direction signals to the TMC2130. The
TMC2130 provides the related motor coil currents to operate the motor. In Standalone Mode, the
TMC2130 can be configured using pins. In this mode of operation CPU interaction is not necessary.
The third mode of operation is the SPI Driver Mode, which is used in combination with TRINAMICs
TMC4361 motion controller chip. This mode of operation offers several possibilities for sophisticated
applications.
OPERATION MODE 1: Step/Direction Driver Mode
An external motion controller is used or a central CPU generates step and direction signals. The
motion controller (e.g. TMC429) controls the motor position by sending pulses on the STEP signal
while indicating the direction on the DIR signal. The TMC2130 provides a microstep counter and a sine
table to convert these signals into the coil currents which control the position of the motor. The
TMC2130 automatically takes care of intelligent current and mode control and delivers feedback on the
state of the motor. The microPlyer automatically smoothens motion. To optimize power consumption
and heat dissipation, software may also adjust coolStep and stallGuard2 parameters in real-time, for
example to implement different tradeoffs between speed and power consumption.
VCP
100n
CPI
charge pump
CPO
VSA
4.7µ
2R2 and 470n are optional
filtering components for
best chopper precision
AIN_IREF
DIR
F
step multiplier
microPlyer
SPI™
IREF
SCK
PU
SDI
PU
SDO
PU
f ace
Inter
programmable
sine table
4*256 entry
Control register
set
Diganostics
DIAG0
PMD
RS
current
comparator
Stepper driver
Protection
& diagnostics
current
comparator
IREF
DAC
DAC
RS
BRB
DIAG out
stallGuard2™
Half Bridge 2
leave open
PU
DRV_ENN
PU
PU
dcStep control
Tie DCEN to GND if
dcStep is not used
Figure 1.1 TMC2130 STEP/DIR application diagram
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DCO
GNDA
DIE PAD
SPI_MODE
TST_MODE
100n
Half Bridge 1
DCIN
PU
VCC_IO
OB2
ISENSE
ISENSE
DCEN
CLK oscillator/
selector
PU=166K pullup to VCC
CLK_IN
phase
stepper
motor
GNDP
coolStep™
dcStep™
opt. ext. clock
10-16MHz
+VIO
3.3V or 5V
I/O voltage
RS=0R15 allows for
maximum coil current.
Use low inductance
SMD resistor type.
Tie BRA and BRB to
GND for internal
2
current sensing
IREF
PDD=100k pulldown
PMD=50k to VCC/2
PDD
BRA
GNDP
spreadCycle &
stealthChop
Chopper
x
OA2
Half Bridge 2
ISENSE
DRV_ENN
SPI interface
B.Dwersteg, ©
TRINAMIC 2014
DIAG1
ISENSE
tep &
coolS Chop
th
steal driver
r
o
t
o
m
PU=166K pullup resistor to VCC
PD=166k pull down resistor to GND
CSN
+VM
OA1
Half Bridge 1
DAC Reference
VCC
PU
5VOUT
100n
2R2
470n
RREF
Optional for internal current
sensing. RREF=9K1 allows for
maximum coil current.
VS
5V Voltage
regulator
5VOUT
optional current scaling
Standstill
current
reduction
22n
100n
STEP
TMC2130
Stepper Motor Driver
+VM
F
F = 60ns spike filter
step & dir input
opt. driver enable
OB1
VS
100n
+VM
S
N
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
6
OPERATION MODE 2: Standalone Mode
The TMC2130 positions the motor based on step and direction signals. The microPlyer automatically
smoothens motion. No CPU interaction is required. Configuration is done by hardware pins. Basic
standby current control can be done by the TMC2130. Optional feedback signals allow error detection
and synchronization.
AIN_IREF
optional current scaling
DIR
STEP
step & dir input
RREF
5VOUT
Optional for internal current
sensing. RREF=9K1 allows for
maximum coil current.
+VM
VCP
100n
charge pump
CPO
CFG1
step multiplier
microPlyer
VSA
4.7µ
2R2
VCC
2R2 and 470n are optional
filtering components for
best chopper precision
470n
TG= toggle with 166K resistor between VCC
and GND to detect open pin
TG
CFG1
TG
CFG2
TG
CFG3
TG
CFG4
TG
CFG5
TG
DRV_ENN_CFG6
TG
TRISTATE configuration
(GND, VCC_IO or open)
Opt. driver
enable input
CFG0
CFG4
Configuration
interface
with TRISTATE
detection
B.Dwersteg, ©
TRINAMIC 2014
PDD=100k pulldown
PMD=50k to VCC/2
Index pulse
Driver error
opt. ext. clock
10-16MHz
+VIO
3.3V or 5V
I/O voltage
DIAG1
PDD
DIAG0
PMD
CLK_IN
IREF
ISENSE
sine table
4*256 entry
CFG2
BRA
ISENSE
RS
GNDP
CFG1
CFG5
spreadCycle &
stealthChop
Chopper
DRV_ENN
Stepper driver
Protection
& diagnostics
x
OA2
Half Bridge 2
CFG0
CFG1
OA1
Half Bridge 1
DAC Reference
le &
dCyc
sprea hChop
t
steal driver
r
o
t
o
m
5V Voltage
regulator
5VOUT
CFG3
Standstill
current
reduction
CFG6
22n
100n
+VM
VS
CFG2
CPI
100n
F
F
F = 60ns spike filter
TMC 2130 Standalone
Stepper Motor Driver
CFG2
current
comparator
current
comparator
IREF
DAC
RS=0R15 allows for
maximum coil
current;
Tie BRA and BRB to
GND for internal
current sensing
DAC
IREF
f ace
Inter
GNDP
S
N
2 phase
stepper
motor
RS
BRB
Half Bridge 2
Status out
(open drain)
OB2
ISENSE
Half Bridge 1
CLK oscillator/
selector
ISENSE
PU
VCC_IO
VS
100n
+VM
GNDA
DIE PAD
TST_MODE
100n
SPI_MODE
OB1
Figure 1.2 TMC2130 standalone driver application diagram
OPERATION MODE 3: SPI Driver Mode
Together with the TMC4361 high-performance S-ramp motion controller the TMC2130 stepper motor
driver offers an SPI control mode, which gives full control over the motor coil currents to the
TMC4361. Combining these two ICs offers several possibilities for demanding applications including
servo features. Please refer to Figure 1.1 for more information about the pinning, which is identical to
step/direction driver mode, except that the STEP & DIR pins are not required for operation.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
7
1.1 Key Concepts
The TMC2130 implements advanced features which are exclusive to TRINAMIC products. These features
contribute toward greater precision, greater energy efficiency, higher reliability, smoother motion, and
cooler operation in many stepper motor applications.
stealthChop™
No-noise, high-precision chopper algorithm for inaudible motion and inaudible
standstill of the motor.
spreadCycle™
High-precision chopper algorithm for highly dynamic motion and absolutely clean
current wave.
dcStep™
Load dependent speed control. The motor moves as fast as possible and never loses
a step.
stallGuard2™
Sensorless stall detection and mechanical load measurement.
coolStep™
Load-adaptive current control reducing energy consumption by as much as 75%.
microPlyer™
Microstep interpolator for obtaining increased smoothness of microstepping when
using the STEP/DIR interface.
In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect
and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.
1.2 SPI Control Interface
The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC2130 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.
The SPI command rate typically is a single initialization after power-on.
1.3 Software
From a software point of view the TMC2130 is a peripheral with a number of control and status
registers. Most of them can either be written only or read only. Some of the registers allow both read
and write access. In case read-modify-write access is desired for a write only register, a shadow
register can be realized in master software.
1.4 Moving the Motor
1.4.1
STEP/DIR Interface
The motor can be controlled by a step and direction input. Active edges on the STEP input can be
rising edges or both rising and falling edges as controlled by a mode bit (dedge). Using both edges
cuts the toggle rate of the STEP signal in half, which is useful for communication over slow interfaces
such as optically isolated interfaces. On each active edge, the state sampled from the DIR input
determines whether to step forward or back. Each step can be a fullstep or a microstep, in which
there are 2, 4, 8, 16, 32, 64, 128, or 256 microsteps per fullstep. A step impulse with a low state on
DIR increases the microstep counter and a high decreases the counter by an amount controlled by the
microstep resolution. An internal table translates the counter value into the sine and cosine values
which control the motor current for microstepping.
1.4.2
SPI Direct Mode
The direct mode allows control of both motor coil currents and polarity via SPI. It mainly is intended
for use with a dedicated external motion controller IC with integrated sequencer. The sequencer
applies sine and cosine waves to the motor coils. This mode also allows control of DC motors, etc.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
8
1.5 stealthChop Driver
stealthChop is a voltage chopper based principle. It guarantees absolutely quiet motor standstill and
silent slow motion, except for noise generated by ball bearings. stealthChop can be combined with
classic cycle-by-cycle chopper modes for best performance in all velocity ranges. Two additional
chopper modes are available: a traditional constant off-time mode and the spreadCycle mode. The
constant off-time mode provides high torque at highest velocity, while spreadCycle offers smooth
operation and good power efficiency over a wide range of speed and load. spreadCycle automatically
integrates a fast decay cycle and guarantees smooth zero crossing performance. The extremely
smooth motion of stealthChop is beneficial for many applications.
Programmable microstep shapes allow optimizing the motor performance for low cost motors.
Benefits of using stealthChop:
- Significantly improved microstepping with low cost motors
- Motor runs smooth and quiet
- Absolutely no standby noise
- Reduced mechanical resonances yields improved torque
1.6 stallGuard2 – Mechanical Load Sensing
stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.
1.7 coolStep – Load Adaptive Current Control
coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool.
Benefits are:
- Energy efficiency
- Motor generates less heat
- Less or no cooling
- Use of smaller motor
power consumption decreased up to 75%
improved mechanical precision
improved reliability
less torque reserve required → cheaper motor does the job
Figure 1.3 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.
0,9
Efficiency with coolStep
0,8
Efficiency with 50% torque reserve
0,7
0,6
0,5
Efficiency
0,4
0,3
0,2
0,1
0
0
50
100
150
200
250
300
350
Velocity [RPM]
Figure 1.3 Energy efficiency with coolStep (example)
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
9
1.8 dcStep – Load Dependent Speed Control
dcStep allows the motor to run near its load limit and at its velocity limit without losing a step. If the
mechanical load on the motor increases to the stalling load, the motor automatically decreases
velocity so that it can still drive the load. With this feature, the motor will never stall. In addition to
the increased torque at a lower velocity, dynamic inertia will allow the motor to overcome mechanical
overloads by decelerating. dcStep feeds back status information to the external motion controller or
to the system CPU, so that the target position will be reached, even if the motor velocity needs to be
decreased due to increased mechanical load. A dynamic range of up to factor 10 or more can be
covered by dcStep without any step loss. By optimizing the motion velocity in high load situations,
this feature further enhances overall system efficiency.
Benefits are:
- Motor does not loose steps in overload conditions
- Application works as fast as possible
- Highest possible acceleration automatically
- Highest energy efficiency at speed limit
- Highest possible motor torque using fullstep drive
- Cheaper motor does the job
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
2
10
Pin Assignments
BRA
OA2
VS
VSA
VCP
31
30
29
34
32
OA1
35
33
TST_MODE
GNDP
36
2.1 Package Outline
CLK
1
28
CSN_CFG3
2
27
CPI
CPO
SCK_CFG2
3
26
VCC
25
5VOUT
24
GNDA
23
AIN_IREF
22
DRV_ENN_CFG6
21
DIAG1
20
DIAG0
19
DCIN_CFG5
SDI_CFG1
4
SDO_CFG0
5
STEP
6
TMC2130-LA
QFN-36
DIR
7
5mm x 6mm
VCC_IO
8
-
9
SPI_MODE
10
18
17
16
VS
DCO
DCEN_CFG4
15
OB2
BRB
14
13
OB1
12
-
GNDP
11
PAD = GNDD
OA2
-
VS
VSA
VCP
CPI
41
40
39
38
37
43
42
-
BRA
OA1
46
44
47
45
GNDP
48
Figure 2.1 TMC2130-LA package and pinning QFN36 (5x6mm² body)
TST_MODE
1
36
CLK
2
35
CPO
CSN_CFG3
3
34
VCC
SCK_CFG2
4
33
5VOUT
SDI_CFG1
5
32
GNDA
-
6
31
-
SDO_CFG0
7
30
AIN_IREF
STEP
8
29
DRV_ENN_CFG6
DIR
9
28
-
VCC_IO
10
27
DIAG1
-
11
26
DIAG0
SPI_MODE
12
25
DCIN_CFG5
TMC2130-TA
TQFP-48
9mm x 9mm
17
18
19
20
21
22
-
BRB
-
OB2
-
VS
-
24
16
OB1
23
15
DCO
14
-
DCEN_CFG4
13
GNDP
PAD = GNDD
Figure 2.2 TMC2130-TA package and pinning TQFP-EP 48-EP (7x7mm² body, 9x9mm² with leads)
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
11
2.2 Signal Descriptions
Pin
QFN36
TQFP48
Type
CLK
1
2
DI
CSN_CFG3
2
3
SCK_CFG2
3
4
SDI_CFG1
4
5
SDO_CFG0
5
7
STEP
DIR
VCC_IO
6
7
8
8
9
10
11,
18,
28,
45,
DNC
9
DI
(tpu)
DI
(tpu)
DI
(tpu)
DIO
(tpu)
DI
DI
14, 16,
20, 22,
41, 43,
47
-
DI
(pu)
SPI_MODE
10
12
N.C.
11
6, 31, 36
GNDP
OB1
12, 35
13
13, 48
15
BRB
14
17
OB2
15
19
VS
16, 31
21, 40
DCO
17
23
DIO
DCEN_CFG4
18
24
DI
(tpu)
DCIN_CFG5
19
25
DI
(tpu)
DIAG0
20
26
DIO
DIAG1
21
27
DIO
DRV_ENN_
CFG6
22
29
DI
(tpu)
AIN_IREF
23
30
AI
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Function
CLK input. Tie to GND using short wire for internal clock
or supply external clock.
SPI chip select input (negative active) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).
SPI serial clock input (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).
SPI data input (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).
SPI data output (tristate) (SPI_MODE=1) or
Configuration input (SPI_MODE=0) (tristate detection).
STEP input
DIR input
3.3V to 5V IO supply voltage for all digital pins.
Do not connect. Leave open to ensure highest distance
for high voltage pins in TQFP package!
Mode selection input with pullup resistor. When tied low,
the chip is in standalone mode and pins have their CFG
functions. When tied high, the SPI interface is available
for control. Integrated pull-up resistor.
Unused pin, connect to GND for compatibility to future
versions.
Power GND. Connect to GND plane near pin.
Motor coil B output 1
Sense resistor connection for coil B. Place sense resistor
to GND near pin. An additional 100nF capacitor to GND
(GND plane) is recommended for best performance.
Motor coil B output 2
Motor supply voltage. Provide filtering capacity near pin
with short loop to nearest GNDP pin (respectively via GND
plane).
dcStep ready output
dcStep enable input (SPI_MODE=1) - tie to GND for normal
operation (no dcStep) or
Configuration input (SPI_MODE=0) (tristate detection).
dcStep gating input for axis synchronization (SPI_MODE=1)
or
Configuration input (SPI_MODE=0) (tristate detection).
Diagnostics output DIAG0. Use external pull-up resistor
with 47k or less in open drain mode.
Diagnostics output DIAG1. Use external pull-up resistor
with 47k or less in open drain mode.
Enable input (SPI_MODE=1) or
configuration / Enable input (SPI_MODE=0) (tristate
detection).
The power stage becomes switched off (all motor outputs
floating) when this pin becomes driven to a high level.
Analog reference voltage for current scaling (optional
mode) or reference current for use of internal sense
resistors
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
Pin
GNDA
QFN36
24
TQFP48
32
5VOUT
25
33
VCC
26
34
CPO
27
35
CPI
28
37
VCP
29
38
VSA
30
39
OA2
32
42
BRA
33
44
OA1
TST_MODE
34
36
46
1
Exposed
die pad
-
-
Type
DI
12
Function
Analog GND. Tie to GND plane.
Output of internal 5V regulator. Attach 2.2µF or larger
ceramic capacitor to GNDA near to pin for best
performance. May be used to supply VCC of chip.
5V supply input for digital circuitry within chip and
charge pump. Attach 470nF capacitor to GND (GND plane).
May be supplied by 5VOUT. A 2.2 or 3.3 Ohm resistor is
recommended for decoupling noise from 5VOUT. When
using an external supply, make sure, that VCC comes up
before or in parallel to 5VOUT or VCC_IO, whichever
comes up later!
Charge pump capacitor output.
Charge pump capacitor input. Tie to CPO using 22nF 50V
capacitor.
Charge pump voltage. Tie to VS using 100nF capacitor.
Analog supply voltage for 5V regulator. Normally tied to
VS. Provide a 100nF filtering capacitor.
Motor coil A output 2
Sense resistor connection for coil A. Place sense resistor
to GND near pin. An additional 100nF capacitor to GND
(GND plane) is recommended for best performance.
Motor coil A output 1
Test mode input. Tie to GND using short wire.
Connect the exposed die pad to a GND plane. Provide as
many as possible vias for heat transfer to GND plane.
Serves as GND pin for digital circuitry.
*(pu) denominates a pin with pullup resistor; (tpu) denominates a pin with pullup resistor or toggle
detection. Toggle detection is active in standalone mode, only (SPI_MODE=0)
* Digital Pins: All pins of type DI, DI(pu), DI(tpu), DIO and DIO(tpu) refer to VCC_IO and have intrinsic
protective clamping diodes to GND and VCC_IO and use Schmitt trigger inputs.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
3
13
Sample Circuits
The sample circuits show the connection of external components in different operation and supply
modes. The connection of the bus interface and further digital signals is left out for clarity.
Optional use lower
voltage down to 6V
VCP
CPI
CPO
AIN_IREF
22n
63V
+VM
100n
16V
+VM
VS
VSA
5VOUT
100n
DIR
STEP
3.1 Standard Application Circuit
4.7µ
5V Voltage
regulator
Step & Dir input
with microPlyer
charge pump
DAC Reference
100n
100n
100µF
IREF
2R2
VCC
OA1
TMC2130
470n
CSN
SCK
SDI
SDO
OA2
S
N
stepper
motor
SPI interface
Use low inductivity SMD
type, e.g. 1206, 0.5W
Sequencer
DIAG1
Full Bridge A
BRA
Driver
RSA
B.Dwersteg, ©
TRINAMIC 2014
DIAG / INT out
DIAG0
OB1
Full Bridge B
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
OB2
CLK_IN
dcStep Controller
Interface
Use low inductivity SMD
type, e.g. 1206, 0.5W
VCC_IO
BRB
RSB
leave open
opt. dcStep control
GNDP
GNDA
DIE PAD
TST_MODE
DRV_ENN
DCO
DC_IN
DC_EN
SPI_MODE
100n
opt. driver enable
Figure 3.1 Standard application circuit
The standard application circuit uses a minimum set of additional components. Two sense resistors
set the motor coil current. See chapter 9 to choose the right sense resistors. Use low ESR capacitors
for filtering the power supply. The capacitors need to cope with the current ripple cause by chopper
operation. A minimum capacity of 100µF near the driver is recommended for best performance.
Current ripple in the supply capacitors also depends on the power supply internal resistance and
cable length. VCC_IO can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V
regulator. In order to minimize linear voltage regulator power dissipation of the internal 5V voltage
regulator in applications where VM is high, a different (lower) supply voltage can be used for VSA, if
available. For example, many applications provide a 12V supply in addition to a higher driver supply
voltage. Using the 12V supply for VSA rather than 24V will reduce the power dissipation of the
internal 5V regulator to about 37% of the dissipation caused by supply with the full motor voltage.
Basic layout hints
Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.
Attention
In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop, especially also upon power up or power down.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
14
3.2 Reduced Number of Components
Optional use lower
voltage down to 6V
+VM
VSA
5VOUT
100n
5V Voltage
regulator
4.7µ
VCC
Figure 3.2 Reduced number of filtering components
The standard application circuit uses RC filtering to de-couple the output of the internal linear
regulator from high frequency ripple caused by digital circuitry supplied by the VCC input. For cost
sensitive applications, the RC-Filtering on VCC can be eliminated. This leads to more noise on 5VOUT
caused by operation of the charge pump and the internal digital circuitry. There is a slight impact on
microstep vibration and chopper noise performance.
3.3 Internal RDSon Sensing
5VOUT
For cost critical or space limited applications, sense resistors can be omitted. For internal current
sensing, a reference current set by a tiny external resistor programs the output current. For calculation
of the reference resistor, refer chapter 10.
AIN_IREF
RREF
DAC Reference
IREF
OA1
Full Bridge A
OA2
S
N
stepper
motor
BRA
Driver
OB1
Full Bridge B
OB2
BRB
Figure 3.3 RDSon based sensing eliminates high current sense resistors
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
15
3.4 External 5V Power Supply
When an external 5V power supply is available, the power dissipation caused by the internal linear
regulator can be eliminated. This especially is beneficial in high voltage applications, and when
thermal conditions are critical. There are two options for using an external 5V source: either the
external 5V source is used to support the digital supply of the driver by supplying the VCC pin, or the
complete internal voltage regulator becomes bridged and is replaced by the external supply voltage.
3.4.1
Support for the VCC Supply
This scheme uses an external supply for all digital circuitry within the driver (Figure 3.4). As the digital
circuitry makes up for most of the power dissipation, this way the internal 5V regulator sees only low
remaining load. The precisely regulated voltage of the internal regulator is still used as the reference
for the motor current regulation as well as for supplying internal analog circuitry.
When cutting VCC from 5VOUT, make sure that the VCC supply comes up before or synchronously
with the 5VOUT supply to ensure a correct power up reset of the internal logic. A simple schematic
uses two diodes forming an OR of the internal and the external power supplies for VCC. In order to
prevent the chip from drawing part of the power from its internal regulator, a low drop 1A Schottky
diode is used for the external 5V supply path, while a silicon diode is used for the 5VOUT path. An
enhanced solution uses a dual PNP transistor as an active switch. It minimizes voltage drop and thus
gives best performance.
In certain setups, switching of VCC voltage can be eliminated. A third variant uses the VCC_IO supply
to ensure power-on reset. This is possible, if VCC_IO comes up synchronously with or delayed to VCC.
Use a linear regulator to generate a 3.3V VCC_IO from the external 5V VCC source. This 3.3V regulator
will cause a certain voltage drop. A voltage drop in the regulator of 0.9V or more (e.g. LD1117-3.3)
ensures that the 5V supply already has exceeded the lower limit of about 3.0V once the reset
conditions ends. The reset condition ends earliest, when VCC_IO exceeds the undervoltage limit of
minimum 2.1V. Make sure that the power-down sequence also is safe. Undefined states can result
when VCC drops well below 4V without safely triggering a reset condition. Triggering a reset upon
power-down can be ensured when VSA goes down synchronously with or before VCC.
+VM
+VM
VSA
5VOUT
+5V
100n
4.7µ
VSA
5V Voltage
regulator
5VOUT
+5V
LL4448
100n
4.7µ
VCC
MSS1P3
5V Voltage
regulator
VCC
VCC_IO
3.3V
regulator
470n
470n
100n
3.3V
VCC supplied from external 5V. 5V or 3.3V IO voltage.
VCC supplied from external 5V. 3.3V IO voltage generated from same source.
+VM
VSA
5VOUT
100n
5V Voltage
regulator
4.7µ
+5V
BAT54
10k
VCC
2x BC857 or
1x BC857BS
470n
4k7
VCC supplied from external 5V using active switch. 5V or 3.3V IO voltage.
Figure 3.4 Using an external 5V supply for digital circuitry of driver (different options)
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
3.4.2
16
Internal Regulator Bridged
In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.5). The circuit will benefit from a well-regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.
Well-regulated, stable
supply, better than +-5%
+5V
VSA
5VOUT
4.7µ
5V Voltage
regulator
10R
VCC
470n
Figure 3.5 Using an external 5V supply to bypass internal regulator
3.5 Pre-Regulator for Reduced Power Dissipation
When operating at supply voltages up to 46V for VS and VSA, the internal linear regulator will
contribute with up to 1W to the power dissipation of the driver. This will reduce the capability of the
chip to continuously drive high motor current, especially at high environment temperatures. When no
external power supply in the range 5V to 24V is available, an external pre-regulator can be built with
a few inexpensive components in order to dissipate most of the voltage drop in external components.
Figure 3.6 shows different examples. In case a well-defined supply voltage is available, a single 1W or
higher power Zener diode also does the job.
+VM
+VM
22k
BCX56 or
similar
22k
BCX56 or
similar
4k7
Z5.6V e.g.
MM5Z5V6
VSA
5VOUT
470n
16V
4.7µ
5V Voltage
regulator
2R2
100R
VSA
5VOUT
470n
16V
4.7µ
VCC
470n
Simple pre-regulator for 24V up to 46V
Figure 3.6 Examples for simple pre-regulators
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5V Voltage
regulator
2R2
VCC
470n
Simple short circuit protected pre-regulator for 24V up to 46V
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
17
VCP
22n
63V
CPI
CPO
AIN_IREF
DIR
STEP
3.6 5V Only Supply
+5V
100n
16V
+5V
VS
VSA
5VOUT
5V Voltage
regulator
Step & Dir input
with microPlyer
charge pump
DAC Reference
4.7µ
100n
100n
100µF
IREF
VCC
OA1
TMC2130
470n
CSN
SCK
SDI
SDO
SPI interface
OA2
S
N
stepper
motor
Use low inductivity SMD
type, e.g. 1206, 0.5W
Sequencer
DIAG1
Full Bridge A
BRA
Driver
RSA
DIAG / INT out
DIAG0
OB1
Full Bridge B
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
OB2
CLK_IN
dcStep Controller
Interface
VCC_IO
A
B
Use low inductivity SMD
type, e.g. 1206, 0.5W
BRB
N
RSB
leave open
opt. dcStep control
GNDP
GNDA
DIE PAD
TST_MODE
DRV_ENN
DCO
DC_IN
DC_EN
SPI_MODE
100n
opt. driver enable
Figure 3.7 5V only operation
While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
18
3.7 High Motor Current
When operating at a high motor current, the driver power dissipation due to MOSFET switch onresistance significantly heats up the driver. This power dissipation will heat up the PCB cooling
infrastructure also, if operated at an increased duty cycle. This in turn leads to a further increase of
driver temperature. An increase of temperature by about 100°C increases MOSFET resistance by
roughly 50%. This is a typical behavior of MOSFET switches. Therefore, under high duty cycle, high
load conditions, thermal characteristics have to be carefully taken into account, especially when
increased environment temperatures are to be supported. Refer the thermal characteristics and the
layout hints for more information. As a thumb rule, thermal properties of the PCB design become
critical for the QFN-36 at or above about 1000mA RMS motor current for increased periods of time.
Keep in mind that resistive power dissipation raises with the square of the motor current. On the
other hand, this means that a small reduction of motor current significantly saves heat dissipation
and energy.
An effect which might be perceived at medium motor velocities and motor sine wave peak currents
above roughly 1.2A peak is a slight sine distortion of the current wave when using spreadCycle. It
results from an increasing negative impact of parasitic internal diode conduction, which in turn
negatively influences the duration of the fast decay cycle of the spreadCycle chopper. This is, because
the current measurement does not see the full coil current during this phase of the sine wave,
because an increasing part of the current flows directly from the power MOSFETs’ drain to GND and
does not flow through the sense resistor. This effect with most motors does not negatively influence
the smoothness of operation, as it does not impact the critical current zero transition. The effect does
not occur with stealthChop.
3.7.1
Reduce Linear Regulator Power Dissipation
When operating at high supply voltages, as a first step the power dissipation of the integrated 5V
linear regulator can be reduced, e.g. by using an external 5V source for supply. This will reduce overall
heating. It is advised to reduce motor stand still current in order to decrease overall power
dissipation. If applicable, also use coolStep. A decreased clock frequency will reduce power dissipation
of the internal logic. Further a decreased chopper frequency also can reduce power dissipation.
3.7.2
Operation near to / above 2A Peak Current
The driver can deliver up to 2.5A motor peak current. Considering thermal characteristics, this only is
possible in duty cycle limited operation. When a peak current up to 2.5A is to be driven, the driver
chip temperature is to be kept at a maximum of 105°C. Linearly derate the design peak temperature
from 125°C to 105°C in the range 2A to 2.5A output current (see Figure 3.8). Exceeding this may lead
to triggering the short circuit detection.
Limit by lower limit of
overtemperature threshold
High temperature
range
125°C
115°C
d
de
en e
m tim
om of
ec s
t r i od
no er
n dp
tio e
ra as
ea cre
Op r in
fo
Die
Temperature
135°C
Specified operational
range for max. 125°C
105°C
1.5A 1.75A
2A
Current
limitation
Derating
for >2A
2.25A 2.5A Peak coil
current
Figure 3.8 Derating of maximum sine wave peak current at increased die temperature
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
3.7.3
19
Reduction of Resistive Losses by Adding Schottky Diodes
Schottky Diodes can be added to the circuit to reduce driver power dissipation when driving high
motor currents (see Figure 3.9). The Schottky diodes have a conduction voltage of about 0.5V and will
take over more than half of the motor current during the negative half wave of each output in slow
decay and fast decay phases, thus leading to a cooler motor driver. This effect starts from a few
percent at 1.2A and increases with higher motor current rating up to roughly 20%. As a 30V Schottky
diode has a lower forward voltage than a 50V or 60V diode, it makes sense to use a 30V diode when
the supply voltage is below 30V. The diodes will have less effect when working with stealthChop due
to lower times of diode conduction in the chopper cycle. At current levels below 1.2A coil current, the
effect of the diodes is negligible.
OA1
Full Bridge A
OA2
BRA
Driver
S
N
stepper
motor
RSA
OB1
Full Bridge B
OB2
1A Schottky Diodes like MSS1P6
or MSS1P3 (VM limited to 30V)
BRB
RSB
Figure 3.9 Schottky diodes reduce power dissipation at high peak currents up to 2A (2.5A)
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
20
3.8 Driver Protection and EME Circuitry
Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events of several kV. It is best practice to avoid ESD events by
attaching all conductive parts, especially the motors themselves to PCB ground, or to apply electrically
conductive plastic parts. In addition, the driver can be protected up to a certain degree against ESD
events or live plugging / pulling the motor, which also causes high voltages and high currents into
the motor connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the
dV/dt caused by ESD events. Larger capacitors will bring more benefit concerning ESD suppression,
but cause additional current flow in each chopper cycle, and thus increase driver power dissipation,
especially at high supply voltages. The values shown are example values – they might be varied
between 100pF and 1nF. The capacitors also dampen high frequency noise injected from digital parts
of the application PCB circuitry and thus reduce electromagnetic emission. A more elaborate scheme
uses LC filters to de-couple the driver outputs from the motor connector. Varistors in between of the
coil terminals eliminate coil overvoltage caused by live plugging. Optionally protect all outputs by a
varistor against ESD voltage.
470pF
100V
OA1
Full Bridge A
OA1
OA2
S
N
stepper
motor
Full Bridge A
50Ohm @
100MHz
V1A
V1
OA2
50Ohm @
100MHz
470pF
100V
BRA
Driver
RSA
470pF
100V
S
N
stepper
motor
V1B
470pF
100V
Driver
100nF
16V
470pF
100V
OB1
Full Bridge B
OB1
Full Bridge B
OB2
50Ohm @
100MHz
V2A
V2
OB2
50Ohm @
100MHz
470pF
100V
BRB
RSB
100nF
16V
470pF
100V
V2B
470pF
100V
Fit varistors to supply voltage
rating. SMD inductivities
conduct full motor coil
current.
Figure 3.10 Simple ESD enhancement and more elaborate motor output protection
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Varistors V1 and V2 protect
against inductive motor coil
overvoltage.
V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
4
21
SPI Interface
4.1 SPI Datagram Structure
The TMC2130 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the device must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the device is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set. Each register is accessed via 32
data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
39 ...
→ 8 bit address
8 bit SPI status
... 0
→ 32 bit data
39 ... 32
→ to TMC2130
RW + 7 bit address
from TMC2130
8 bit SPI status
W
39 / 38 ... 32
38...32
LSB (transmitted last)
31 ... 0
8 bit data
8 bit data
31 ... 24
31...28
27...24
23 ... 16
23...20
19...16
8 bit data
8 bit data
15 ... 8
15...12
7 ... 0
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4.1.1
Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC2130, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
22
Example:
For a read access to the register (DRV_STATUS) with the address 0x6F, the address byte has
to be set to 0x6F in the access preceding the read access. For a write access to the register
(CHOPCONF), the address byte has to be set to 0x80 + 0x6C = 0xEC. For read access, the data
bit might have any value (-). So, one can set them to 0.
action
read DRV_STATUS
read DRV_STATUS
write CHOPCONF:= 0x00ABCDEF
write CHOPCONF:= 0x00123456
data sent to TMC2130
→ 0x6F00000000
→ 0x6F00000000
→ 0xEC00ABCDEF
→ 0xEC00123456
data received from TMC2130
0xSS & unused data
0xSS & DRV_STATUS
0xSS & DRV_STATUS
0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2
SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32
Bit
7
6
5
4
3
2
1
0
Name
Comment
standstill
sg2
driver_error
reset_flag
unused
unused
unused
unused
DRV_STATUS[31] – 1: Signals motor stand still
DRV_STATUS[24] – 1: Signals stallguard flag active
GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)
GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3
Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC2130 has four signals:
- SCK – bus clock input
- SDI – serial data input
- SDO – serial data output
- CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC2130.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
23
4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
tDU
SDI
bit39
tDH
bit38
bit0
tDO
SDO
tZC
bit39
bit38
bit0
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
Parameter
SCK valid before or after change
of CSN
AC-Characteristics
clock period: tCLK
Symbol
tCC
fSCK
fSCK
assumes
synchronous CLK
tCSH
SCK low time
tCL
SCK high time
tCH
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Min
Typ
Max
10
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
*) Min time is for
synchronous CLK
only
*) Min time is for
synchronous CLK
only
assumes minimum
OSC frequency
CSN high time
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
Data out valid time after falling
SCK clock edge
SDI, SCK and CSN filter delay
time
Conditions
Unit
ns
tCLK*)
>2tCLK+10
ns
tCLK*)
>tCLK+10
ns
tCLK*)
>tCLK+10
ns
4
MHz
8
MHz
tDU
10
ns
tDH
10
ns
tDO
no capacitive load
on SDO
tFILT
rising and falling
edge
12
20
tFILT+5
ns
30
ns
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
5
24
Register Mapping
This chapter gives an overview of the complete register set. Some of the registers bundling a number
of single bits are detailed in extra tables. The functional practical application of the settings is detailed
in dedicated chapters.
Note
- All registers become reset to 0 upon power up, unless otherwise noted.
- Add 0x80 to the address Addr for write accesses!
NOTATION OF HEXADECIMAL AND BINARY NUMBERS
0x
%
precedes a hexadecimal number, e.g. 0x04
precedes a multi-bit binary number, e.g. %100
NOTATION OF R/W FIELD
R
W
R/W
R+C
Read only
Write only
Read- and writable register
Clear upon read
OVERVIEW REGISTER MAPPING
REGISTER
DESCRIPTION
General Configuration Registers
These registers contain
global configuration
global status flags
interface configuration
and I/O signal configuration
This register set offers registers for
driver current control
setting thresholds for coolStep operation
setting thresholds for different chopper modes
setting thresholds for dcStep operation
This register set offers registers for
setting / reading out microstep table and
counter
chopper and driver configuration
coolStep and stallGuard2 configuration
dcStep configuration
reading out stallGuard2 values and driver error
flags
Setting for minimum dcStep velocity
Velocity Dependent Driver Feature Control Register
Set
Motor Driver Register Set
dcStep Minimum Velocity
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
25
5.1 General Configuration Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
RW
0x00
17
Register
GCONF
Description / bit names
Bit
GCONF – Global configuration flags
0 I_scale_analog
0:
Normal operation, use internal reference voltage
1:
Use voltage supplied to AIN as current reference
1 internal_Rsense
0:
Normal operation
1:
Internal sense resistors. Use current supplied into
AIN as reference for internal sense resistor
2 en_pwm_mode
1:
stealthChop voltage PWM mode enabled
(depending on velocity thresholds). Switch from
off to on state while in stand still, only.
3 enc_commutation (Special mode - do not use, leave 0)
1:
Enable commutation by full step encoder
(DCIN_CFG5 = ENC_A, DCEN_CFG4 = ENC_B)
4 shaft
1:
Inverse motor direction
5 diag0_error
1:
Enable DIAG0 active on driver errors:
Over temperature (ot), short to GND (s2g),
undervoltage chargepump (uv_cp)
DIAG0 always shows the reset-status, i.e. is active low
during reset condition.
6 diag0_otpw
1:
Enable DIAG0 active on driver over temperature
prewarning (otpw)
7 diag0_stall
1:
Enable DIAG0 active on motor stall (set
TCOOLTHRS before using this feature)
8 diag1_stall
1:
Enable DIAG1 active on motor stall (set
TCOOLTHRS before using this feature)
9 diag1_index
1:
Enable DIAG1 active on index position (microstep
look up table position 0)
10 diag1_onstate
1:
Enable DIAG1 active when chopper is on (for the
coil which is in the second half of the fullstep)
11
12
13
14
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diag1_steps_skipped
1:
Enable output toggle when steps are skipped in
dcStep mode (increment of LOST_STEPS). Do not
enable in conjunction with other DIAG1 options.
diag0_int_pushpull
0:
DIAG0 is open collector output (active low)
1:
Enable DIAG0 push pull output (active high)
diag1_pushpull
0:
DIAG1 is open collector output (active low)
1:
Enable DIAG1 push pull output (active high)
small_hysteresis
0:
Hysteresis for step frequency comparison is 1/16
1:
Hysteresis for step frequency comparison is 1/32
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
26
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
R+C
0x01
3
GSTAT
R
0x04
8
+
8
IOIN
www.trinamic.com
Description / bit names
15 stop_enable
0:
Normal operation
1:
Emergency stop: DCIN stops the sequencer when
tied high (no steps become executed by the
sequencer, motor goes to standstill state).
16 direct_mode
0:
Normal operation
1:
Motor coil currents and polarity directly
programmed via serial interface: Register XDIRECT
(0x2D) specifies signed coil A current (bits 8..0)
and coil B current (bits 24..16). In this mode, the
current is scaled by IHOLD setting. Velocity based
current regulation of stealthChop is not available
in this mode. The automatic stealthChop current
regulation will work only for low stepper motor
velocities.
17 test_mode
0:
Normal operation
1:
Enable analog test output on pin DCO. IHOLD[1..0]
selects the function of DCO:
0…2: T120, DAC, VDDH
Attention: Not for user, set to 0 for normal operation!
Bit
GSTAT – Global status flags
0 reset
1:
Indicates that the IC has been reset since the last
read access to GSTAT. All registers have been
cleared to reset values.
1 drv_err
1:
Indicates, that the driver has been shut down
due to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS for
details. The flag can only be reset when all error
conditions are cleared.
2 uv_cp
1:
Indicates an undervoltage on the charge pump.
The driver is disabled in this case.
Bit
INPUT
Reads the state of all input pins available
0 STEP
1 DIR
2 DCEN_CFG4
3 DCIN_CFG5
4 DRV_ENN_CFG6
5 DCO
6 This bit always shows 1.
7 Don’t care.
31.. VERSION: 0x11=first version of the IC
24 Identical numbers mean full digital compatibility.
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
27
5.2 Velocity Dependent Driver Feature Control Register Set
VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET (0X10…0X1F)
R/W
W
Addr
n
0x10
5
+
5
+
4
Register
Description / bit names
Bit
IHOLD_IRUN – Driver current control
4..0 IHOLD
Standstill current (0=1/32…31=32/32)
In combination with stealthChop mode, setting
IHOLD=0 allows to choose freewheeling or coil
short circuit for motor stand still.
12..8 IRUN
Motor run current (0=1/32…31=32/32)
IHOLD_IRUN
19..16
Hint: Choose sense resistors in a way, that normal
IRUN is 16 to 31 for best microstep performance.
IHOLDDELAY
Controls the number of clock cycles for motor
power down after a motion as soon as standstill is
detected (stst=1) and TPOWERDOWN has expired.
The smooth transition avoids a motor jerk upon
power down.
0:
1..15:
W
R
W
0x11
0x12
0x13
8
20
20
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TPOWER
DOWN
TSTEP
TPWMTHRS
instant power down
Delay per current reduction step in multiple
of 2^18 clocks
TPOWERDOWN sets the delay time after stand still (stst) of the
motor to motor current power down. Time range is about 0 to
4 seconds.
0…((2^8)-1) * 2^18 tCLK
Actual measured time between two 1/256 microsteps derived
from the step input frequency in units of 1/fCLK. Measured
value is (2^20)-1 in case of overflow or stand still.
All TSTEP related thresholds use a hysteresis of 1/16 of the
compare value to compensate for jitter in the clock or the step
frequency. The flag small_hysteresis modifies the hysteresis to
a smaller value of 1/32.
(Txxx*15/16)-1 or
(Txxx*31/32)-1 is used as a second compare value for each
comparison value.
This means, that the lower switching velocity equals the
calculated setting, but the upper switching velocity is higher as
defined by the hysteresis setting.
In dcStep mode TSTEP will not show the mean velocity of the
motor, but the velocities for each microstep, which may not be
stable and thus does not represent the real motor velocity in
case it runs slower than the target velocity.
This is the upper velocity for stealthChop voltage PWM mode.
TSTEP ≥ TPWMTHRS
- stealthChop PWM mode is enabled, if configured
- dcStep is disabled
TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
28
VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET (0X10…0X1F)
R/W
W
Addr
0x14
n
20
Register
TCOOLTHRS
Description / bit names
This is the lower threshold velocity for switching on smart
energy coolStep and stallGuard feature. (unsigned)
Set this parameter to disable coolStep at low speeds, where it
cannot work reliably. The stall detection and stallGuard output
signal becomes enabled when exceeding this velocity. In nondcStep mode, it becomes disabled again once the velocity falls
below this threshold.
TCOOLTHRS ≥ TSTEP ≥ THIGH:
- coolStep is enabled, if configured
- stealthChop voltage PWM mode is disabled
TCOOLTHRS ≥ TSTEP
- stallGuard status output signal is enabled, if
configured
This velocity setting allows velocity dependent switching into
a different chopper mode and fullstepping to maximize torque.
(unsigned)
The stall detection feature becomes switched off for 2-3
electrical periods whenever passing THIGH threshold to
compensate for the effect of switching modes.
W
0x15
20
THIGH
TSTEP ≤ THIGH:
- coolStep is disabled (motor runs with normal current
scale)
- stealthChop voltage PWM mode is disabled
- If vhighchm is set, the chopper switches to chm=1
with TFD=0 (constant off time with slow decay, only).
- chopSync2 is switched off (SYNC=0)
- If vhighfs is set, the motor operates in fullstep mode
and the stall detection becomes switched over to
dcStep stall detection.
microstep velocity time reference t for velocities: TSTEP = fCLK / fSTEP
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
29
5.3 SPI Mode Register
This register cannot be used in STEP/DIR mode.
SPI MODE REGISTER (0X2D)
R/W
Addr
n
Register
Description / bit names
direct_mode
0:
Normal operation
1:
Directly SPI driven motor current
Range [Unit]
±255
for both coils
Direct mode operation:
XDIRECT specifies Motor coil currents and
polarity directly programmed via the serial
interface. Use signed, two’s complement
numbers.
RW
0x2D
32
XDIRECT
Coil A current (bits 8..0) (signed)
Coil B current (bits 24..16) (signed)
Range: +-248 for normal operation, up to +-255
with stealthChop
In this mode, the current is scaled by IHOLD
setting. Velocity based current regulation of
voltage PWM is not available in this mode. The
automatic voltage PWM current regulation will
work only for low stepper motor velocities.
dcStep is not available in this mode. coolStep
and stallGuard only can be used, when
additionally supplying a STEP signal. This will
also enable automatic current scaling.
5.4 dcStep Minimum Velocity Register
DCSTEP MINIMUM VELOCITY REGISTER
R/W
Addr
n
Register
W
0x33
23
VDCMIN
(0X33)
Description / bit names
The automatic commutation dcStep becomes enabled by the
external signal DCEN. VDCMIN is used as the minimum step
velocity when the motor is heavily loaded.
Hint: Also set DCCTRL parameters in order to operate dcStep.
time reference t for VDCMIN: t = 2^24 / fCLK
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TMC2130 DATASHEET (Rev. 1.10 / 2018-MAY-09)
30
5.5 Motor Driver Registers
MICROSTEPPING CONTROL REGISTER SET (0X60…0X6B)
R/W
Addr
n
Register
MSLUT[0]
W
0x60
32
microstep
table entries
0…31
MSLUT[1...7]
W
W
W
R
R
0x61
…
0x67
0x68
0x69
0x6A
0x6B
7
x
32
32
8
+
8
10
9
+
9
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microstep
table entries
32…255
MSLUTSEL
MSLUTSTART
MSCNT
MSCURACT
Description / bit names
Each bit gives the difference between entry x
and entry x+1 when combined with the corresponding MSLUTSEL W bits:
0: W= %00: -1
%01: +0
%10: +1
%11: +2
1: W= %00: +0
%01: +1
%10: +2
%11: +3
This is the differential coding for the first
quarter of a wave. Start values for CUR_A and
CUR_B are stored for MSCNT position 0 in
START_SIN and START_SIN90.
ofs31, ofs30, …, ofs01, ofs00
…
ofs255, ofs254, …, ofs225, ofs224
This register defines four segments within
each quarter MSLUT wave. Four 2 bit entries
determine the meaning of a 0 and a 1 bit in
the corresponding segment of MSLUT.
See separate table!
bit 7… 0:
START_SIN
bit 23… 16: START_SIN90
START_SIN gives the absolute current at
microstep table entry 0.
START_SIN90 gives the absolute current for
microstep table entry at positions 256.
Start values are transferred to the microstep
registers CUR_A and CUR_B, whenever the
reference position MSCNT=0 is passed.
Microstep counter. Indicates actual position
in the microstep table for CUR_A. CUR_B uses
an offset of 256 (2 phase motor).
Hint: Move to a position where MSCNT is
zero before re-initializing MSLUTSTART or
MSLUT and MSLUTSEL.
bit 8… 0:
CUR_A (signed):
Actual microstep current for
motor phase A as read from
MSLUT (not scaled by current)
bit 24… 16: CUR_B (signed):
Actual microstep current for
motor phase B as read from
MSLUT (not scaled by current)
Range [Unit]
32x 0 or 1
reset default=
sine wave
table
7x
32x 0 or 1
reset default=
sine wave
table
0
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