SI2304DDS

New Product Si2304DDS Vishay Siliconix N-Channel 30-V (D-S) MOSFET PRODUCT SUMMARY VDS (V) 30 RDS(on) (Ω) 0.060 at VGS = 10 V 0.075 at VGS = 4.5 V ID (A)a 3.6 2.1 nC 3.6 Qg (Typ.) FEATURES • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • DC/DC Converter TO-236 (SOT-23) D G 1 3 D S 2 G Top View Si2304DDS (P4)* * Marking Code Ordering Information: Si2304DDS-T1-GE3 (Lead (Pb)-free and Halogen-free) S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C) Pulsed Drain Current Continuous Source-Drain Diode Current TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C Maximum Power Dissipation TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)d, e TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Symbol VDS VGS ID IDM IS Limit 30 ± 20 3.6a 3.3 3.3 2.7 15 1.4 0.9b, c 1.7 1.1 1.1b, c 0.7b, c - 55 to 150 260 Unit V A PD TJ, Tstg W °C THERMAL RESISTANCE RATINGS Parameter t≤5s Maximum Junction-to-Ambientb, d Maximum Junction-to-Foot (Drain) Steady State Notes: a. Package limited b. Surface Mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 130 °C/W. Symbol RthJA RthJF Typical 90 60 Maximum 115 75 Unit °C/W Document Number: 65175 S09-1496-Rev. A, 10-Aug-09 www.vishay.com 1 New Product Si2304DDS Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Dynamic b Symbol VDS ΔVDS/TJ ΔVGS(th)/TJ VGS(th) IGSS IDSS ID(on) RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd Rg td(on) tr td(off) tf td(on) tr td(off) tf IS ISM VSD trr Qrr ta tb Test Conditions VGS = 0 V, ID = 250 µA ID = 250 µA VDS = VGS , ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 0 V, TJ = 55 °C VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 3.2 A VGS = 4.5 V, ID = 2.8 A VDS = 15 V, ID = 4.8 A Min. 30 Typ. Max. Unit V 31 -5 1.2 2.2 ± 100 1 10 10 0.049 0.061 11 0.060 0.075 mV/°C V nA µA A Ω S Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulse Diode Forward Current Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Reverse Recovery Fall Time Reverse Recovery Rise Time 235 VDS = 15 V, VGS = 0 V, f = 1 MHz VDS = 15 V, VGS = 10 V, ID = 3.4 A VDS = 15 V, VGS = 4.5 V, ID = 3.4 A f = 1 MHz VDD = 15 V, RL = 5.6 Ω ID ≅ 2.7 A, VGEN = 4.5 V, Rg = 1 Ω 0.8 45 17 4.5 2.1 0.85 0.65 4.4 12 50 12 22 5 VDD = 15 V, RL = 5.6 Ω ID ≅ 2.7 A, VGEN = 10 V, Rg = 1 Ω 12 10 5 TC = 25 °C IS = 2.7 A, VGS = 0 V 0.8 10 IF = 2.7 A, dI/dt = 100 A/µs, TJ = 25 °C 5 6 4 8.8 20 75 20 35 10 20 15 10 1.4 15 1.2 20 10 ns Ω 6.7 3.2 nC pF A V ns nC ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 65175 S09-1496-Rev. A, 10-Aug-09 New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 15 VGS = 10 V thru 4 V 12 I D - Drain Current (A) I D - Drain Current (A) 4 25 °C, unless otherwise noted 5 9 3 TC = - 55 °C 2 TC = 25 °C 1 TC = 125 °C 6 VGS = 3 V 3 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics 0.10 300 Transfer Characteristics R DS(on) - On-Resistance (Ω) 0.08 VGS = 4.5 V 0.06 VGS = 10 V C - Capacitance (pF) 250 Ciss 200 150 0.04 100 Coss 0.02 50 Crss 0 5 10 15 20 25 30 0.00 0 3 6 9 12 15 0 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage 10 ID = 3.4 A VGS - Gate-to-Source Voltage (V) 8 VDS = 7.5 V 6 VDS = 24 V 4 VDS = 15 V R DS(on) - On-Resistance 1.6 1.5 1.4 1.3 (Normalized) 1.2 1.1 1.0 0.9 0.8 0 0 1 2 3 4 5 0.7 - 50 ID = 3.2 A Capacitance VGS = 10 V 2 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 65175 S09-1496-Rev. A, 10-Aug-09 www.vishay.com 3 New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 100 0.14 ID = 3.2 A R DS(on) - On-Resistance (Ω) 0.12 I S - Source Current (A) 10 TJ = 150 °C 0.10 TJ = 25 °C 0.08 TJ = 125 °C 1 0.06 TJ = 25 °C 0.1 0.0 0.04 0.3 0.6 0.9 1.2 1.5 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage 2.4 25 On-Resistance vs. Gate-to-Source Voltage 2.2 20 2.0 VGS(th) (V) Power (W) 15 ID = 250 µA 1.8 10 1.6 5 1.4 1.2 - 50 - 25 0 25 50 75 100 125 150 0 0.001 0.01 0.1 1 Time (s) 10 100 1000 TJ - Temperature (°C) Threshold Voltage 100 Limited by RDS(on)* I D - Drain Current (A) 10 100 µs Single Pulse Power 1 1 ms 10 ms 100 ms 0.1 TA = 25 °C Single Pulse 0.01 0.1 1 1 s, 10 s DC BVDSS Limited 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient www.vishay.com 4 Document Number: 65175 S09-1496-Rev. A, 10-Aug-09 New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 5 25 °C, unless otherwise noted 2.0 4 I D - Drain Current (A) 1.5 Package Limited 3 Power (W) 1.0 2 0.5 1 0 0 25 50 75 100 125 150 0.0 25 50 75 100 125 150 TC - Case Temperature (°C) TC - Case Temperature (°C) Current Derating* Power Derating * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 65175 S09-1496-Rev. A, 10-Aug-09 www.vishay.com 5 New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 0.1 0.05 0.02 Notes: PDM t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 130 °C/W 3. TJM - T A = PDMZthJA(t) 0.01 10 -4 Single Pulse 10 -3 10 -2 10 -1 1 10 4. Surface Mounted 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 Square Wave Pulse Duration (s) 10 -1 1 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65175. www.vishay.com 6 Document Number: 65175 S09-1496-Rev. A, 10-Aug-09 Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 1 2 E S e1 e D 0.10 mm A A2 0.004" Seating Plane A1 C L L1 C C q 0.25 mm Gauge Plane Seating Plane Dim A A1 A2 b c D E E1 e e1 L L1 S q ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 MILLIMETERS Min 0.89 0.01 0.88 0.35 0.085 2.80 2.10 1.20 0.95 BSC 1.90 BSC 0.40 0.64 Ref 0.50 Ref 3° 8° 3° 0.60 0.016 INCHES Max 1.12 0.10 1.02 0.50 0.18 3.04 2.64 1.40 Min 0.035 0.0004 0.0346 0.014 0.003 0.110 0.083 0.047 0.0374 Ref 0.0748 Ref Max 0.044 0.004 0.040 0.020 0.007 0.120 0.104 0.055 0.024 0.025 Ref 0.020 Ref 8° Document Number: 71196 09-Jul-01 www.vishay.com 1 AN807 Vishay Siliconix Mounting LITTLE FOOTR SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. ambient air. This pattern uses all the available area underneath the body for this purpose. 0.114 2.9 See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.081 2.05 0.150 3.8 0.059 1.5 0.0394 1.0 0.037 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. Document Number: 70739 26-Nov-03 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SOT-23 0.037 (0.950) 0.022 (0.559) (2.692) 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index (0.724) 0.029 (1.245) 0.106 0.049 APPLICATION NOTE Document Number: 72609 Revision: 21-Jan-08 www.vishay.com 25 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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