SI9102DN02-T1-E3

Si9102 Vishay Siliconix 3-W High-Voltage Switchmode Regulator DESCRIPTION The Si9102 high-voltage switchmode regulator is a monolithic BiC/DMOS integrated circuit which contains most of the components necessary to implement a high-efficiency dc-todc converter up to 3 watts. It can either be operated from a low-voltage dc supply, or directly from a 10 to 120 V unregulated dc power source. This device may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward). The Si9102 is available in both standard and lead (Pb)-free 14-pin plastic DIP and 20-pin PLCC packages which are specified to operate over the industrial temperature range of - 40 °C to 85 °C. FEATURES • • • • • • • 10 to 120 V Input Range Current-Mode Control On-chip 200 V, 7 Ω MOSFET Switch SHUTDOWN and RESET High Efficiency Operation (> 80 %) Internal Start-Up Circuit Internal Oscillator (1 MHz) FUNCTIONAL BLOCK DIAGRAM OSC IN 8 (11) OSC OUT 7 (10) FB 14 (20) COMP 13 (18) DISCHARGE 9 (12) Error Amplifier 10 (14) + 4 V (1 %) Ref Gen 2V + OSC Clock (1/2 fOSC) Current-Mode Comparator R Q S + 1.2 V C/L Comparator 3 (5) DRAIN - VIN (BODY) VREF 5 (8) 1 (2) BIAS 6 (9) Current Sources To Internal Circuits 4 (7) VCC Undervoltage Comparator Q R SOURCE VCC +VIN 2 (3) 8.8 V + 9.4 V + S 11 (16) 12 (17) SHUTDOWN RESET Note: Figures in parenthesis represent pin numbers for 20-pin package. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 www.vishay.com 1 Si9102 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Voltages Referenced to - VIN (VCC < + VIN + 0.3 V) VCC +VIN VDS ID (Peak) (Note: 300 µs pulse, 2 % duty cycle) ID (rms) Logic Inputs (RESET, SHUTDOWN, OSC IN) Linear Inputs (FEEDBACK, SOURCE) HV Pre-Regulator Input Current (continuous) Storage Temperature Operating Temperature Junction Temperature (TJ) Power Dissipation (Package)a Thermal Impedance (ΘJA) 14-Pin Plastic DIP (J Suffix)b 20-Pin PLCC (N Suffix)c 14-Pin Plastic DIP 20-Pin PLCC Limit 15 120 200 2 250 - 0.3 V to VCC + 0.3 V - 0.3 to 7 3 - 65 to 125 - 40 to 85 150 750 1400 167 90 Unit V A mA V mA °C mW °C/W Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 6 mW/°C above 25 °C. c. Derate 11.2 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Voltages Referenced to - VIN VCC ROSC Linear Inputs + VIN fOSC Digital Inputs Limit 9.5 to 13.5 25 kΩ to 1 MΩ 0 to 7 10 to 120 40 kHz to 1 MHz 0 to VCC Unit V V V SPECIFICATIONSa Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 390 kΩ, ROSC = 330 kΩ OSC IN = - VIN (OSC Disabled) RL = 10 MΩ VREF = - VIN Limits D Suffix - 40 to 85 °C Tempb Room Full Room Room Full Room Room Room Room Full Mind 3.92 3.86 15 70 Typc 4.0 30 100 0.5 3 100 200 10 200 Maxd 4.08 4.14 45 130 1.0 Parameter Reference Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye Oscillator Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente Symbol Unit VR ZOUT ISREF TREF fMAX fOSC Δf/f TOSC V kΩ µA mV/°C MHz ROSC = 0 ROSC = 330 kΩg ROSC = 150 kΩg Δf/f = f(13.5 V) - f(9.5 V)/f(9.5 V) 1 80 160 120 240 15 500 kHz % ppm/°C www.vishay.com 2 Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 390 kΩ, ROSC = 330 kΩ FB Tied to COMP OSC IN = - VIN (OSC Disabled) OSC IN = - VIN, VFB = 4 V, OSC IN = - VIN (OSC Disabled) Source (VFB = 3.4 V) OSC IN = - VIN (OSC Disabled) Sink (VFB = 4.5 V) 9.5 V ≤ VCC ≤ 13.5 V RL = 100 Ω from DRAIN to VCC VFB = 0 V RL = 100 Ω from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1 IIN = 10 µA VCC ≥ 10 V Pulse Width ≤ 300 µs, VCC = 7 V IPRE-REGULATOR = 10 µA RL = 100 Ω from DRAIN to VCC See Detailed Description Limits D Suffix - 40 to 85 °C Tempb Mind Typc Maxd Unit Parameter Error Amplifier Feedback Input Voltage Input BIAS Current Open Loop Voltage Gaine Unity Gain Bandwidth Output Current Input OFFSET Voltage Output Current Power Supply Rejection Current Limit Threshold Voltage Delay to Outpute Pre-Regulator/Start-Up Input Voltage Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG, - VUVLO Supply Supply Current Bias Current Logic SHUTDOWN Delaye SHUTDOWN Pulse Widthe RESET Pulse Widthe Latching Pulse Widthe SHUTDOWN and RESET Low Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low MOSFET Switch Breakdown Voltage Drain-Source On Resistancef Drain Off Leakage Current e Symbol VFB IFB AVOL BW ZOUT IOUT VOS IOUT PSRR Room Room Room Room Room Room Room Room Room 3.96 4.00 25 4.04 500 V nA dB MHz 60 0.7 80 1 1000 - 2.0 ± 15 2000 - 1.4 ± 40 Dynamic Output Impedancee Ω mA mV mA dB 0.12 50 0.15 70 VSOURCE td Room Room 1.0 1.2 100 1.4 200 V ns + VIN + IIN ISTART VREG VUVLO VDELTA ICC IBIAS tSD tSW tRW tLW VIL VIH IIH IIL VBR(DSS) rDS(on) IDSS Room Room Room Room Room Room Room Room 8 7.8 7.0 0.3 0.45 10 15 9.4 8.8 0.6 0.6 15 50 50 50 25 120 10 V µA mA 9.7 9.2 V 1.0 20 100 mA µA VSOURCE = - VIN, See Figure 2 Room Room Room Room Room Room 8.0 See Figure 3 ns 2.0 1 - 35 200 - 25 220 7 5 10 5 V µA VIN = 10 V VIN = 0 V IDRAIN = 100 µA IDRAIN = 100 mA VDRAIN = 100 V Room Room Full Room Room V Ω µA Room 35 pF Drain Capacitance CDS Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. Temperature coefficient of rDS(on) is 0.75 % per °C, typical. g. CSTRAY Pin 8 = ≤ 5 pF. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 www.vishay.com 3 Si9102 Vishay Siliconix TIMING WAVEFORMS 1.5 V SOURCE 0 VCC DRAIN 0 50 % td tr ≤ 10 ns VCC SHUTDOWN 0VCC DRAIN 0 50 % tSD tf ≤ 10 ns 10 % 10 % Figure 1. Figure 2. tSW VCC SHUTDOWN 0VCC RESET 050 % 50 % tRW 50 % 50 % tLW 50 % tr, tf ≤ 10 ns Figure 3. TYPICAL CHARACTERISTICS 140 VCC = - VIN 120 100 +V IN (V) 80 60 40 20 0 10 15 +IIN (mA) 20 f OUT (Hz) 1M 100 k 10 k 10 k 100 k rOSC - Oscillator Resistance (Ω) 1M Figure 4. + VIN vs. + IIN at Start-Up Figure 5. Output Switching Frequency vs. Oscillator Resistance www.vishay.com 4 Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix PIN CONFIGURATIONS PDIP-14 1 2 3 4 5 6 7 Top View 14 13 12 11 10 9 8 PIN DESCRIPTION Function BIAS + VIN DRAIN SOURCE - VIN VCC OSC OUT OSC IN DISCHARGE VREF Pin 14-Pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20-Pin PLCC* 2 3 5 7 8 9 10 11 12 14 16 17 18 20 PLCC-20 3 2 1 20 19 SHUTDOWN RESET COMP FB 4 5 6 7 8 18 17 16 15 14 *Pins 1, 4, 6, 13, 15, and 19 = N/C ORDERING INFORMATION Standard Part Number Si9102DJ02 Si9102DN02 Lead (Pb)-free Part Number Si9102DJ02-E3 Si9102DN02-E3 - 40 to 85 °C PLCC-20 Temperature Range Package PDIP-14 9 10 11 12 13 Top View Si9102DN02-T1 Si9102DN02-T1-E3 (With Tape (With Tape and Reel) and Reel) DETAIL DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9102 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated lowvoltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, + VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between + VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 9.4 V. If VCC is not forced to exceed the 9.4 V threshold, then VCC will be regulated to a nominal value of 9.4 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.8 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: During start-up or when VCC drops below 9.4 V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48 V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 4 gives the typical pre-regulator current at start-up as a function of input voltage. www.vishay.com 5 Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix DETAIL DESCRIPTION BIAS To properly set the bias for the Si9102, a 390 kΩ resistor should be tied from BIAS to - VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 µA. Reference Section The reference section of the Si9102 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the Si9102 brings the output of the error amplifier (which is configured for unity gain during trimming) to within ± 1 % of 4 V. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC in and OSC out pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to - VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to ≤ 50 % by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5 V pulse amplitude and 0.5 µs pulse width, typical values would be 100 pF in series with 3 kΩ to OSC IN. Output Switch The output switch is a 7 Ω , 200 V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic bodydrain diode. However, the body contact in the Si9102 is connected internally to - VIN and is independent of the SOURCE. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Table 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN H H L L RESET H H L L Output Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change) www.vishay.com 6 Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix APPLICATIONS +VIN GND 100 µH 2 1N5819 3 +5V 20 µF 300 µH 0.1 µF 220 µF 1 4 5 GND 7 18 kΩ 1 2 390 kΩ 3 4 5 6 7 2Ω W 14 13 12 240 kΩ 0.022 µF 8 6 1N5819 0.1 µF 47 µF -5V Si9102DJ 11 10 9 8 0.1 µF 0.1 µF 1/ 2 12 kΩ 1N4148 150 kΩ - VIN (- 96 VDC) Figure 6. Flyback Converter for Double Battery Telecommunications Power Supplies Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70001. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 www.vishay.com 7 Package Information Vishay Siliconix PLCC: 2O-LEAD (POWER IC ONLY) D−SQUARE D1−SQUARE B1 A2 MILLIMETERS Dim A A1 A2 B B1 D D1 D2 e1 Min 4.20 2.29 0.51 0.331 0.661 9.78 8.890 7.37 INCHES Min 0.165 0.090 0.020 0.013 0.026 0.385 0.350 0.290 Max 4.57 3.04 − 0.553 0.812 10.03 9.042 8.38 Max 0.180 0.120 − 0.021 0.032 0.395 0.356 0.330 B e1 D2 1.27 BSC 0.050 BSC A1 A ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5917 0.101 mm 0.004″ Document Number: 72812 28-Jan-04 www.vishay.com 1 Package Information Vishay Siliconix PDIP: 14-LEAD (POWER IC ONLY) 14 13 12 11 10 9 8 E1 E 1 2 3 4 5 6 7 D S Q1 A A1 L 15° MAX eA B1 e1 B C Dim A A1 B B1 C D E E1 e1 eA L Q1 S MILLIMETERS Min Max 3.81 0.38 0.38 0.89 0.20 17.27 7.62 5.59 2.29 7.37 2.79 1.27 1.02 5.08 1.27 0.51 1.65 0.30 19.30 8.26 7.11 2.79 7.87 3.81 2.03 2.03 INCHES Min Max 0.150 0.015 0.015 0.035 0.008 0.680 0.300 0.220 0.090 0.290 0.110 0.050 0.040 0.200 0.050 0.020 0.065 0.012 0.760 0.325 0.280 0.110 0.310 0.150 0.080 0.080 ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5919 Document Number: 72814 28-Jan-04 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1