SI9122E

Si9122E Vishay Siliconix 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers DESCRIPTION Si9122E is a half-bridge controller IC ideally suited to fixed telecom applications where high efficiency is required at low output voltages (e.g. < 3.3 V). Designed to operate within the fixed telecom voltage range of 36 V to 75 V, the IC is capable of controlling and driving both the low and high-side switching devices of a half bridge circuit and also controlling the switching devices on the secondary side of the bridge. Due to the very low on-resistance of the secondary MOSFETs, a significant increase in conversion efficiency can be achieved as compared with conventional Schottky diodes. Control of the secondary devices is by means of a pulse transformer and a pair of inverters. Such a system has efficiencies well in excess of 90 % even for low output voltages. On-chip control of the dead time delays between the primary and secondary synchronous signals keep efficiencies high and prevent shorting of the power transformer. An external resistor sets the oscillator frequency from 200 kHz to 500 kHz. Si9122E has advanced current monitoring and control circuitry which allow the user to set the maximum current in the primary circuit. Such a feature acts as protection against output shorting and also provides constant current into large capacitive loads during start-up or when paralleling power supplies. Current sensing is by means of a sense resistor on the low-side primary device. FEATURES • • • • • • • • • • • • • 92 % primary/secondary duty cycle 135 °C over temperature protection Compatible with ETSI 300 132-2 RoHS COMPLIANT 28 V to 75 V input voltage range Integrated ± 1 A half bridge primary drivers Secondary synchronous rectifier control signals with programmable deadtime delay Voltage mode control Voltage feedforward compensation High voltage pre-regulator operates during start-up Current sensing on low-side primary device Frequency foldback eliminates constant current tail Advanced maximum current control during start-up and shorted load Low input voltage detection Programmable soft-start function • APPLICATIONS • • • • Network cards Power supply modules Distributed power systems Intermediate bus converter • Brick converter FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION 36 V to 75 V VCC VIN REG_COMP BST Synchronous Rectifiers DH LX 1 V to 12 V Typ. + VOUT - Si9122E VINDET DL CS2 CS1 CL_CONT SRH SRL PGND ROSC VREF BBM GND VCC Error Amplifier + VREF EP SS Opto Isolator Figure 1. Document Number: 73866 S-80112-Rev. D, 21-Jan-08 www.vishay.com 1 Si9122E Vishay Siliconix TECHNICAL DESCRIPTION Si9122E is a voltage mode controller for the half-bridge topology. With 100 V depletion mode MOSFET, the Si9122E is capable of powering directly from the high voltage bus to VCC through an external PNP pass transistor, or may be powered through an external regulator directly through the VCC pin. With PWM control, Si9122E provides peak efficiency throughout the entire line and load range. In order to simplify the design of efficient secondary synchronous rectification circuitry, the Si9122E provides intelligent gate drive signals to control the secondary MOSFETs. With independent gate drive signals from the controller, transformer design is no longer limited by the gate to source rating of the secondary-side MOSFETs. Si9122E provides constant VGS voltage, independent of the line voltage to minimize the gate charge loss as well as conduction loss. To prevent shoot-through current or transformer shorting, adjustable Break-Before-Make (BBM) time is incorporated into the IC and is programmed by an external precision resistor. Si9122E is assembled in lead (Pb)-free TSSOP-20 and MLP65-20 packages. To satisfy stringent ambient temperature requirements, Si9122E is rated to handle the industrial temperature range of - 40 °C to 85 °C. When a situation arises which results in a rapid increase in primary (or secondary) current such as output shorted or start-up with a large output capacitor, control of the PWM generator is handed over to the current loop. Monitoring of the load current is by means of an external current sense resistor in the source of the primary low-side switch. With the lower OTP set at 135 °C , the DNF20 package improves the thermal headroom. ROSC High-Side Primary Driver Int VIN VCC 9.1 V REG_COMP Pre-Regulator VREF VINDET VREF + + + - BST DH LX VUVLO 8.8 V Low-Side Primary Driver OSC Ramp VUV VFF VCC DL VSD 550 mV 132 k 60 k EP Error Amplifier – + V REF PGND + – 2 PWM Comparator Driver Control and Timing VCC SRH SYNC Driver High 20 µA SS ISS 8V OTP Over Current Protection + – Peak DET Duty Cycle Control VCC SRL CS2 CS1 Si9122E GND CL_CONT BBM SYNC Driver Low Figure 2. ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V Parameter VIN (Continuous) VIN (100 ms) VCC VBST VLX VBST - VLX VREF, ROSC Logic Inputs Analog Inputs HV Pre-Regulator Input Current Continuous Continuous 100 ms Limit 80 100 14.5 95 113.2 100 15 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 5 mA V Unit www.vishay.com 2 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V Parameter Storage Temperature Operating Junction Temperature Power Dissipationa Thermal Impedance (θJA) TSSOP-20 MLP65-20c TSSOP-20 MLP65-20 b Limit - 65 to 150 150 850 2500 75 38 Unit °C mW °C/W Notes: a. Device mounted on JEDEC compliant 1S2P test board. b. Derate 14 mW/°C above 25 °C. c. Derate 26 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE All voltages referenced to GND = 0 V Parameter VIN VCC CVCC fOSC ROSC RBBM CREF CBOOST Analog Inputs Digital Inputs Reference Voltage Output Current Limit 36 to 75 10.5 to 13.2 ≥ 4.7 200 to 500 30 to 72 22 to 50 0.1 0.1 0 to VCC - 2 0 to VCC 0.1 to 2.5 Unit V µF kHz kΩ µF V mA SPECIFICATIONSa Test Conditions Unless Otherwise Specified fNOM = 500 kHz, VIN = 75 V VINDET = 7.5 V; 10.5 V ≤ VCC ≤ 13.2 V VCC = 12 V, 25 °C Load = 0 mA VREF = 0 V IREF = 0 to - 2.5 mA at 100 Hz ROSC = 30 kΩ, fNOM = 500 kHz FMAX FFOBK IBIAS AV BW PSRR SR at 110 Hz ROSC = 22.6 kΩ fNOM = 500 kHz, VCS2 - VCS1 > 150 mV VEP = 0 V - 40 - 2.2 5 60 0.5 - 20 400 500 100 - 15 - 30 60 20 600 Limits - 40 to 85 °C Min.b 3.2 Typ.c 3.3 Max.b 3.4 - 50 - 75 Unit V mA mV dB % kHz Parameter Reference (3.3 V) Output Voltage Short Circuit Current Load Regulation Power Supply Rejection Oscillator Accuracy (1 % ROSC) Max Frequencyg Foldback Frequencyd Error Amplifier Input Bias Current Gain Bandwidth Power Supply Rejection Slew State Symbol VREF ISREF dVr/dir PSRR µA V/V MHz dB V/µs Document Number: 73866 S-80112-Rev. D, 21-Jan-08 www.vishay.com 3 Si9122E Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified fNOM = 500 kHz, VIN = 75 V VINDET = 7.5 V; 10.5 V ≤ VCC ≤ 13.2 V VCS1 - GND, VCS2 - GND Limits - 40 to 85 °C Min.b Typ.c ± 150 Max.b Unit mV Parameter Current Sense Amplifier Input Voltage CM Range Current Sense Amplifier Input Amplifier Gain Input Amplifier Bandwidth Input Amplifier Offset Voltage CL_CONT Current Symbol VCM AVOL BW VOS 17.5 5 ±5 dVCS = 0 120 0 >2 100 dVCS = 100 mV dVCS = 100 mV dB MHz mV µA mA ICL_CONT Lower Current Limit Threshold Upper Current Limit Threshold Hysteresis CL_CONT Clamp Level PWM Operation VTLCL VTHCL CL_CONT IPD = IPU - ICL_CONT = 0 IPD > 2 mA IPU < 500 µA IPU = 500 µA Primary 0.6 88 90 mV 150 - 50 1.5 91 93 < 17 3 36 86 8 - 29 50 20 7.4 TA = 25 °C 8.5 7.15 TA = 25 °C 8.1 9.1 9.1 9.2 8.8 8.8 0.5 9.8 9.3 10.4 9.7 V - 19 82 75 10 200 14 -9 110 V µA mA µA mA 94 95 V % % DMAX Duty Cycle DMIN Pre-Regulator Input Voltage Input Leakage Current Regulator Bias Current Regulator_Comp Pre-Regulator drive Capability VCC Pre-Regulator Turn Off Threshold Voltage Undervoltage Lockout VULVO Hysteresisf Soft-Start Soft-Start Current Output Soft-Start Completion Voltage Shutdown VINDET Shutdown VSD Hysteresis VINDET Input Threshold Protection VINDET - VIN Under Voltage VUV Hysteresis Over Temperature Voltages Activating Temperature De-Activating Temperature OTP_on OTP_off VUV ISS VSS_COMP VSD + VIN ILKG IREG1 IREG2 ISOURCE ISINK ISTART VREG1 VREG2 VUVLO VUVLOHYS fOSC = 500 kHz, 25 °C VINDET = 4.8 V, VIN = 48 V VEP = 0 V Secondary VEP = 1.75 V VCS2 - VCS1 > 150 mV IIN = 10 µA VIN = 75 V, VCC > VREG VIN = 75 V, VINDET < VSD VIN = 75 V, VINDET > VREF VCC = 12 V VCC < VREG VINDET > VREF VINDET = 0 V VCC Rising Start-Up Condition Normal Operation VINDET Rising VINDET Falling VINDET Rising VINDET Falling TJ Increasing TJ Decreasing 12 7.35 350 20 8.05 550 200 28 8.85 720 µA V mV 3.13 0.23 3.3 0.3 135 113 3.46 0.35 V °C www.vishay.com 4 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified fNOM = 500 kHz, VIN = 75 V VINDET = 7.5 V; 10.5 V ≤ VCC ≤ 13.2 V Shutdown, VINDET = 0 V VINDET < VREF VINDET > VREF, fNOM = 500 kHZ VCC = 12 V, CDH = CDL = 3 nF CSRH = CSRL = 0.3 nF Sourcing 10 mA Sinking 10 mA VLX = 48 V, VBST = VLX + VCC VLX = 48 V, VBST = VLX + VCC VCC = 10.5 V CDH = 3 nF VBST - 0.3 VLX + 0.3 1.3 - 1.3 0.75 1.9 - 0.7 - 1.0 1.0 35 35 VCC - 0.3 0.3 - 1.0 0.75 1.0 35 35 VCC - 0.4 0.4 48 9 24 18 - 100 100 35 35 < 200 < 200 < 200 < 200 mA ns ns - 0.75 2.7 - 0.4 - 0.75 Limits - 40 to 85 °C Min.b 50 4 5 8 10 21 Typ.c Max.b 350 12 15 mA Unit µA Parameter Converter Supply Current (VCC) Shutdown Converter Supply Current (VCC) Switching Disabled Switching w/o Load Switching with CLOAD Symbol ICC1 ICC2 ICC3 ICC4 Output MOSFET DH Driver (High-Side) VOH Output High Voltage VOL Output Low Voltage Boost Current LX Current Peak Output Source Peak Output Sink Rise Time Fall Time IBST ILX ISOURCE ISINK tr tf V mA A ns Output MOSFET DL Driver (Low-Side) VOH Output High Voltage VOL Output Low Voltage Peak Output Source Peak Output Sink Rise Time Fall Time ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA VCC = 10.5 V CDH = 3 nF V A ns Synchronous Rectifier (SRH, SRL) Drivers VOH Output High Voltage Output Low Voltage VOL tBBM1 Break-Before-Make Timee tBBM2 tBBM3 tBBM4 Peak Output Source Peak Output Sink Rise Time Fall Time Voltage Mode Error Amplifier Current Mode Current Amplifier td3DH td4DL td1DH td2DL ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA TA = 25 °C, RBBM = 33 kΩ, VINDET = 4.8 V, VEP = 0 V, VIN = 48 V TA = 25 °C, RBBM = 33 kΩ, BST= 60 V, VINDET = 4.8 V, VEP = 0 V, VIN = 48 V = LX VCC = 10.5 V CDH = 3 nF V Input to High-Side Switch Off Input to Low-Side Switch Off Input to High-Side Switch Off Input to Low-Side Switch Off ns ns Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. FMIN when VCL_CONT at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature. e. See Figure 3 for Break-Before-Make time definition. f. VUVLO tracks VREG1 by a diode drop. g. Guaranteed by design and characterization, not tested in production. Document Number: 73866 S-80112-Rev. D, 21-Jan-08 www.vishay.com 5 Si9122E Vishay Siliconix TIMING DIAGRAM FOR MOS DRIVERS VCC PWM GND VCC DL GND VCC SRL GND VBST DH DH SRL DL PWM PWM PWM VMID DH GND DH VCC SRH GND SRH Time DH BST = LX + VCC 50 % V LX LX tBBM1 tBBM2 tBBM3 tBBM4 DH , LX DH, LX VMID SRH 50 % DH , LX VCC G ND tBBM3 DL SRL SRL tBBM4 VCC G ND tBBM1 tBBM2 Figure 3. www.vishay.com 6 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix PIN CONFIGURATION Si9122EDQ (TSSOP-20) VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 BST DH LX DL PGND SRH SRL SS BBM CL_CONT VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 Top View Top View 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Si9122EDLP (MLP65-20) BST DH LX DL PGND SRH SRL SS BBM CL_CONT ORDERING INFORMATION Part Number Si9122EDQ-T1-E3 Si9122EDLP-T1-E3 Temperature Range - 40 °C to 85 °C Package TSSOP-20 MLP65-20 Eval Board Contact Factory Temperature Range - 10 °C to 70 °C Board Type Surface Mount and Thru-Hole PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 CL_CONT BBM SS SRL SRH PGND DL LX DH BST Input supply voltage for the start-up circuit Control signal for an external pass transistor Supply voltage for internal circuitry 3.3 V reference Ground External resistor connection to oscillator Voltage control input VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET falls below preset threshold voltages and provides the feed forward voltage. Current limit amplifier negative input Current limit amplifier positive input Current limit compensation Programmable Break-Before-Make time connection to an external resistor to set time delay Soft-Start control - external capacitor connection Signal transformer drive, sequenced with the primary side. Signal transformer drive, sequenced with the primary side Power ground Low-side gate drive signal - primary High-side source and transformer connection node High-side gate drive signal - primary Bootstrap voltage to drive the high-side n-channel MOSFET switch Document Number: 73866 S-80112-Rev. D, 21-Jan-08 www.vishay.com 7 Si9122E Vishay Siliconix VCC VIN Pre-Regulator + – 12 V VREF Bandgap Reference 3.3 V + – VINDET CL_CONT VREF + – Frequency Foldback Voltage Feedforward VSD 135 °C Temp Protection VSD Clock Clock 132 k 60 k EP – + VREF/2 – + PWM Generator Timer Loop Control Blanking Logic Logic VUV VUVLO OTP VREG 9.1 V VUVLO VUV 9.1 V + – 8.8 V High-Side Primary Driver BST 550 mV High Voltage Interface DH LX ROSC Oscillator OSC VCC Low-Side Primary Driver DL PGND Current Control CS2 CS1 + – 100 mV Gain VCC Synchronous Driver (High) SRH VCC CL_CONT VCC 20 µA Soft-Start SS Enable Synchronous Driver (Low) SRL Si9122E 8V SS BBM GND Figure 4. Detailed Si9122E Block Diagram DETAILED OPTION Start-Up When VINEXT rises above 0 V, the internal pre-regulator begins to charge up the VCC capacitor. Current into the external VCC capacitor is limited to typically 40 mA by the internal DMOS device. When VCC exceeds the UVLO voltage of 8.8 V a soft-start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals VREG. During this period, between VUVLO and VREG, excessive load current will result in VCC falling below VUVLO and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing of the VCC capacitor, bootstrap capacitor and the soft-start capacitor. The value of the VCC capacitor should therefore be chosen to be capable of maintaining switch mode operation until the required VCC current can be supplied from the external circuit (e.g via a power transformer winding and zener regulator). Feedback from the output of the switch mode supply charges VCC above VREG and fully disconnects the pre-regulator, www.vishay.com 8 isolating VCC from VIN. VCC is then maintained above VREG for the duration of switch mode operation. In the event of an over voltage condition on VCC, an internal voltage clamp turns on at 14.5 V to shunt excessive current to GND. Care needs to be taken if there is a delay prior to the external circuit feeding back to the VCC supply. To prevent excessive power dissipation within the IC it is advisable to use an external PNP device. A pin has been incorporated on the IC, (REG_COMP) to provide compensation when employing the external device. In this case the VIN pin is connected to the base of the PNP device and controls the current, while the REG_COMP pin determines the frequency compensation of the circuit. The value of the REG_COMP capacitor cannot be too big, otherwise it will slow down the response of the pre-regulator in the case that fault situations occur and pre-regulator needs to be turned on again. To understand the operation, please refer to figure 5. Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix The soft-start circuit is designed for the dc-dc converter to start-up in an orderly manner and reduce component stresses on the Converter. This feature is programmable by selecting an external CSS. An internal 20 µA current source charges CSS from 0 V to the final clamped voltage of 8 V. In the event of UVLO or shutdown, VSS will be held low (< 1 V) disabling driver switching. To prevent oscillations, a longer soft-start time may be needed for highly capacitive loads and/or high peak output current applications. avoid this, a dedicated break-before-make circuit is included which will generate non-overlapping waveforms for the primary and the secondary drive signals. This is achieved by a programmable timer which delays the on switching of the primary driver relative to the off switching of the related secondary and subsequently delays the on switching of the secondary relative to the off switching of the related primary. Typical variations of BBM times with respect to RBBM and other operating parameters are shown on page 14 and 15. Reference The reference voltage of Si9122E is set at 3.3 V. The reference voltage should be de-coupled externally with 0.1 µF capacitor. The VREF voltage is 0 V in shutdown mode and has 50 mA source capability. Primary High- and Low-Side MOSFET Drivers The drive voltage for the low-side MOSFET switch is provided directly from VCC. The high-side MOSFET however requires the gate voltage to be enhanced above VIN. This is achieved by bootstrapping the VCC voltage onto the LX voltage (the high-side MOSFET source). In order to provide the bootstrapping an external diode and capacitor are required as shown on the application schematic. The capacitor will charge up after the low-side driver has turned on. The switch gatedrive signals DH and DL are shown in figure 3. Voltage Mode PWM Operation Under normal load conditions, the IC operates in voltage mode and generates a fixed frequency pulse width modulated signal to the drivers. Duty cycle is controlled over a wide range to maintain output voltage under line and load variation. Voltage feedforward is also included to take account of variations in supply voltage VIN. In the half-bridge topology requiring isolation between output and input, the reference voltage and error amplifier must be supplied externally, usually on the secondary side. The error information is thus passed to the power controller through an opto-coupling device. This information is inverted, hence 0 V represents the maximum duty cycle, while 2 V represents minimum duty cycle. The error information enters the IC via pin EP, and is passed to the PWM generator via an inverting amplifier. The relationship between Duty cycle and VEP is shown in the Typical Characteristic Graph, Duty Cycle vs. VEP 25 °C , page 12. Voltage feedforward is implemented by taking the attenuated VIN signal at VINDET and directly modulating the duty cycle. At start-up, i.e., once VCC is greater than VUVLO, switching is initiated under soft-start control which increases primary switch on-times linearly from DMIN to DMAX over the soft-start period. Start-up from a VINDET power down is also initiated under soft-start control. Secondary MOSFET Drivers The secondary side MOSFETs are driven from the Si9122E via a center tapped pulse transformer and inverter drivers. The waveforms from SRH and SRL are shown in figure 3. Of importance is the relative voltage between SRH and SRL, i.e. that which is presented across the primary of the pulse transformer. When both potentials of SRL and SRH are equal then by the action of the inverting drivers both secondary MOSFETs are turned on. Oscillator The oscillator is designed to operate at a nominal frequency of 500 kHz. The 500 kHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator and therefore the switching frequency is programmable by attaching a resistor to the ROSC pin. Under overload conditions the oscillator frequency is reduced by the current overload protection to enable a constant current to be maintained into a low impedance circuit. Half Bridge and Synchronous Rectification Timing Sequence The PWM signal generated within the Si9122E controls the low and high-side bridge drivers on alternative cycles. A period of inactivity always results after initiation of the softstart cycle until the soft-start voltage reaches approximately 1.2 V and PWM controlled switching begins. The first bridge driver to switch is always the low-side (DL), as this allows charging of the high-side boost capacitor. The timing and coordination of the drives to the primary and secondary stages is very important and shown in figure 3. It is essential to avoid the situation where both of the secondary MOSFETs are on when either the high or the lowside switch are active. In this situation the transformer would effectively be presented with a short across the output. To Current Limit Current mode control providing constant current operation is achieved by monitoring the differential voltage VCS between the CS1 and CS2 pins, which are connected to a current sense resistor on the primary low-side MOSFET. In the absence of an overcurrent condition, VCS is less than lower current limit threshold VTLCL (typical 100 mV); CL_CONT is pulled up linearly via the 120 µA current source (IPU) and both DL and DH switch at half the oscillator set frequency. When a moderate overcurrent condition occurs (VTLCL < VCS < VTHCL), the CL_CONT capacitor will be discharged at a rate that is proportional to VCS - 100 mV by the IPD current source. Both driver outputs are in frequency fold-back mode and the switching frequency becomes roughly 20 % of www.vishay.com 9 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix normal switching frequency. When a severe overcurrent condition occurs (VTHCL < VCS), the NMOS discharges CL_CONT capacitor immediately at 2 mA rate and the CL_CONT voltage will be clamped to 1.2 V disabling both DL and DH outputs. Before VCS reaches severe overcurrent condition, a lowering of the CL_CONT voltage results in PWM control of the output drive being taken over by the current limit control loop through CL_CONT. Current control initially reduces the switching duty cycle toward the minimum the chip can reach (DMIN). If this duty cycle reduction still cannot lower the load current, then the switching frequency will start to fold back to minimum 1/5 of the nominal frequency. This prevents the on-time of the primary drivers from being reduced to below 100 ns and avoids current tails. If VCS > VTHCL, the switching will then stop. With constant current mode control and frequency foldback, protection of the MOSFET switches is increased. The converter reverts to voltage mode operation immediately when the primary current falls below the limit level, and CL_CONT capacitor is charged up and clamped to 6.5 V. The soft-start function does not apply during current limit period, as this would constitute hiccup mode operation. However, if the divided voltage applied to the VINDET pin is greater than VCC - 0.3 V, the high-side driver, DH, will stop switching until the voltage drops below VCC - 0.3 V. Thus, the resistive tap on the VIN divider must be set to accommodate the normal VCC operating voltage to avoid this condition. Alternatively, a zener clamp diode from VINDET to GND may also be used. Shutdown Mode If VINDET is forced below the lower VSD threshold, the device will enter SHUTDOWN mode. This powers down all unnecessary functions of the controller, ensures that the primary switches are off, and results in a low level current demand from the VIN or VCC supplies. VINEXT REXT VIN 12 V PNP Ext HVDMOS VCC REG_COMP CVCC 0.5 µF Auxillary VCC VIN Voltage Monitor - VINDET The chip provides a means of sensing the voltage of VIN, and withholding operation of the output drivers until a minimum voltage of VREF (3.3 V, 300 mV hysteresis), is achieved. This is achieved by choosing an appropriate resistive tap between the ground and VIN, and comparing this voltage with the reference voltage. When the applied voltage is greater than VREF, the output drivers are activated as normal. VINDET also provides the input to the voltage feedforward function. CEXT 2 nF VREF 14.5 V GND Figure 5. High-Voltage Pre-Regulator Circuit VCC AV + Peak Detect IPU 120 µA (nom) GM VOFFSET CL_CLAMP CL_CONT CS1 CS2 Blank + AV 100 mV + AV AV 150 mV REXT OSC GM IPD 0 to 240 µA (nom) CEXT Figure 6. Current Limit Circuit www.vishay.com 10 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix REDUCTION OF BBM2, 4 AT HIGHER fOSC The start of a switching period is defined as the turning point of the oscillator, marked in Figure 7 as A, with the end of a switching period marked as B. For a half bridge, two switching periods are required for both the primary high-side and low-side drivers to operate as shown in Figure 3. For a given oscillator frequency there is a finite time in which all events from equation (1) have to occur. These are tdt deadtime duration which is a function of VEP, tpd1 is the propagation delay from the PWM to SRL (or SRH ) output going low, tBBM1 (or tBBM3) rise delay, DL (or DH) primary driver on-time, tpd2 is the propagation delay from PWM to DL (or DH) output going low and tBBM2(or tBBM4) fall delay. Figure 7 shows the switching cycle for the low side primary driver and associated synchronous driver and equation (1) shows the switching time components. At 500 kHz and maximum duty tpd2 is typically 60 ns. Tswitch = 1/2tdt + tpd1+ tSRLOFF + 1/2tdt - tpd2- tBBM2 A MAX To mitigate the decrease in set tBBM2 and tBBM4, the following criteria must be met. The set tBBM2 plus its associated tpd2 must not exceed 3.4 % of the oscillator period. The typical tBBM2 and tBBM4 delays are provided in figure 9 to facilitate setting these delays for a given frequency with RBBM of 33 kΩ. tBBM2 + tpd2 < 3.4 % of oscillator period (2) tBBM4 + tpd4 < 3.4 % of oscillator period (3) It is critical to avoid the condition where the sum of tBBM2(set) and tpd2 is greater than 6.8 % of oscillator period whereby the correct sequence of logic signals cannot be guaranteed. A B (1) B 1.2 V V EP ½ deadtime ½ deadtime SR L Tpd1 Actual BBM2 Tpd2 1.2 V DL BBM1 Set BBM2 SR L Tpd1 Transition point Figure 8. Components of a Low-Side Switching Period with Maximum Duty and Limited BBM2 Tpd2 60 DL BBM1 BBM4 BBM2 50 Figure 7. Components of a Low-Side Switching Period Delay (ns) Transition point 40 30 BBM2 The Si9122E has an improved primary and secondary duty cycles with typical maximum secondary duty at 93.2 %. Hence the dead-time is 6.8 % or 136 ns at 500 kHz. Half of the dead-time is 68 ns and during this time tpd2 plus tBBM2 has to occur before the next transition point of the oscillator cycle. RBBM contributes 1.2 ns/kΩ to tBBM2; with 33 kΩ this amounts to 40 ns. If tBBM2 is set beyond the transition point, SRL will be forced high due to logic conditions and a reduction in the set tBBM2 will be determined by the half deadtime minus tpd2 and will be independent of the RBBM value as shown in figure 8. Note: this applies to tBBM4 as well. Document Number: 73866 S-80112-Rev. D, 21-Jan-08 20 10 0 150 200 250 300 350 400 450 500 Fosc (kHz) Figure 9. Reduction in BBM2 and BBM4 Si9122E BBM vs. FOSC, VIN = 50 V, VCC = 10 V, BST = 60 V, LX = 50 V, VEP = 0 V www.vishay.com 11 Si9122E Vishay Siliconix TYPICAL CHARACTERISTICS 600 3.300 3.295 500 3.290 FOSC (kHz) V REF (V) 400 3.285 3.280 300 3.275 200 20 30 40 50 ROSC (k ) 60 70 80 3.270 - 50 - 25 0 25 50 75 100 Temperature (°C) FOSC vs. ROSC at VCC = 12 V 10.0 100 90 VREF vs. Temperature, VCC = 12 V 3.6 V = VINDET 9.5 Duty Cycle (%) 80 70 60 50 40 30 8.0 20 10 7.5 - 50 0 0.0 VCC = 12 V 7.2 V 4.8 V V REG(V) 9.0 VINDET 8.5 TC = - 11 mV/C VREF - 25 0 25 50 75 100 125 150 0.5 1.0 VEP (V) 1.5 2.0 Temperature (°C) VREG vs. Temperature, VIN = 48 V 25 VCC = 13 V 23 VCC = 12 V V SS (V) 21 8.20 SRL, SRH Duty Cycle vs. VEP 8.15 TC = + 1.25 mV/C 8.10 VINDET VREF I SS1 (uA) 8.05 19 8.00 VCC = 10 V 17 7.95 15 - 50 - 25 0 25 50 75 100 125 7.90 - 50 - 25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) ISS vs. Temperature VSS vs. Temperature, V = 12 V www.vishay.com 12 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix TYPICAL CHARACTERISTICS 11 13 10 12 9 IREG2 (mA) ICC3 (mA) 11 8 10 7 9 6 8 5 - 50 - 25 0 25 50 75 100 7 - 50 - 25 0 25 50 75 100 Temperature (°C) Temperature (°C) IREG2 vs. Temperature, VCC = 12 V 250 250 ICC3 vs. Temperature VCC = 12 V 200 VCC = 12 V 200 VCC = 12 V I SOURCE (mA) ISINK (mA) 150 150 100 100 50 50 0 0 200 400 VOH (mV) 600 800 0 0 200 400 VOL (mV) 600 800 DH, DL ISOURCE vs. VOH 35 30 VCC = 12 V 25 ISOURCE (mA) ISINK (mA) 20 15 10 5 0 0 200 400 VOH (mV) 600 800 25 20 15 10 5 0 0 200 35 30 DH, DL ISINK vs. VOL VCC = 12 V 400 VOL (mV) 600 800 SRL, SRH ISOURCE vs. VOH SRL, SRH ISINK vs. VOL Document Number: 73866 S-80112-Rev. D, 21-Jan-08 www.vishay.com 13 Si9122E Vishay Siliconix TYPICAL CHARACTERISTICS 100 90 80 tBBM4 70 tBBM (ns) tBBM (ns) 60 50 40 25 30 20 25 30 35 RBBM (k ) 40 45 15 25 30 35 RBBM (k ) 40 45 45 tBBM3 35 tBBM2 VCC = 12 V tBBM1 55 65 VCC = 12 V tBBM4 tBBM1 tBBM3 tBBM2 tBBM vs. RBBM, VEP = 0 V, VLX = 48 V, BST = 60 V, VINDET = 4.8 V, fOSC < 200 kHZ 80 tBBM1, VCC = 13 V tBBM1, VCC = 12 V 70 tBBM1, VCC = 10 V tBBM1, 2 (ns) 60 VEP = 0 V RBBM = 33 k 50 tBBM2, VCC = 10 V 40 tBBM2, VCC = 13 V 30 - 50 - 25 0 25 50 75 100 125 tBBM1, 2 (ns) 55 60 tBBM vs. RBBM, VEP = 1.65 V, VLX = 48 V, BST = 60 V, VINDET = 4.8 V VEP = 1.65 V RBBM = 33 k tBBM1, VCC = 10 V 50 tBBM1, VCC = 13 V tBBM1, VCC = 12 V 40 tBBM2, VCC = 12 V 35 tBBM2, VCC = 10 V tBBM2, VCC = 12 V tBBM2, VCC = 13 V 30 - 50 45 - 25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) tBBM1, 2 vs. Temperature, VEP = 0 V, fOSC < 200 kHz 70 65 60 55 50 45 40 35 30 - 50 tBBM3, VCC = 10 V - 25 0 25 50 75 100 125 20 - 50 tBBM4, VCC = 12 V tBBM 3, 4 (ns) tBBM4, VCC = 13 V 60 VEP = 0 V RBBM = 33 k tBBM4, VCC = 10 V fosc < 200 kHz 80 tBBM1, 2 vs. Temperature, VEP = 1.65 V VEP = 1.65 V RBBM = 33 k 70 tBBM4, VCC = 13 V tBBM4, VCC = 12 V tBBM4, VCC = 10 V tBBM 3, 4 (ns) 50 tBBM3, VCC = 13 V tBBM3, VCC = 12 V 40 tBBM3, VCC = 10 V 30 tBBM3, VCC = 13 V tBBM3, VCC = 12 V - 25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) tBBM3, 4 vs. Temperature, VEP = 0 V, fosc < 200 kHz www.vishay.com 14 tBBM3, 4 vs. Temperature, VEP = 1.65 V Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Si9122E Vishay Siliconix TYPICAL CHARACTERISTICS 80 tBBM1, VCC = 13 V 70 tBBM1, VCC = 12 V 55 tBBM1, VCC = 13 V 50 tBBM1, 2 (ns) tBBM1, VCC = 12 V tBBM1, VCC = 10 V 45 VEP = 1.65 V 40 tBBM2, VCC = 12 V tBBM2, VCC = 13 V tBBM1, VCC = 10 V tBBM1, 2 (ns) 60 VEP = 0 V 50 tBBM2, VCC = 10 V 40 tBBM2, VCC = 12 V 30 3.5 4.5 5.5 VINDET (V) tBBM2, VCC = 13 V 6.5 7.5 35 3.5 tBBM2, VCC = 10 V 4.5 5.5 VINDET (V) 6.5 7.5 tBBM1, 2 vs. VCC vs. VINDET, fOSC < 200 kHz 80 VEP = 0 V 70 LX = 48 V, BST = 60 V tBBM4, VCC = 12 V tBBM4, VCC = 10 V tBBM 3, 4 (ns) tBBM 3, 4 (ns) 60 tBBM4, VCC = 13 V 50 tBBM3, VCC = 10 V 40 35 30 3.5 tBBM3, VCC = 13 V 4.5 5.5 VINDET (V) 6.5 7.5 30 3.5 tBBM3, VCC = 12 V 60 65 tBBM1, 2 vs. VCC vs. VINDET tBBM4, VCC = 10 V LX = 48 V, BST = 60 V tBBM4, VCC = 12 V 55 tBBM4, VCC = 13 V 50 45 40 VEP = 1.65 V tBBM3, VCC = 12 V tBBM3, VCC = 13 V tBBM3, VCC = 10 V 4.5 5.5 VINDET (V) 6.5 7.5 tBBM3, 4 vs. VCC vs. VINDET, fOSC < 200 kHz 60 Frequency VROSC (V), FOSC (kHz), Duty Cycle (%) 50 I OUT, Duty Cycle %. V OUT D% Frequency (kHz) 40 300 30 200 20 IOUT 10 VOUT 0 0.0 0 1.0 100 400 500 50 45 40 tBBM3, 4 vs. VCC vs. VINDET 500 Frequency 400 D% 35 Frequency (kHz) 30 25 20 15 10 5 0 1 2 3 VC L_CONT (V) 4 5 VR OSC 0 100 DDL DSR L 200 300 0.2 0.4 0.6 0.8 RLOAD ( ) IOUT vs. RLOAD (VIN = 72 V) VROSC, FOSC, and Duty Cycle vs. VCL_CONT Document Number: 73866 S-80112-Rev. D, 21-Jan-08 www.vishay.com 15 Si9122E Vishay Siliconix TYPICAL WAVEFORMS SR L10 V/div SR L10 V/div IOUT 5 A /div DL 10 V/div IOUT 5 A /div DL 5 V/div CS2 5 V/div CS2 50 mV/div 2 µs/div 2 µs/div Figure 10. Foldback Mode, RL = 0.02 Ω Figure 11. Normal Mode, RL = 0.1 Ω VIN 2 V/div VCL 2 V/div VEP 2 V/div IOUT 10 A/div VOUT 2 V/div VCC 2 V/div 2 ms/div 200 µs/div Figure 12. VCC Ramp-Up DH 5 V/div LX 20 V/div SRL 5 V/div Figure 13. Overload Recovery DL 5 V/div SRH 2 V/div SRH 5 V/div SR L 2 V/div 500 ns/div 500 ns/div Figure 14. Effective BBM - Measured On Secondary Figure 15. Drive Waveforms Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73866. www.vishay.com 16 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Package Information Vishay Siliconix TSSOP: 20-LEAD (POWER IC ONLY) B D N 4X 0.20 C A−B 0.20 H A−B E1 E 1.00 2X N/2 TIPS D D b bbb M C A−B D 9 0.05 C E/2 A2 A C 123 1.00 DIA. 1.00 (14_) A H e aaa A1 D SIDE VIEW SEATING PLANE C MILLIMETERS 0.25 + + H L 6 c 1.00 (14_) DETAIL ‘A’ (SCALE: 30/1) (VIEW ROTATED 90_ C.W.) C L B B PARTING LINE (∝) e/2 X X = A and B Dim A A1 A2 aaa b b1 bbb c c1 D E E1 e L N P P1 ∝ Min — 0.05 0.85 0.19 0.19 0.09 0.09 Nom — — 0.90 0.076 − 0.22 0.10 − 0.127 6.50 BSC 6.40 BSC Max 1.10 0.15 0.95 0.30 0.25 0.20 0.16 4.30 0.50 4.40 0.65 BSC 0.60 20 4.2 3.0 4.50 0.70 0_ — 8_ SEE DETAIL ‘A’ END VIEW ECN: S-40082—Rev. A, 02-Feb-04 DWG: 5923 LEAD SIDES TOP VIEW Document Number: 72818 28-Jan-04 www.vishay.com 1 Package Information Vishay Siliconix PowerPAKr MLP65-18/20 (POWER IC ONLY) -B- D D/2 -AIndex Area D/2 E/2 NXb 2x E/2 E E2/2 2.00 E2 NXb bbb M A B C aaa C Index Area D/2 E/2 aaa C 2x NXL Detail D D2 D2/2 TOP VIEW BOTTOM VIEW A // ccc C A3 SEATING NX 0.08 C A1 SIDE VIEW PLANE -C- # IDENTIFIER TYPE A Chamber e/2 Terminal Tip e 5 EVEN TERMINAL SIDE DETAIL B e Terminal Tip 5 ODD TERMINAL SIDE Document Number: 73182 15-Oct-04 www.vishay.com 1 Package Information Vishay Siliconix PowerPAK MLP65-18/20 (POWER IC ONLY) N = 18/20 PITCH: 0.5 mm, BODY SIZE: 6.00 x 5.00 MILLIMETERS* Dim Min Nom Max 1.00 0.05 1.00 − 0.30 − − − 4.25 3.25 − 0.65 INCHES Min 0.031 0.000 0.000 − 0.007 − − − 0.157 0.118 − 0.018 Nom 0.035 0.001 0.003 0.008 REF 0.006 0.010 0.004 0.009 0.004 0.236 BSC 1.63 0.197 BSC 0.124 0.020 0.022 18, 20 9 0 10 0 Max 0.039 0.002 0.004 − 0.012 − − − 0.167 0.128 − 0.026 Notes 1, 2 1, 2 1, 2 A 0.80 0.90 A1 0.00 0.02 A2 0.00 0.65 A3 0.20 REF aaa − 0.15 b 0.18 0.25 bbb − 0.10 C’ − 0.225 ccc − 0.10 D 6.00 BSC D2 4.00 4.15 E 5.00 BSC E2 3.00 3.15 e − 0.50 L 0.45 0.55 N 18, 20 ND(18) 9 NE(18) 0 ND(20) 10 NE(20) 0 * Use millimeters as the primary measurement. ECN: S-41946—Rev. A, 18-Oct-04 DWG: 5939 8 4, 10 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All dimensions are in millimeters. All angels are in degrees. N is the total number of terminals. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95 SSP-022. Details of terminal #1 identifier are optional, but must be located within the zone indicated. A dot can be marked on the top side by pin 1 to indicate orientation. ND and NE refer to the number of terminals on the D and E side respectively. Depopulation is possible in a symmetrical fashion. NJR refers to NON JEDEC REGISTERED. Dimension “b” applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has optional radius on the other end of the terminal, the dimension “b” should not be measured in that radius area. Coplanarity applies to the exposed heat slug as well as the terminal. The 45_ chamfer dimension C’ is located by pin 1 on the bottom side of the package. www.vishay.com 2 Document Number: 73182 15-Oct-04 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1