W27C512-45Z

W27C512 64K × 8 ELECTRICALLY ERASABLE EPROM Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 2 2. FEATURES ................................................................................................................................. 2 3. PIN CONFIGURATIONS ............................................................................................................ 3 4. BLOCK DIAGRAM ...................................................................................................................... 4 5. PIN DESCRIPTION..................................................................................................................... 4 6. FUNCTIONAL DESCRIPTION ................................................................................................... 5 7. TABLE OF OPERATING MODES .............................................................................................. 7 8. DC CHARACTERISTICS............................................................................................................ 8 9. CAPACITANCE........................................................................................................................... 9 10. AC CHARACTERISTICS ............................................................................................................ 9 11. READ OPERATION DC CHARACTERISTICS ........................................................................ 10 12. READ OPERATION AC CHARACTERISTICS......................................................................... 10 13. DC PROGRAMMING CHARACTERISTICS............................................................................. 11 14. AC PROGRAMMING/ERASE CHARACTERISTICS................................................................ 12 15. TIMING WAVEFORMS ............................................................................................................. 13 16. SMART PROGRAMMING ALGORITHM 1 ............................................................................... 15 17. SMART PROGRAMMING ALGORITHM 2 ............................................................................... 16 18. SMART ERASE ALGORITHM.................................................................................................. 17 19. ORDERING INFORMATION .................................................................................................... 18 20. PACKAGE DIMENSIONS ......................................................................................................... 19 21. VERSION HISTORY ................................................................................................................. 20 -1- Publication Release Date: January 9, 2006 Revision A6 W27C512 1. GENERAL DESCRIPTION The W27C512 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27C512 provides an electrical chip erase function. 2. FEATURES y High speed access time: 45/70/90/120 nS (max.) y Read operating current: 30 mA (max.) y Erase/Programming operating current: 30 mA (max.) y Standby current: 1 mA (max.) y Single 5V power supply y +14V erase/+12V programming voltage y Fully static operation y All inputs and outputs directly TTL/CMOS compatible y Three-state outputs y Available packages: 28-pin 600 mil DIP, 330 mil 32-pin PLCC -2- W27C512 3. PIN CONFIGURATIONS A15 1 28 V CC A12 2 27 A14 A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 A2 8 OE/Vpp A10 A1 9 20 A0 10 19 CE Q7 Q0 11 18 Q6 Q1 12 17 Q5 Q2 13 16 Q4 14 15 Q3 GND A6 A5 A4 A3 A2 A1 A0 NC Q0 5 6 7 8 9 10 11 12 13 28-pin DIP 21 A 7 A 1 2 A 1 5 N C V C C A 1 4 A 1 3 4 3 2 1 3 2 3 1 3 0 32-pin PLCC 1 4 Q 1 1 5 Q 2 1 6 1 7 G N D N C 1 8 Q 3 -3- 1 9 2 0 Q 4 Q 5 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE/Vpp A10 CE Q7 Q6 Publication Release Date: January 9, 2006 Revision A6 W27C512 4. BLOCK DIAGRAM CE OE/V OUTPUT BUFFER CONTROL PP Q7 A0 . CORE DECODER ARRAY . A15 V CC GND 5. PIN DESCRIPTION SYMBOL DESCRIPTION A0−A15 Address Inputs Q0−Q7 Data Inputs/Outputs CE OE /VPP Chip Enable Output Enable, Program/Erase Supply Voltage VCC Power Supply GND Ground NC Q0 . . No Connection -4- W27C512 6. FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE /VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE /VPP, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when OE /VPP is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0 low, and all other address pins low and data input pins high. Pulsing CE low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if VCC = VCE (3.75V), CE low, and OE /VPP low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when OE /VPP is raised to VPP (12V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if OE /VPP low and CE low. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the CE and OE /VPP pins, the W27C512 may have common inputs. -5- Publication Release Date: January 9, 2006 Revision A6 W27C512 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE /VPP. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C512 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE . Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 μ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 μF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. -6- W27C512 7. TABLE OF OPERATING MODES (VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL) MODE PINS CE OE /VPP A0 A9 VCC Read VIL VIL X X VCC DOUT Output Disable VIL VIH X X VCC High Z Standby (TTL) VIH X X X VCC High Z VCC ±0.3V X X X VCC High Z Program VIL VPP X X VCP DIN Program Verify VIL VIL X X VCC DOUT Program Inhibit VIH VPP X X VCP High Z Erase VIL VPE VIL VPE VCE DIH Erase Verify VIL VIL X X 3.75 DOUT Erase Inhibit VIH VPE X X VCE High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC DA (Hex) Product Identifier-device VIL VIL VIH VHH VCC 08 (Hex) Standby (CMOS) -7- OUTPUTS Publication Release Date: January 9, 2006 Revision A6 W27C512 8. DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT 0 to +70 °C -65 to +125 °C -0.5 to VCC +0.5 V Voltage on OE /VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V -0.5 to +7 V Operation Temperature Storage Temperature Voltage on all Pins with Respect to Ground Except OE /VPP, A9 and VCC Pins Voltage VCC Pin with Respect to Ground Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ±5%) PARAMETER SYM. LIMITS CONDITIONS UNIT MIN. TYP. MAX. -10 - 10 μA Input Load Current ILI VIN = VIL or VIH VCC Erase Current ICP CE = VIL, OE /VPP = VPE - - 30 mA VPP Erase Current IPP CE = VIL, OE /VPP = VPE - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - - A9 Erase Voltage VID - 13.75 14 14.25 V VPP Erase Voltage VPE - 13.75 14 14.25 V VCC Supply Voltage (Erase) VCE - 4.75 5.0 5.25 V VCC Supply Voltage (Erase Verify) VCE - 3.5 3.75 4.0 V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -8- W27C512 9. CAPACITANCE (VCC = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF 10. AC CHARACTERISTICS AC Test Conditions CONDITIONS PARAMETER 45/70 NS 90/120 NS Input Pulse Levels 0 to 3.0V 0.45V to 2.4V Input Rise and Fall Times 5 nS 10 nS Input and Output Timing Reference Level 1.5V/1.5V 0.8V/2.0V Output Load CL = 30 pF, IOH/IOL = -0.4 mA/2.1 mA CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA AC Test Load and Waveforms +1.3V (IN914) 3.3K ohm D OUT 100 pF for 90/120 nS (Including Jig and Scope) 30 pF for 45/70 nS (Including Jig and Scope) Output Input Test Points Test Points 2.4V For 90/120 nS 0.45V 2.0V 2.0V 0.8V 0.8V Output Input Test Point Test Point 3.0V 1.5V For 45/70 nS 1.5V 0V -9- Publication Release Date: January 9, 2006 Revision A6 W27C512 11. READ OPERATION DC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 70° C) PARAMETER SYM. LIMITS CONDITIONS MIN. UNIT TYP. MAX. Input Load Current ILI VIN = 0V to VCC -5 - 5 μA Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 Standby VCC Current (TTL input) Standby VCC Current (CMOS input) VCC Operating Current ISB CE = VIH - - 1.0 μA mA ISB1 CE = VCC ±0.3V - 5 100 μA ICC - - 30 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIL VIH VOL VOH CE = VIL IOUT = 0 mA, f = 5 MHz IOL = 2.1 mA IOH = -0.4 mA -0.3 2.2 2.4 - 0.8 VCC +0.5 0.45 - V V V V 12. READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 70° C) PARAMETER SYM. W27C512-45 W27C512-70 W27C512-90 W27C512-12 MIN. MAX. MIN. MAX. MIN. MAX. MIN. UNIT MAX. Read Cycle Time TRC 45 - 70 - 90 - 120 - nS Chip Enable Access Time TCE - 45 - 70 - 90 - 120 nS Address Access Time TACC - 45 - 70 - 90 - 120 nS Output Enable Access Time TOE - 20 - 30 - 40 - 55 nS OE /VPP High to High-Z Output TDF - 20 - 30 - 30 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - 0 - nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. - 10 - W27C512 13. DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. LIMITS CONDITIONS VIN = VIL or VIH UNIT MIN. TYP. MAX. -10 - 10 μA - - 30 mA - - 30 mA Input Load Current ILI VCC Program Current ICP VPP Program Current IPP Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.75 5.0 5.25 V CE = VIL, OE / VPP = VPP CE = VIL, OE / VPP = VPP - 11 - Publication Release Date: January 9, 2006 Revision A6 W27C512 14. AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER LIMITS SYM. UNIT MIN. TYP. MAX. OE /VPP Pulse Rise Time TPRT 50 - - nS Data Setup Time TDS 2.0 - - μS CE Program Pulse Width TPWP 95 100 105 μS CE Erase Pulse Width TPWE 95 100 105 mS Data Hold Time TDH 2.0 - - μS OE /VPP Setup Time TOES 2.0 - - μS OE /VPP Hold Time TOEH 2.0 - - μS Data Valid from CE TDV1 25 - 1 μS Data Valid from Address Change TDV2 25 - 1 μS CE High to Output High Z TDFP 0 - 130 nS Address Setup Time TAS 2.0 - - μS Address Hold Time TAH 0 - - μS Address Hold Time after CE High (Erase) TAHC 2.0 - - μS OE /VPP Valid after CE High TVS 2.0 - - μS OE /VPP Recovery Time TVR 2.0 - - μS Address Access Time During Erase Verify (VCC = 3.75V) TACV - - 250 nS Output Enable Access Time during Erase Verify (VCC = 3.75V) TOEV - - 150 nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. - 12 - W27C512 15. TIMING WAVEFORMS AC Read Waveform V IH Address Address Valid V IL V IH CE V IL TCE V IH OE/Vpp TDF V IL TOE TOH TACC High Z Outputs Valid Output High Z Erase Waveform Read Company SID Read Device SID A9 = 12.0V Blank Check Read Verify Erase Verify Chip Erase A9 = 14.0V Others = IL V Address VIH VIL A0 = VI L TACC Data Others = IL V A0 = V IH Others = IL V Address Valid TACC TAS 08 DA TACV =250 nS TAHC TDH 5V Address Valid TACV =250 nS DOUT Data All One TDS Vcc Address Valid Address Valid TACC DOUT DOUT TVCS 3.75V TOES 14.0V TOE TOE TOEV = 150 nS VIH OE/Vpp VIL VIH CE V IH VIH TOE TOEH TCE TPRT TVS Always = IL V VIL TPWE TVR - 13 - Publication Release Date: January 9, 2006 Revision A6 W27C512 Timing Waveforms, continued Programming Waveform Program Program Verify Read Verify VIH Address Stable Address Stable Address V IL TAH TAS TAS Address Stable Address Valid Address Valid TOH TAH TDFP VIH V IL TDS Data Out Data In Stable Data In Stable Data TDH TDS TACC TDH TDV1 12.0V OE/Vpp V IH VIL TOES TOEH TDV2 VIL TPRT TOE TVR TPWP CE Data Out V IH VIL V IL CE should not be toggled during program verify period - 14 - TCE TOH W27C512 16. SMART PROGRAMMING ALGORITHM 1 Start Address = First Location Vcc = 5.0V OE/Vpp = 12V Program One 100 μS Pulse Increment Address No Last Address? Yes Address = First Location Increment Address X=0 No Last Address? Pass Fail Verify Byte Increment X No Program One 100 μS Pulse X = 25 ? Yes Vcc = 5.0V OE/Vpp = VIL Yes Compare All Bytes to Original Data Fail Device Failed Pass Device Passed - 15 - Publication Release Date: January 9, 2006 Revision A6 W27C512 17. SMART PROGRAMMING ALGORITHM 2 Start Address = First Location Vcc = 5.0V X=0 Program One 100 μS Pulse OE/VPP = 12V Increment X X = 25? Yes No Fail Verify One Byte OE/VPP = VIL Verify One Byte OE/VPP = VIL Pass Increment Address Fail Pass No Last Address ? Yes Compare All Bytes to Original Data Fail Pass Device Passed - 16 - Device Failed W27C512 18. SMART ERASE ALGORITHM Start X=0 Vcc = 5V OE/Vpp = 14V A9 = 14V; A0 = V IL Chip Erase 100 mS Pulse Address = First Location Increment X Vcc = 3.75V OE/Vpp = V IL No Erase Verify Fail X = 20 ? Pass Yes Increment Address No Last Address? Yes Vcc = 5V OE/Vpp = VIL Compare All Bytes to FFs (HEX) Fail Pass Pass Device Fail Device - 17 - Publication Release Date: January 9, 2006 Revision A6 W27C512 19. ORDERING INFORMATION ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (μA) W27C512-45 45 30 100 600 mil DIP W27C512-70 70 30 100 600 mil DIP W27C512-90 90 30 100 600 mil DIP W27C512-12 120 30 100 600 mil DIP W27C512P-45 45 30 100 32-pin PLCC W27C512P-70 70 30 100 32-pin PLCC W27C512P-90 90 30 100 32-pin PLCC W27C512P-12 120 30 100 32-pin PLCC W27C512-45Z 45 30 100 600 mil DIP Lead Free W27C512P-45Z 45 30 100 32-pin PLCC Lead Free PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 18 - W27C512 20. PACKAGE DIMENSIONS 28-pin P-DIP Dimension in Inches Symbol A A1 A2 B B1 c D E E1 e1 L D 28 15 eA S Min. Nom. Max. 5.33 0.210 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.058 0.060 0.064 1.47 1.52 1.63 0.008 0.010 0.014 0.20 0.25 0.36 1.460 1.470 37.08 37.34 0.590 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0 a E1 Dimension in mm Min. Nom. Max. 0.630 0.650 15 0.090 2.29 Notes: 1 14 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. E S c A A2 A1 L Base Plane Seating Plane B e1 eA a B1 32-pin PLCC HE E 4 1 32 30 Dimension in Inches Symbol 5 29 GD D HD 21 13 14 c 20 A A1 A2 b1 b c D E e GD GE HD HE L y θ Min. Nom. Max. Dimension in mm Min. Nom. Max. 3.56 0.140 0.50 0.020 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.10 0.004 0 10 0 10 Notes: L A2 θ e b b1 Seating Plane GE 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection spec. A A1 y - 19 - Publication Release Date: January 9, 2006 Revision A6 W27C512 21. VERSION HISTORY VERSION DATE A1 Mar. 1998 A2 Sep. 1998 PAGE Initial Issued 6 4,6 A3 Aug. 1999 DESCRIPTION 1, 5, 6, 13 2, 3 Correct Imput High Voltage (VIH) from 2.0 (min) to 2.2 (max) Correct VCC from 5.0 ±10% to 5.0 ±5% Add 45 nS bining Modify function description (VIL and VIH): VIL → Low; VIH → High A4 Nov. 1999 6 Typo correction A5 April 14, 2005 15 Adding important notice A6 Jan. 9, 2006 18 Ordering Information:Add W27C512-45Z and W27C512P-45Z Lead free part Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 20 -