W29EE011
128K × 8 CMOS FLASH MEMORY
Table of Contents1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS............................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................... 5
PIN DESCRIPTION..................................................................................................................... 5
FUNCTIONAL DESCRIPTION.................................................................................................... 6
6.1
Read Mode ..................................................................................................................... 6
6.2
Page Write Mode ............................................................................................................ 6
6.3
Software-protected Data Write ....................................................................................... 6
6.4
Hardware Data Protection .............................................................................................. 7
6.5
Data Polling (DQ7)-Write Status Detection .................................................................... 7
6.6
Toggle Bit (DQ6)-Write Status Detection........................................................................ 7
6.7
5-Volt-only Software Chip Erase..................................................................................... 7
6.8
Product Identification ...................................................................................................... 7
TABLE OF OPERATING MODES .............................................................................................. 8
7.1
Operating Mode Selection .............................................................................................. 8
7.2
Command Codes for Software Data Protection ............................................................. 8
7.2.1
7.3
Command Codes for Software Chip Erase .................................................................. 10
7.3.1
7.4
Software Product Identification Acquisition Flow ....................................................11
ELECTRICAL CHARACTERISTICS......................................................................................... 12
8.1
Absolute Maximum Ratings .......................................................................................... 12
8.2
DC Characteristics ........................................................................................................ 12
8.2.1
8.2.2
8.2.3
8.3
Operating Characteristics .......................................................................................12
Power-up Timing ....................................................................................................12
Capacitance............................................................................................................13
AC Characteristics ........................................................................................................ 13
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
9.
Software Chip Erase Acquisition Flow....................................................................10
Command Codes for Product Identification.................................................................. 11
7.4.1
8.
Software Data Protection Acquisition Flow ...............................................................9
AC Test Conditions.................................................................................................13
AC Test Load and Waveforms................................................................................13
Read Cycle Timing Parameters..............................................................................14
Byte/Page-write Cycle Timing Parameters .............................................................14
Data Polling and Toggle Bit Timing Parameters .....................................................15
TIMING WAVEFORMS ............................................................................................................. 16
9.1
Read Cycle Timing Diagram......................................................................................... 16
9.2
#WE Controlled Write Cycle Timing Diagram............................................................... 16
9.3
#CE Controlled Write Cycle Timing Diagram ............................................................... 17
-1-
Publication Release Date: April 11, 2006
Revision A18
W29EE011
10.
11.
12.
13.
Page Write Cycle Timing Diagram................................................................................ 17
9.4
9.5
#DATA Polling Timing Diagram .................................................................................... 18
9.6
Toggle Bit Timing Diagram ........................................................................................... 18
9.7
Page Write Timing Diagram Software Data Protection Mode ...................................... 19
9.8
Reset Software Data Protection Timing Diagram......................................................... 19
9.9
5 Volt-only Software Chip Erase Timing Diagram ........................................................ 20
ORDERING INFORMATION..................................................................................................... 21
HOW TO READ THE TOP MARKING...................................................................................... 22
PACKAGE DIMENSIONS ......................................................................................................... 23
12.1 32-pin P-DIP ................................................................................................................. 23
12.2 32-pin PLCC ................................................................................................................. 23
12.3 32-pin TSOP (8 x 20 mm)............................................................................................. 24
12.4 32-pin STSOP (8 x 14 mm) .......................................................................................... 24
VERSION HISTORY ................................................................................................................. 25
-2-
W29EE011
1. GENERAL DESCRIPTION
The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29EE011 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
y
y
Single 5-volt program and erase operations
Fast page-write operations
− 128 bytes per page
− Page program cycle: 10 mS (max.)
− Effective byte-program cycle time: 39 µS
− Optional software-protected data write
y
y
y
y
y
y
Fast chip-erase operation: 50 mS
Read access time: 90/150 nS
Page program/erase cycles: 1K/10K
Ten-year data retention
Software and hardware data protection
Low power consumption
y
y
− Active current: 25 mA (typ.)
− Standby current: 20 µA (typ.)
Automatic program timing with internal VPP generation
End of program detection
y
y
y
y
− Toggle bit
− Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP, 32-pin TSOP (8 x 20 mm), 32-pin STSOP
(8 x 14 mm), 32-pin PLCC, and Lead-free 32-pin PLCC
-3-
Publication Release Date: April 11, 2006
Revision A18
W29EE011
3. PIN CONFIGURATIONS
NC
1
32
V DD
A16
2
31
#WE
A15
3
30
NC
A12
4
29
A14
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
A3
32-pin
DIP
25
A11
9
24
#OE
A2
10
23
A10
A1
11
22
#CE
A0
12
21
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
GND
16
17
DQ3
A
1
2
A
1
5
A
1
6
N
C
V
D
D
#
W
E
N
C
4
3
2
1
32
31
30
A7
5
29
A14
A6
6
28
A13
A5
7
27
A8
A4
8
A3
9
A2
A1
32-pin
PLCC
26
A9
25
A11
10
24
#OE
11
23
A10
A0
12
22
#CE
DQ0
13
21
DQ7
14
15
16
17
18
19
20
D
Q
1
D
Q
2
G
N
D
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A11
A9
A8
A13
A14
NC
1
2
6
27
#WE
V DD
NC
A16
A15
A12
A7
A6
A5
A4
7
26
25
32
31
3
30
4
5
29
8
9
10
28
32-pin
TSOP
11
12
24
23
22
21
20
13
14
19
15
18
17
16
-4-
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
W29EE011
4. BLOCK DIAGRAM
VDD
GND
#CE
#OE
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
#WE
DQ0
.
.
DQ7
A0
.
.
A16
5. PIN DESCRIPTION
SYMBOL
A0 − A16
DQ0 − DQ7
PIN NAME
Address Inputs
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
VDD
Power Supply
GND
Ground
NC
No Connection
-5-
Publication Release Date: April 11, 2006
Revision A18
W29EE011
6. FUNCTIONAL DESCRIPTION
6.1 Read Mode
The read operation of the W29EE011 is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is
de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for further details.
6.2
Page Write Mode
The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device. Step 2 is an internal programming cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200
µS, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes can
then be loaded consecutively. The page load cycle will be terminated and the internal programming
cycle will start if no additional byte is loaded into the page buffer within 300 µS (TBLCO) from the last
byte-load cycle, i.e., there is no subsequent #WE high-to-low transition after the last rising edge of
#WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer must have the
same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any
order; sequential loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.
6.3
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up and power-down.
The W29EE011 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
required. See Table 3 for specific codes and Figure 10 for the timing diagram.
-6-
W29EE011
6.4
Hardware Data Protection
The integrity of the data stored in the W29EE011 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 3.8V.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
6.5
Data Polling (DQ7)-Write Status Detection
The W29EE011 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE011 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during
the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is
completed. DQ7 will show the true data.
6.6
Toggle Bit (DQ6)-Write Status Detection
In addition to data polling, the W29EE011 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.
6.7
5-Volt-only Software Chip Erase
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.
6.8
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C1h). The product ID operation can be terminated by a three-byte command sequence.
In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
-7-
Publication Release Date: April 11, 2006
Revision A18
W29EE011
7. TABLE OF OPERATING MODES
7.1 Operating Mode Selection
Operating Range = 0 to 70°C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V
MODE
PINS
#CE
#OE
#WE
ADDRESS
Read
VIL
VIL
VIH
AIN
Dout
Write
VIL
VIH
VIL
AIN
Din
Standby
VIH
X
X
X
High Z
X
VIL
X
X
High Z/DOUT
X
X
VIH
X
High Z/DOUT
X
VIH
X
X
High Z
5-Volt Software Chip
Erase
VIL
VIH
VIL
AIN
Product ID
VIL
VIL
VIH
A0 = VIL; A1 − A16 = VIL; Manufacturer Code DA
(Hex)
A9 = VHH
VIL
VIL
VIH
A0 = VIH; A1 − A16 = VIL; Device Code
C1 (Hex)
A9 = VHH
Write Inhibit
Output Disable
7.2
DQ.
DIN
Command Codes for Software Data Protection
BYTE SEQUENCE
TO ENABLE PROTECTION
ADDRESS
TO DISABLE PROTECTION
DATA
ADDRESS
DATA
AAH
5555H
AAH
0 Write
5555H
1 Write
2AAAH
55H
2AAAH
55H
2 Write
5555H
A0H
5555H
80H
3 Write
-
-
5555H
AAH
4 Write
-
-
2AAAH
55H
5 Write
-
-
5555H
20H
-8-
W29EE011
7.2.1 Software Data Protection Acquisition Flow
Software Data Protection
Enable Flow
(Optional page
load operation)
Software Data Protection
Disable Flow
Load data AA
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data 80
to
address 5555
Sequentially load
up to 128 bytes
of page data
Load data AA
to
address 5555
Pause 10 mS
Load data 55
to
address 2AAA
Exit
Load data 20
to
address 5555
Pause 10 mS
Exit
Notes for software program code:
Data Format: DQ7 − DQ0 (Hex)
Address Format: A14 − A0 (Hex)
-9-
Publication Release Date: April 11, 2006
Revision A18
W29EE011
7.3
Command Codes for Software Chip Erase
BYTE SEQUENCE
ADDRESS
0 Write
5555H
AAH
1 Write
2AAAH
55H
2 Write
5555H
80H
3 Write
5555H
AAH
4 Write
2AAAH
55H
5 Write
5555H
10H
7.3.1 Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 50 mS
Exit
Notes for software chip erase:
Data Format: DQ7 − DQ0 (Hex)
Address Format: A14 − A0 (Hex)
- 10 -
DATA
W29EE011
7.4
Command Codes for Product Identification
BYTE SEQUENCE
SOFTWARE PRODUCT
IDENTIFICATION ENTRY
ADDRESS
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
DATA
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
60H
Pause 10 µS
SOFTWARE PRODUCT
IDENTIFICATION EXIT
ADDRESS
DATA
5555H
2AAAH
5555H
-
AAH
55H
F0H
Pause 10 µS
7.4.1 Software Product Identification Acquisition Flow
Product Identification Entry(1)
Product Identification Mode(2, 3)
Product Identification Exit(1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Read address = 0
data = DA
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Load data FO
to
address 5555
Read address = 1
data = C1
m
Pause 10 µS
(4)
Load data 60
to
address 5555
Normal Mode
Pause 10 µ S
Notes for software product identification:
(1) Data format: DQ7 − DQ0 (Hex); address format: A14 − A0 (Hex).
(2) A1 − A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification mode if power down.
(4) The device returns to standard operation mode.
- 11 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER
RATING
UNIT
-0.5 to +7.0
V
0 to +70
°C
-65 to +150
°C
D.C. Voltage on Any Pin to Ground Potential Except #OE
-0.5 to VDD +1.0
V
Transient Voltage (< 20 nS) on Any Pin to Ground Potential
-1.0 to VDD +1.0
V
-0.5 to 12.5
V
Power Supply Voltage to GND Potential
Operating Temperature
Storage Temperature
Voltage on #OE Pin to Ground Potential
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8.2
DC Characteristics
8.2.1 Operating Characteristics
(VDD = 5.0V ±10%, GND = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
Power Supply Current
ICC
Standby VDD Current
(TTL input)
ISB1
TEST CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
#CE = #OE = VIL, #WE = VIH,
all I/Os open
Address inputs = VIL/VIH,
at f = 5 MHz
-
-
50
mA
#CE = VIH, all I/Os open
Other inputs = VIL/VIH
-
2
3
mA
Standby VDD Current
(CMOS input)
ISB2
#CE = VDD -0.3V, all I/Os open
Other inputs = VDD -0.3V/GND
-
20
100
µA
Input Leakage Current
ILI
VIN = GND to VDD
-
-
1
µA
Output Leakage Current
ILO
VIN = GND to VDD
-
-
10
µA
Input Low Voltage
VIL
-
-0.3
-
0.8
V
Input High Voltage
VIH
-
2.0
-
VDD +0.5
V
Output Low Voltage
VOL
IOL = 2.1 mA
-
-
0.45
V
Output High Voltage
VOH
IOH = -0.4 mA
2.4
-
-
V
8.2.2 Power-up Timing
PARAMETER
SYMBOL
TYPICAL
UNIT
Power-up to Read Operation
TPU.READ
100
µS
Power-up to Write Operation
TPU.WRITE
5
mS
- 12 -
W29EE011
8.2.3 Capacitance
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
I/O Pin Capacitance
CI/O
VI/O = 0V
12
pF
Input Capacitance
CIN
VIN = 0V
6
pF
8.3
AC Characteristics
8.3.1 AC Test Conditions
(VDD = 5V ±10%)
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise/Fall Time
< 5 nS
Input/Output Timing Level
1.5V/1.5V
Output Load
1 TTL Gate and CL = 30 pF for 70 nS and 100 pF for others.
8.3.2 AC Test Load and Waveforms
+5V
1.8K ohm
DOUT
100 pF for 90/120/150 nS
30 pF for 70 nS
(Including Jig and Scope)
1.3K ohm
Input
Output
3V
1.5V
1.5V
0V
Test Point
Test Point
- 13 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
8.3.3 Read Cycle Timing Parameters
(VDD = 5.0V ±10 %, VDD = 5.0 ±5 % for 70 nS, GND = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
W29EE011-90
W29EE011-15
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
TRC
90
-
150
-
nS
Chip Enable Access Time
TCE
-
90
-
150
nS
Address Access Time
TAA
-
90
-
150
nS
Output Enable Access Time
TOE
-
45
-
70
nS
#CE Low to Active Output
TCLZ
0
-
0
-
nS
#OE Low to Active Output
TOLZ
0
-
0
-
nS
#CE High to High-Z Output
TCHZ
-
45
-
45
nS
#OE High to High-Z Output
TOHZ
-
45
-
45
nS
Output Hold from Address Change
TOH
0
-
0
-
nS
8.3.4 Byte/Page-write Cycle Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Write Cycle (Erase and Program)
TWC
-
-
10
mS
Address Setup Time
TAS
0
-
-
nS
Address Hold Time
TAH
50
-
-
nS
#WE and #CE Setup Time
TCS
0
-
-
nS
#WE and #CE Hold Time
TCH
0
-
-
nS
#OE High Setup Time
TOES
10
-
-
nS
#OE High Hold Time
TOEH
10
-
-
nS
#CE Pulse Width
TCP
70
-
-
nS
#WE Pulse Width
TWP
70
-
-
nS
#WE High Width
TWPH
150
-
-
nS
Data Setup Time
TDS
50
-
-
nS
Data Hold Time
TDH
10
-
-
nS
Byte Load Cycle Time
TBLC
0.22
-
200
µS
Byte Load Cycle Time-out
TBLCO
300
-
-
µS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
- 14 -
W29EE011
8.3.5 Data Polling and Toggle Bit Timing Parameters
PARAMETER
SYM.
W29EE011-90
W29EE011-15
MIN.
MAX.
MIN.
MAX.
UNIT
#OE to Data Polling Output Delay
TOEP
-
45
-
70
nS
#CE to Data Polling Output Delay
TCEP
-
90
-
150
nS
#OE to Toggle Bit Output Delay
TOET
-
45
-
70
nS
#CE to Toggle Bit Output Delay
TCET
-
90
-
150
nS
- 15 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
9. TIMING WAVEFORMS
9.1 Read Cycle Timing Diagram
TRC
Address A16-0
TCE
#CE
TOE
#OE
#WE
T OHZ
TOLZ
VIH
TCLZ
DQ7-0
TOH
TCHZ
High-Z
High-Z
Data Valid
Data Valid
TAA
9.2
#WE Controlled Write Cycle Timing Diagram
TBLCO
TAS
T WC
TAH
Address A16-0
#CE
TCS
TCH
TOES
T OEH
#OE
#WE
TWP
TWPH
TDS
DQ7-0
Data Valid
TDH
Internal write starts
- 16 -
W29EE011
9.3
#CE Controlled Write Cycle Timing Diagram
TAS
TBLCO
T AH
T WC
Address A16-0
T CPH
T CP
#CE
T OES
T OEH
#OE
#WE
T DS
DQ7-0
High Z
Data Valid
T DH
Internal Write Starts
9.4
Page Write Cycle Timing Diagram
TWC
Address A16-0
DQ7-0
#CE
#OE
TWP
T WPH
TBLCO
TBLC
#WE
Byte 0
Byte 1
Byte 2
Byte N-1
Byte N
Internal Write Start
- 17 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
9.5
#DATA Polling Timing Diagram
Address A16-0
#WE
TCEP
#CE
TOES
TOEH
#OE
TOEP
DQ7-0
X
X
X
X
TWC
9.6
Toggle Bit Timing Diagram
Address A16-0
#WE
#CE
TOES
TOEH
#OE
DQ6
TWC
- 18 -
W29EE011
9.7
Page Write Timing Diagram Software Data Protection Mode
Address A16-0
DQ6
5555
2AAA
5555
AA
TWC
Byte/page load
cycle starts
Three-byte sequence for
software data protection mode
A0
55
#CE
#OE
TBLC
TWP
#WE
TBLCO
TWPH
Byte N-1
Byte 0
SW2
SW1
SW0
Byte N
(last byte)
Internal write starts
9.8
Reset Software Data Protection Timing Diagram
Six-byte sequence for resetting
software data protection mode
Address A16-0
DQ7-0
5555
2AAA
5555
55
80
AA
5555
AA
TWC
2AAA
55
5555
20
#CE
#OE
TWP
#WE
TBLC
TBLCO
TWPH
SW0
SW1
SW2
SW3
SW4
SW5
Internal programming starts
- 19 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
9.9
5 Volt-only Software Chip Erase Timing Diagram
Six-byte code for 5V-only software
chip erase
Address A16-0
DQ7-0
5555
2AAA
5555
55
80
AA
5555
AA
2AAA
55
TWC
5555
10
#CE
#OE
TWP
#WE
TBLC
TBLCO
TWPH
SW0
SW1
SW2
SW3
SW4
SW5
Internal programming starts
- 20 -
W29EE011
10. ORDERING INFORMATION
PART NO.
ACCESS
TIME
(NS)
W29EE011-90
W29EE011-15
90
150
W29EE011T-90
90
W29EE011T-15
150
W29EE011Q-90
90
W29EE011Q-15
150
W29EE011P-90
W29EE011P-15
W29EE011-90B
W29EE011-15B
W29EE011T90B
W29EE011T15B
W29EE011Q90B
W29EE011Q15B
W29EE011P90B
W29EE011P15B
W29EE011-90N
W29EE011-15N
W29EE011P90N
W29EE011P15N
90
150
90
150
90
150
90
150
90
150
90
150
90
150
W29EE011P90Z
90
W29EE011P15Z
150
W29EE011Q90Z
90
POWER
STANDBY VDD
SUPPLY
CURRENT
PACKAGE
CURRENT
MAX. (µA)
MAX. (MA)
50
100
600 mil DIP
50
100
600 mil DIP
TSOP
50
100
(8 x 20 mm)
TSOP
50
100
(8 x 20 mm)
STSOP
50
100
(8 x 14 mm)
STSOP
50
100
(8 x 14 mm)
50
100
32-pin PLCC
50
100
32-pin PLCC
50
100
600 mil DIP
50
100
600 mil DIP
50
100
TSOP (8x20mm)
50
100
TSOP (8x20mm)
50
100
STSOP (8x14mm)
50
100
STSOP (8x14mm)
50
100
32-pin PLCC
50
100
32-pin PLCC
50
100
600 mil DIP
50
100
600 mil DIP
50
100
32-pin PLCC
50
100
32-pin PLCC
Lead-free 32-pin
50
100
PLCC
Lead-free 32-pin
50
100
PLCC
50
100
STSOP (8x14mm)
CYCLING
HARDWARE
SID READ
FUNCTION
1K
1K
Y
Y
1K
Y
1K
Y
1K
Y
1K
Y
1K
1K
10K
10K
10K
10K
10K
10K
10K
10K
1K
1K
1K
1K
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
1K
Y
1K
Y
10K
Y
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
3. In Hardware SID Read column: Y = with SID read function; N = without SID read function.
- 21 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
11. HOW TO READ THE TOP MARKING
Example: The top marking of 32L-PLCC W29EE011P15N
W29EE011P15N
2138977A-A12
149OBRA
1st line: winbond logo
2nd line: the part number: W29EE011P15N
3rd line: the lot number
4th line: the tracking code: 149 O B RA
149: Packages made in ’01, week 49
O: Assembly house ID: A means ASE, O means OSE, ...etc.
B: IC revision; A means version A, B means version B, ...etc.
RA: Process code
- 22 -
W29EE011
12. PACKAGE DIMENSIONS
12.1 32-pin P-DIP
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
17
32
E1
E
A1
L
Base Plane
Seating Plane
B
e1
a
B1
0.25
0.155
0.160
3.81
3.94
4.06
0.016
0.018
0.022
0.41
0.46
0.56
0.048
0.050
0.054
1.22
1.27
1.37
0.008
0.010
0.014
0.20
0.25
0.36
0.150
1.650
1.660
41.91
42.16
0.600
0.610
14.99
15.24
15.49
0.590
0.545
0.550
0.555
13.84
13.97
14.10
0.090
0.100
0.110
2.29
2.54
2.79
0.120
0.130
0.140
3.05
3.30
3.56
15
0
0.670
16.00
16.51
17.02
0
0.630 0.650
15
0.085
2.16
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
2.Dimension E1 does not include interlead flash.
3.Dimensions D & E1. include mold mismatch and
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
5.Controlling dimension: Inches
6.General appearance spec. should be based on
final visual inspection spec.
c
A A2
5.33
0.210
eA
S
Notes:
16
S
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.010
a
1
Dimension in inches
eA
12.2 32-pin PLCC
Symbol
HE
E
4
1
32
30
5
29
GD
D HD
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
θ
Dimension in Inches
Min.
Nom.
Max.
Dimension in mm
Min.
Nom.
0.140
0.020
Max.
3.56
0.50
0.105
0.110
0.115
2.67
2.80
2.93
0.026
0.028
0.032
0.66
0.71
0.81
0.016
0.018
0.022
0.41
0.46
0.008
0.010
0.014
0.20
0.25
0.35
0.547
0.550
0.553
13.89
13.97
14.05
0.447
0.450
0.453
11.35
11.43
11.51
0.044
0.050
0.056
1.12
1.27
1.42
0.490
0.51
0.530
12.45
13.46
0.56
9.91
12.9
5
10.41
0.585
0.590
0.595
14.86
14.99
15.11
0.485
0.49
0
0.090
0.495
12.32
12.45
12.57
0.095
1.91
2.29
2.41
0.390
0.075
0.410
0.430
0.004
0
10
10.92
0.10
0
10
21
13
Notes:
14
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.
c
20
L
A2
θ
e
b
b1
Seating Plane
GE
A
A1
y
- 23 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
Package Dimensions, continued
12.3 32-pin TSOP (8 x 20 mm)
HD
Dimension in Inches
Dimension in mm
Symbol
D
Nom.
__
__
A
c
M
Min.
e
E
0.10(0.004)
b
A1
0.002
A2
0.037
b
__
__
Max.
1.20
0.039
0.041
0.95
1.00
1.05
0.007
0.008
0.009
0.17
0.20
0.23
c
0.005
0.006
0.007
0.12
0.15
0.17
D
0.720
0.724
0.728
18.30
18.40
18.50
E
0.311
0.315
0.319
7.90
8.00
8.10
HD
0.780
0.787
0.795
19.80
20.00
20.20
__
__
0.024
0.40
__
__
__
L
L
__
Nom.
__
0.05
0.020
0.016
0.020
__
L
θ
0.047
Min.
0.006
e
A
Max.
0.031
1
A2
Y
0.000
A1
θ
1
__
0.004
0.00
5
1
3
0.15
__
0.50
0.50
0.60
__
0.80
__
0.10
5
3
Y
L1
Note:
Controlling dimension: Millimeters
12.4 32-pin STSOP (8 x 14 mm)
HD
Dimension in Inches Dimension in mm
D
Symbol
Min. Nom. Max.
c
A
A1
A2
b
c
D
E
HD
e
L
L1
Y
θ
e
E
b
θ
L
L1
A1
A2
A
- 24 -
Y
Min. Nom. Max.
0.047
0.002
1.20
0.006
0.05
0.15
0.035
0.040
0.041
0.95
1.00
1.05
0.007
0.009
0.010
0.17
0.22
0.27
0.004
-----
0.008
0.10
-----
0.21
0.488
12.40
0.315
8.00
0.551
14.00
0.020
0.020
0.024
0.50
0.028
0.50
0.031
0.000
0
3
0.60
0.70
0.80
0.004
0.00
5
0
0.10
3
5
W29EE011
13. VERSION HISTORY
VERSION
DATE
PAGE
A9
Feb. 1998
6
Add pause 10 mS
7
Add pause 50 mS
8
Correct the time 10 mS to 10 µS
1, 17
A10
Jun. 1998
1, 10, 11, 12, 17
A11
Aug. 1998
1, 2, 17, 19
A12
Jul. 1999
1, 17
1, 11, 12, 17
1, 17, 18
A13
Dec. 2000
4, 17
A14
Mar. 2001
1, 17, 18
A15
Feb. 19, 2002
DESCRIPTION
Add cycing 100 item
Add 70 nS bining
Add TSOP package
Change endurance cycles as 1K/10K
Delete 70, 120 nS bining
Delete SOP package
Add in Hardware SID Read Function note
Add in TSOP (8 x 14 mm) package
17
Correct Part No. in Ordering Information
4
Modify VDD Power Up/Down Detection in Hardware
Data Protection
18
Add HOW TO READ THE TOP MARKING
1, 17, 20
Rename TSOP (8 x 14 mm) as STSOP (8 X 14 mm)
A16
Feb. 17, 2004
1, 17
Add in Lead-free 32-pin PLCC package
A17
April 15 ,2005
23
Add important notice
A18
April 11, 2006
21
Add W29EE011Q90Z package
- 25 -
Publication Release Date: April 11, 2006
Revision A18
W29EE011
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 26 -
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