W78CE354P

Preliminary W78C354 MONITOR MICROCONTROLLER GENERAL DESCRIPTION The W78C354 is a high-performance monitor microcontroller that is based on the embedded 80C32 microcontroller core. The W78C354 includes a 16 KB ROM, 512 byte internal data RAM, a 6-bit A/D converter, two 12-bit and fourteen 8-bit PWM static DACs, one 12-bit and three 8-bit PWM dynamic DACs, a sync processor, an I2C port, a DDC port, a watchdog timer, and glue logic specially designed for monitor applications. The W78C354 is suitable for monitors applying VESA DDC1/DDC2B/DDC2B+. This product's high level of integration and the availability of a one-time programmable (OTP) flash PROM version(the W78E354) help to reduce unit costs, development costs, and development time. FEATURES • • • • • • • • • • • • • • • • • • • 80C32 MCU core included 20 MHz maximum operating frequency 16 KB ROM for program storage 512 bytes of on-chip data RAM: − Lower 256 bytes accessed as in the 80C32 − Higher 256 bytes accessed as an external data memory via "MOVX @Ri". One SPI/RS232 port (80C32 standard serial port) One external interrupt input Two timers/counters One 8-bit auto-reload timer for software time base PWM DACs: − Two 12-bit PWM/BRM static DACs − Fourteen 8-bit PWM static DACs − One 12-bit PWM/BRM dynamic DAC − Three 8-bit PWM dynamic DACs One 6-bit ADC with 4 multiplexed analog inputs Sync processor: − Horizontal & vertical polarity detector − Sync separator for composite sync − Horizontal & vertical frequency counter − Programmable dummy frequency generator − Programmable H-clamp pulse output − Safe operation area (SOA) output − Self-test pattern output One software I2C port One DDC port (master/slave mode I2C, supports DDC1/DDC2B/DDC2B+) Watchdog timer Moire cancellation Two 15 mA output pins for driving LED Power-low reset OTP type: W78E354 (16 KB flash PROM) Three package types: − PLCC68 (W78C/E354P), DIP48 (W78C/E354E), DIP40 (W78C/E354) -1- Publication Release Date: October 1996 Revision A1 W78C354 PIN CONFIGURATIONS W78C/E354P (PLCC68) S D A C 9 S D A C 8 S D A C 7 5 S D A C 6 4 S D A C 5 3 S D A C 4 S D A C 3 S D A C 2 S D A C 1 P 2 . 5 9 SDAC10 SDAC11 P2.6 P2.7 OSCOUT OSCIN VSS P2.0 P2.1 SDAC12 SDAC13 P2.2 P2.3, STP P3.4, T0 P3.5, T1 HIN VIN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P 2 . 4 8 P 4 . 6 2 P 4V .D 5D P 3 . 7 P 4 . 4 P 3 . 3 76 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 SDAC0 BDDAC DDAC2 DDAC1 DDAC0 P4.3 VPP(Only for W78E354P) P4.2 VDD P1.5, SOA P1.4, HCLAMP P1.3, DSDA P1.2, DSCL P1.1, ISDA P1.0, ISCL P4.1 P4.0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 H O U T V O U T B S D A C 0 B S D A C 1 P 3 . 0 , R X D P 3 . 1 , T X D / VVAAVA RSSDDAD SSSCCAC T 2 A01 , P 1 . 6 A NP D C3 . C 2 3 , , I P N 1 T . 0 7 P 3 . 6 W78C/E354E (DIP48) SDAC5 SDAC6 SDAC7 P2.4, SDAC10 P2.5, SDAC11 P2.6, SDAC12 P2.7, SDAC13 OSCOUT OSCIN VSS P2.0 P2.1 P2.2 P2.3, STP P3.4, T0 P3.5, T1 HIN VIN HOUT VOUT BSDAC0 P3.0, RXD P3.1, TXD RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD SDAC4 SDAC3 SDAC2 SDAC1 P3.3 SDAC0 BDDAC DDAC2 DDAC1 DDAC0 VPP (Only for W78E354E) P1.5, SOA P1.4, HCLAMP P1.3, DSDA P1.2, DSCL P1.1, ISDA P1.0, ISCL P3.6 P3.2, INT0 NC VAA ADC0 VSSA W78C/E354 (DIP40) SDAC5 SDAC6 SDAC7 P2.4, SDAC10 P2.5, SDAC11 P2.6, SDAC12 P2.7, SDAC13 OSCOUT OSCIN VSS P2.0 P2.1 P2.2 P2.3, STP HIN VIN HOUT VOUT BSDAC0 P3.0, RXD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD SDAC4 SDAC3 SDAC2 SDAD1 SDAD0 BDDAC DDAC0 VPP (Only for W78E354) P1.5, SOA P1.4, HCLAMP P1.3, DSDA P1.2, DSCL P1.1, ISDA P1.0, ISCL P3.2, INT0 NC ADC0 RST P3.1, TXD -2- W78C354 PIN ARRANGEMENT REFERENCE TABLE DIP-40 22 15 16 17 18 35 36 37 38 39 1 2 3 19 40 10 34 33 26 27 28 29 30 31 23 DIP-48 24 17 18 19 20 42 44 45 46 47 1 2 3 21 48 10 41 38 39 40 31 32 33 34 35 36 26 PLCC-68 PIN NAME 33 RST 25 HIN 26 VIN 27 HOUT 28 VOUT 60 SDAC0 62 SDAC1 63 SDAC2 65 SDAC3 66 SDAC4 3 SDAC5 4 SDAC6 5 SDAC7 6 SDAC8 7 SDAC9 10 SDAC10 11 SDAC11 19 SDAC12 20 SDAC13 29 BSDAC0 30 BSDAC1 68 VDD 16 VSS 59 BDDAC 56 DDAC0 57 DDAC1 58 DDAC2 46 P1.0 (ISCL) 47 P1.1 (ISDA) 48 P1.2 (DSCL) 49 P1.3 (DSDA) 50 P1.4 (HCLAMP) 51 P1.5 (SOA) 36 ADC0 DIP-40 11 12 13 14 4 5 6 7 20 21 25 24 32 8 9 DIP-48 27 25 11 12 13 14 4 5 6 7 22 23 29 43 15 16 30 28 37 8 9 PLCC-68 PIN NAME 37 ADC1 39 40 38 35 17 18 21 22 8 9 12 13 31 32 42 61 23 24 43 67 44 45 53 55 64 1 2 41 54 52 34 14 15 ADC2(P1.6) ADC3(P1.7) VAA VSSA P2.0 P2.1 P2.2 P2.3 (STP) P2.4 (SDAC10) P2.5 (SDAC11) P2.6 (SDAC12) P2.7 (SDAC13) P3.0 (RXD ) P3.1 (TXD ) P3.2 (INT0) P3.3 P3.4 (T0) P3.5 (T1) P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 NC VPP VDD VSS OSCOUT OSCIN -3- Publication Release Date: October 1996 Revision A1 W78C354 PIN DESCRIPTION PIN NAME SDAC0−7 SDAC8−13 BSDAC0−1 DDAC0−2 BDDAC ADC0 ADC1 ADC2 (P1.6) ADC3 (P1.7) P1.0−P1.1 P1.2 (DSCL) P1.3 (DSDA) I/O I/O I/O TYPE O O O O O I FUNCTION 8-bit PWM static DAC output. Sink/source current 4 mA/-4 mA. 8-bit PWM static DAC output. Sink/source current 4 mA/-4 mA. 12-bit PWM/BRM static DAC output. Sink/source current 8 mA/-8 mA. 8-bit PWM dynamic DAC output. Sink/source current 8 mA/-8 mA. 12-bit PWM/BRM dynamic DAC output. Sink/source current 8 mA/-8 mA. Analog signal input channel to AD converter. Alternate function: ADC2: P1.6 input (input only). ADC3: P1.7 input (input only). General purpose I/O. Open-drain, Sink current 2 mA. General purpose I/O. Open-drain, Sink current 6 mA. Alternate function: P1.2: DDC port serial clock DSCL. P1.3: DDC port serial data DSDA. P1.4 (HCLAMP) I/O General purpose I/O. Sink/source current 4 mA/-100 µA. Alternate function: P1.4: HCLAMP (H-clamp pulse) output. While outputing special function, P1.4 sink/source current is 4 mA/-4 mA. P1.5 (SOA) I/O General purpose O/P. Sink/source current 4 mA/-4 mA. Alternate function: P1.5: SOA (safe operation area) output. P2.0−P2.1 I/O General purpose I/O. Sink/source current 15 mA/-100 µA. -4- W78C354 Pin Description, continued PIN NAME P2.2 P2.3 (STP) P2.4 (SDAC10) P2.5 (SDAC11) P2.6 (SDAC12) P2.7 (SDAC13) P3.0 (RXD) P3.1 (TXD) P3.2 (INT0) P3.3 P3.4 (T0) P3.5 (T1) P3.6 P3.7 P4.0−P4.6 HIN VIN HOUT VOUT I/O TYPE I/O General purpose I/O. FUNCTION Sink/source current 4 mA/-100 µA. Alternate function: P2.3: STP (Self-Test Pattern) output. P2.4−P2.7: SDAC10−13 outputs. While outputing special function, P2.3−P2.7 sink/source current is 4 mA/-4 mA. I/O General purpose I/O. Sink/Source current 2 mA/-100 µA. Alternate function: P3.0: Serial input port. P3.1: Serial output port. P3.2: External interrupt input. P3.4, P3.5: Timer/counter 0, 1 external inputs. O I Output port. Sink/source current 2 mA/-2 mA. HIN: Hsync/composite sync input. VIN: Vsync input. Schmitt trigger input pin. O HOUT: Hsync output. VOUT: Vsync output. Sink/source current 4 mA/-4 mA. RST OSCOUT OSCIN VPP VDD VSS VAA VSSA I O I I I I I I Reset the controller (active low). Schmitt trigger input pin. Output from inverting oscillator amplifier. Input to inverting oscillator amplifier. High voltage supply input for flash PROM. Positive power supply for digital circuit, +5V. Digital ground. Positive power supply for analog circuit, +5V. Analog ground. BLOCK DIAGRAM -5- Publication Release Date: October 1996 Revision A1 W78C354 VDD VSS Power source Supervisor 512 x 8 RAM 16K x 8 Mask ROM RST Reset Circuit CPU CORE Interrupt Processor INT0 HOUT, VOUT HIN, VIN HCLAMP SOA WDT SDAC Sync. Processor SDAC0 to 13, BSDAC0 to 1 DDAC0 to 2, BDDAC DDAC ADC0 to 3 ADC VAA , VSSA ISCL IC 2 Oscillator ISDA DSCL DSDA P2 TXD RXD Serial Port DDC Port I/O Port P4 T0 T1 Timer0 Timer1 Auto Reload Timer -6- W78C354 FUNCTIONAL DESCRIPTION The W78C354's core architecture consists of an 80C32 MCU surrounded by various special function registers, or SFRs (some of these are 80C32 standard registers, while others are newly added; see Table 1), three general purpose I/O ports (P1, P2, and P3), one output-only port (P4), 256 bytes of scratchpad RAM, two timer/counters (Timer0 and Timer1) and one 80C32 standard serial port. The processor supports 109 different instructions (without "MOVX A, @DPTR" and "MOVX @DPTR, A"), which are all compatible with the 80C32 family instruction set. There are two major differences between the W78C354 and 80C32. First, the W78C354 cannot access an external program or data memory. This function is unnecessary, because the W78C354's 16 KB of internal ROM and 512 bytes of on-chip RAM should be enough for most monitor applications. Second, the W78C354 has a number of new SFRs (see Table 2), which provide more powerful functions. Table 1. W78C354 special function registers (SFRs) F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 + IP + P3 + IE + P2 + SCON + P1 + TCON + CONTREG1 SBRM0 ADC SDAC7 SDAC0 SBUF AUTOLOAD TMOD SP SBRM1 INTVECT SDAC8 SDAC1 BSDAC0 DHREG TL0 DPL PORT4 STATUS SDAC9 SDAC2 BSDAC1 DVREG TL1 DPH SOAREG HFCOUNTL SDAC10 SDAC3 WDTCLR DDC1 TH0 CONTREG5 SOACLR HFCOUNTH SDAC11 SDAC4 DDAC0 INTMSK TH1 CONTREG2 VFCOUNTL SDAC12 SDAC5 DDAC1 BDDAC PARAL VFCOUNTH SDAC13 SDAC6 DDAC2 DBRM PARAH PCON + ACC + S1CON + PSW + CONTREG4 S1STA S1DAT S1ADR +B FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 Notes: 1. SFRs with a "+" are both byte and bit-addressable. 2. The registers in the shaded region are newly added to the 80C32. A. Memory Address Space The W78C354 operates in three separate address spaces: (1) The first (Figure 1-1) is the 16 KB internal program space (0000H−3FFFH). (2) The second (Figure 1-2) is the data memory space, which is 256 bytes in size (0000H−00FFH). The data memory is integrated inside the chip rather than outside the chip, as in a standard 80C32. This data memory space must be accessed by the "MOVX @Ri" instruction. (3) The third (Figure 1-3) is the same as in the standard 80C32. -7- Publication Release Date: October 1996 Revision A1 W78C354 On-Chip Program Memory 3FFFH On-Chip Data Memory FFH FFH SFR (MOVX @Ri) Scratchpad RAM (Indirect Addressing) 80H 7FH Scratchpad RAM 00H (Direct Addressing) 0000H Figure 1-1 00H Figure 1-2 (Direct/Indirect Addressing) Figure 1-3 Figure 1. Memory address space B. Modified 80C32 SFRs 1. Timer/Counter Control Register (TCON): BIT TCON.7 NAME TF1 Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TCON.6 TCON.5 TR1 TF0 Timer 1 run control bit. Set/cleared by software to turn timer/counter on or off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TCON.4 TCON.3 TCON.2 TCON.1 TR0 IE0 Timer 0 run control bit. Set/cleared by software to turn timer/counter on or off. Reserved Reserved Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. TCON.0 IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. Note: The registers in the shaded region are modified from the 80C32 SFRs. FUNCTION -8- W78C354 2. Power Control Register (PCON): NAME SMOD GF1 GF0 IDL Notes: 1. The SFR is not bit-addressable. 2. The registers in the shaded region are modified from the 80C32 SFRs. FUNCTION Double baud rate bit. Reserved Reserved Reserved General-purpose flag bit. General-purpose flag bit. Reserved Idle mode bit. 3. Interrupt Enable Register (IE): BIT IE.7 NAME EA FUNCTION If EA = 0, no interrupt will be acknowledged (disable all interrupts). If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 Notes: *1. No name for ASSEMBLER, must be used via "IE.x".”. *2. DSCLINT+ADCINT+TIMEOUT+SOAINT+VEVENT+PARAINT +DDC1INT. *1 ES ET1 *1 ET0 EX0 (Reserved) Set/clear to enable/disable the DDC port's I2C interrupt. Set/clear to enable/disable the serial port 0 interrupt. Set/clear to enable/disable the Timer 1 overflow interrupt. Set/clear to enable/disable the *2 interrupt. Set/clear to enable/disable the Timer 0 overflow interrupt. Set/clear to enable/disable the external interrupt 0. -9- Publication Release Date: October 1996 Revision A1 W78C354 4. Interrupt Priority Register (IP) BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 NAME *1 PS PT1 *1 PT0 PX0 (Reserved) (Reserved) Define the DDC port's I2C interrupt priority level. If IP.5 = 1, the priority level is higher. Define the serial port interrupt priority level. If PS = 1, the priority level is higher. Define the Timer 1 interrupt priority level. If PT1 = 1, the priority level is higher. Define the *2 priority level. If IP.2 = 1, the priority level is higher. Define the Timer 0 interrupt priority level. If PT0 = 1, the priority level is higher. Define the external interrupt 0 priority level. If PX0 = 1, the priority level is higher. Notes: *1. No name for ASSEMBLER, must be used via "IP.x". *2. DSCLINT+ADCINT+TIMEOUT+SOAINT+VEVENT+PARAINT+DDC1INT. FUNCTION C. Newly Added Special Function Registers In addition to the 80C32 SFRs, the W78C354 has forty-nine new SFRs in the SFR address space, as listed in Table 2. Table 2. New special function registers REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 CONTREG1 CONTREG5 CONTREG2 PARAL PARAH AUTOLOAD DHREG DVREG DDC1 INTMSK BDDAC DBRM ADDRESS 80H 84H 85H 8EH 8FH 91H 92H 93H 94H 95H 96H 97H FUNCTION Control register 1, bit-addressable Control register 5 Control register 2 Parabola interrupt generator low byte register Parabola interrupt generator high byte register 8-bit auto-reload timer register Dummy Hsync frequency generator register Dummy Vsync frequency generator register DDC port's DDC1 data buffer Interrupt mask register 8-bit PWM register for 12-bit PWM/BRM dynamic DAC 4-bit BRM register for 12-bit PWM/BRM dynamic DAC LENGTH 8 8 8 8 8 8 4 8 8 8 8 4 R/W TYPE R/W R/W W W W W W W W W W W RESET CONTENT 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H - 10 - W78C354 Table 2. New special function registers, continued REGISTER 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Notes: 1. "-" means the SFR has no real hardware but only an address. 2. Three SFRs (CONTREG1, CONTREG4, SICON) can be accessed by bit addressing. BSDAC0 BSDAC1 WDTCLR DDAC0 DDAC1 DDAC2 SDAC0 SDAC1 SDAC2 SDAC3 SDAC4 SDAC5 SDAC6 SDAC7 SDAC8 SDAC9 SDAC10 SDAC11 SDAC12 SDAC13 ADC INTVECT STATUS HFCOUNTL HFCOUNTH VFCOUNTL VFCOUNTH SBRM0 SBRM1 PORT4 SOAREG SOACLR CONTREG4 S1CON S1STA S1DAT S1ADR ADDRESS 9AH 9BH 9CH 9DH 9EH 9FH A1H A2H A3H A4H A5H A6H A7H A9H AAH ABH ACH ADH AEH AFH B1H B2H B3H B4H B5H B6H B7H B9H BAH BBH BCH BDH C8H D8H D9H DAH DBH FUNCTION 8-bit PWM register for 12-bit PWM/BRM Static DAC0 8-bit PWM register for 12-bit PWM/BRM Static DAC1 Watch-dog timer clear register 8-bit PWM dynamic DAC0 register 8-bit PWM dynamic DAC1 register 8-bit PWM dynamic DAC2 register 8-bit PWM static DAC0 register 8-bit PWM static DAC1 register 8-bit PWM static DAC2 register 8-bit PWM static DAC3 register 8-bit PWM static DAC4 register 8-bit PWM static DAC5 register 8-bit PWM static DAC6 register 8-bit PWM static DAC7 register 8-bit PWM static DAC8 register 8-bit PWM static DAC9 register 8-bit PWM static DAC10 register 8-bit PWM static DAC11 register 8-bit PWM static DAC12 register 8-bit PWM static DAC13 register 6-bit ADC result register Interrupt vector register Status register Horizontal frequency counter low byte register Horizontal frequency counter high byte register Vertical frequency counter low byte register Vertical frequency counter high byte register 4-bit BRM register for 12-bit PWM/BRM Static DAC0 4-bit BRM register for 12-bit PWM/BRM Static DAC1 Output latch register Safe operation area register Safe operation area clear register Control register 4 SIO1 port control register SIO1 port status register SIO1 port data register SIO1 port address register LENGTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 8 8 8 8 4 4 7 8 8 8 8 8 8 R/W TYPE W W W W W W W W W W W W W W W W W W W W R R/W R R R R R W W W W W R/W R/W R R/W R/W RESET CONTENT 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H F8H 00H 00H D. Status and Control Register Overview 1. STATUS: Status Register - 11 - Publication Release Date: October 1996 Revision A1 W78C354 BIT 0 1 2 3 NAME HP VP NOH NOV FUNCTION Hsync polarity. 0: Positive, 1: Negative. Vsync polarity. 0: Positive, 1: Negative. Set by hardware if no Hsync. Set by hardware if no Vsync. 2. CONTREG1: Control Register1, Bit-addressable BIT 0 1 2 NAME ADCS0 ADCS1 ENDDC1 FUNCTION ADC channel select bit 0. ADC channel select bit 1. Enable/Disable DDC1 mode. 0: Disable DDC1 mode; the pin P1.3/DSDA is accessed data in the DDC2B/2B+ mode. 1: Enable DDC1 mode ; the pin P1.3/DSDA is output data in the DDC1 mode. 3 HCES 4 5 6 7 HCWS0 HCWS1 DUMMYEN ADCSTRT H-Clamp Edge Select. 0: Pin P1.4 will output H-clamp pluse, if the leading edge of Hsync occurs. 1: Pin P1.4 will output H-clamp pluse, if the trailing edge of Hsync occurs. H-Clamp Width Select bit 0. H-Clamp Width Select bit 1. Enable/Disable dummy frequency generator. 0: Disable, 1: Enable. Start ADC conversion. 0: Stop, 1: Start. 3. CONTREG2: Control Register2 BIT 0 1 2 3 NAME ENVS HSPS VSPS FUNCTION Enable/Disable Vsync Separator. 0: Disable, 1: Enable. Hout Sync Polarity Select. 0: Positive, 1: Negative. Vout Sync Polarity Select. 0: Positive, 1: Negative. Reserved. - 12 - W78C354 3. CONTREG2: Control Register2, continued BIT 4 NAME EINTES 5 6 7 ENM0 ENM1 VDISHC FUNCTION External INT Edge Select. 0: High-level/rising-edge triggered. 1: Low-level/falling-edge triggered. Enable/Disable SDAC0 morie cancel function. 0: Disable, 1: Enable. Enable/Disable SDAC1 morie cancel function. 0: Disable, 1: Enable. Disable H-Clamp pulse at the Vsync pulse period. In initial state, it enables the H-Clamp output. 0: Enable, 1: Disable. 4. CONTREG4: Control Register4, Bit-addressable BIT 0 NAME P24SF FUNCTION Enable/Disable Port 2.4 Special Function. P24SF = 0: General I/0 pin. P24SF = 1 and P2.4 = 0: SDAC10 output. Enable/Disable Port 2.5 Special Function. P25SF = 0: General I/0 pin. P25SF = 1 and P2.5 = 0: SDAC11 output. Enable/Disable Port 2.6 Special Function. P26SF = 0: General I/0 pin. P26SF = 1 and P2.6 = 0: SDAC12 output. Enable/Disable Port 2.7 Special Function. P27SF = 0: General I/0 pin. P27SF = 1 and P2.7 = 0: SDAC13 output. Enable/Disable Port 1.4 Special Function. P14SF = 0: General I/0 pin. P14SF = 1 and P1.4 = 0: H-Clamp output. Enable/Disable Port 1.5 Special Function. P15SF = 0: General I/0 pin. P15SF = 1 and P1.5 = 0: SOA output. Enable/Disable Port 2.3 Special Function. P23SF = 0: General I/0 pin. P23SF = 1 and P2.3 = 0: STP output. Invert Self-Test Pattern. 1 P25SF 2 P26SF 3 P27SF 4 P14SF 5 P15SF 6 P23SF 7 INVSTP Note: To let the Px.y output special function, set PxySF and clear Px.y. - 13 - Publication Release Date: October 1996 Revision A1 W78C354 5. CONTREG5: Control Register5 BIT 0 1 2 3 4 5 6 NAME HDSEL DPARAINT Reserved. Reserved. Reserved. Reserved. Reserved. HCLAMP Source SELect. Enable parabola interrupt with dummy signal. DPARAINT = 0; V dummy signal will generate VEVENT interrupt. DPARAINT = 1; V dummy signal will not generate VEVENT interrupt. 7 Reserved. FUNCTION E. I/O Port The I/O ports available in the W78C354 vary with the package, as shown in the table below: I/O PORT Port 1 Port 2 Port 3 Port 4 68-PIN PLCC 6 bits 8 bits 8 bits 7 bits 48-PIN DIP 6 bits 8 bits 7 bits N.A. 40-PIN DIP 6 bits 8 bits 3 bits N.A. P1, P2, and P3 are the SFR latches of ports 1, 2, and 3, respectively. Writing a "1" to a bit of a port SFR (P1, P2, or P3) causes the corresponding port output pin to switch to high. Writing a "0" causes the port output pin to switch to low. When a port is used as an input, the external state of the port pin will be read into the port SFR (i.e., if the external state is low, the corresponding SFR bit will contain a "0"; if it is high, the bit will contain a "1"). The block diagrams and control registers are shown below. E-1 Port 1 Besides general purpose I/O functions, port 1 provides the functions shown in the following table. PINS P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 SPECIAL FUNCTION ISCL ISDA DSCL DSDA HCLAMP SOA SPECIAL FUNCTION CONTROL BIT P14SF P15SF DESCRIPTION s/w I2C SCL pin s/w I2C SDA pin DDC port's SCL pin DDC port's SDA pin H-clamp pulse output SOA output - 14 - W78C354 Read Latch P1.0/P1.1 Int.Bus Write to Latch D CL Q Q Read Pin Figure 2-1. P1.0/P1.1 architecture SCL output/ SDA output Read Latch Int.Bus Write to Latch P1.2/P1.3 D CL Q Q Read Pin SCL input / SDA input Figure 2-2. P1.2/P1.3 architecture P14SF/P15SF Read Latch Vcc Internal Pullup 0 1 P1.4/P1.5 Int.Bus Write to Latch Read Pin Hclamp/SOA D CL Q Q Figure 2-3. P1.4/P1.5 architecture - 15 - Publication Release Date: October 1996 Revision A1 W78C354 To use the alternate function H-clamp pulse (SOA output) of P1.4 (P1.5), bit P14SF (P15SF) of the SFR CONTREG4 must be set to "1" and a "0" must be written to P1.4 (P1.5). CONDITION OF P14SF P14SF = 0 P14SF = 1 & P1.4 = 0 E-2 Port 2 Port 2.0−2.2 are used for general purpose I/O functions only, whereas 2.3−2.7 have alternate functions, as shown below. In the 40-pin and 48-pin DIP packages, SDAC10−13 have no dedicated output pins, but share pins with P2.4−P2.7. Each pin can be used as an I/O or SDAC output pin by bitaddressing SFR CONTREG4. When a pin is used for a special function, the output source current is 4 mA. Otherwise, the source current is 100 µA. PINS P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SPECIAL FUNCTION STP SDAC10 SDAC11 SDAC12 SDAC13 SPECIAL FUNCTION CONTROL BIT P23SF P24SF P25SF P26SF P27SF DESCRIPTION Self -test pattern output SDAC10 PWM output SDAC11 PWM output SDAC12 PWM output SDAC13 PWM output PORT 1.4 I/O PIN FUNCTION General I/O pin Hclamp pulse output CONDITION OF P14SF P15SF = 0 P15SF = 1 & P1.5 = 0 PORT 1.5 I/O PIN FUNCTION General output pin SOA output Vcc Read Latch Internal Pullup P2.0 to P2.2 Int.Bus Write to Latch D CL Q Q Read Pin Figure 3-1. P2.0 to P2.2 architecture - 16 - W78C354 P2nSF Read Latch Vcc Internal Pullup Int.Bus Write to Latch Read Pin SDACn+6 D CL Q Q 0 1 P2.n/SDACn+6 Figure 3-2. P2.4 to P2.7 architecture (where n = 4−7) E-3 Port 3 The architecture of Port 3 is similar to that of P2.0. There are no special function control bits for these bits; the output latch of the bits must be set to high to enable the special functions. PINS P3.0 SPECIAL FUNCTION SPID/RXD DESCRIPTION If serial port is in mode 0, the pin works as the data line of the SPI port. If serial port is in mode 1, 2, or 3, the pin works as the RXD of the 80C32 standard. If serial port is in mode 0, the pin works as the clock line of the SPI port. If serial port is in mode 1, 2, or 3, the pin works as the TXD of the 80C32 standard. External Interrupt input Counter/Timer 0 input Counter/Timer 1 input P3.1 SPIC/TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 INT0 T0 T1 - - 17 - Publication Release Date: October 1996 Revision A1 W78C354 E-4 Port 4 Port 4 is an output port. The W78C354 can write data to this port using SFR PORT4. Vcc Internal Pullup P4.0 to P4.6 Int.Bus Write to Latch D CL Q Q Figure 4-1. Port 4 architecture F. SPI (Synchronous Peripheral Interface) and RS232 Port • P3.0 (RXD) and P3.1 (TXD) can be used as an SPI port (serial port mode 0 on the standard 80C32) or an RS232 port (serial port mode 1, 2, or 3 on the standard 80C32). • The SPI port can be used to communicate with an OSD chip, DAC, and so on. • The RS232 port can be used to communicate with an auto-alignment system, by using a 18.432 MHz crystal. Maximum baud rate is 19200 bps. G. DDC Port (Display Data Channel Port) The DDC port is composed of the SIO1 and DDC1 ports, and the SIO1 port shares the DSDA pin with the DDC1 port (as shown in Figure 5). The DDC port is designed to support DDC1, DDC2B, and DDC2B+ applications. G-1 SIO1 Port SIO1 is an I2C serial I/O port. SIO1 provides a serial interface that meets the I2C bus specification 2 and supports all transfer modes from and to the I C bus. The SIO1 port handles byte transfers autonomously. The W78C354 interfaces to the SIO1 port through the following four special function registers: S1CON (SIO1 control register), S1STA (SIO1 status register), S1DAT (SIO1 data register), and S1ADR (SIO1 address register). The SIO1 port interfaces to the DDC I2C bus via two pins: P1.2 / DSCL (DDC I2C serial clock line) and P1.3/DSDA (DDC I2C serial data line). The output latches of P1.2 and P1.3 must be set to "1" in order to enable the SIO1 port. For more detailed information, refer to the description of the Philips I2C bus. G-1.1 S1ADR (SIO1 Address Register) (DAH) The W78C354 can read from and write to this 8-bit newly added SFR S1ADR. When the the SIO1 port is in a master mode, the content of this register is irrelevant. In slave mode, the seven most significant bits must be loaded with the address that owns the slave. - 18 - W78C354 7 S1ADR X 6 X 5 X 4 X 3 X 2 X 1 X 0 - |--------------- Address that owns slave ---------------| G-1.2 S1DAT (SIO1 Data Register) (DBH) This register contains a byte of serial data that is waiting to be transmitted or has just been received. When the W78C354 is not performing a shifting operation, data can be read from or written to SFR S1DAT. Data in the S1DAT remain stable as long as SI is set. Data in the S1DAT are shifted from the most significant bit to the least significant bit, and while data are being shifted out, data on the bus are simultaneously being shifted in. S1DAT always contains the last data byte present on the bus. Thus, if arbitration is lost, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. 7 S1DAT SD7 LSB Eight bits of data in the S1DAT are shifted out or in, followed by an acknowledge bit. The acknowledge (ACK) bit is controlled by the SIO1 port hardware and cannot be accessed by the W78C354. Serial data are shifted through the ACK flag into S1DAT on the rising edges of the serial clock pulses on the SCL line and are shifted out from the S1DAT on the falling edges of the SCL clock pulse. When a byte has been shifted into the S1DAT, the serial data are available in S1DAT, and the acknowledge bit is returned by the control logic during the ninth clock pulse. G-1.3 S1CON (SIO1 Control Register) (D8H) The newly added SFR S1CON can be read or written by the programmer. Two bits (SI and STO) are affected by the SIO1 port hardware. When a serial interrupt is requested, the bit SI is automatically set, and when a stop condition is present on the bus, the bit STO is cleared. The bit STO is also cleared when ENS1 = "0." 7 S1CON 6 5 4 STO 3 SI 2 AA 1 CR1 0 CR0 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0 MSB CR2 ENS1 STA G-1.4 ENS1 (SIO1 Enable Bit) When the bit ENS1 is "0," the SDA and SCL outputs are in a high impedance state, the SIO1 port is in the "not addressed" slave mode, and no other bits are affected, except that the bit STO in S1CON is forced to "0." P1.2 and P1.3 may be used as open drain I/O pins. When ENS1 is "1," SIO1 is enabled. The P1.2 and P1.3 pins must be set to high. - 19 - Publication Release Date: October 1996 Revision A1 W78C354 G-1.5 STA (SIO1 Start Flag) When STA is "1," the SIO port will enter the master mode. After the SIO1 port checks the status of the I2C bus, it will generate a start condition if the bus is free. If the bus is not free, the SIO1 port will wait for a stop condition and then generate a start condition after a delay. If the bit STA is set while SIO1 is already in master mode and one or more bytes are to be transmitted or received, SIO1 will transmit a repeated start condition. The bit STA may also be set when SIO1 is an addressed slave. When STA is "0," no start condition or repeated start condition will be generated. G-1.6 STO (SIO1 Stop Flag) When STO is "1," the SIO1 port is in the master mode and a stop condition is transmitted to the I2C bus. When the stop condition is detected on the bus, the SIO1 port will clear STO. In the slave mode, STO may be set to recover from an error condition. In this case, no stop condition exists the I2C bus, but the SIO1 port behaves as if a stop condition has been received and switches to the defined "not addressed" slave receiver mode. STO is automatically cleared by hardware. G-1.7 SI (SIO1 Serial Interrupt Flag) When SI is "1," if the bits EA and ES1 (in the IE register) are also set, then once a serial interrupt is requested, SI will automatically be set by hardware. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. When the bit SI is "1," the low period of the serial clock on the SCL pin is extended, and the serial transfer is suspended. SI must be reset by software. When SI is "0," no serial interrupt is requested, so there is no extension of the serial clock on the SCL pin. G-1.8 AA (SIO1 Assert Acknowledge Flag) If AA is "1," an acknowledge signal (low level to the SDA pin) will be generated during the acknowledge clock pulse on the SCL pin when: (1) The address owning the slave has been received. (2) A data byte has been received while the SIO1 port is in the master receiver mode. (3) A data byte has been received while the SIO1 port is in the addressed slave receiver mode. If the bit AA is "0," a not acknowledge signal (high level to the SDA pin) will be generated during the acknowledge clock pulse on the SCL pin when: (1) A data byte has been received while the SIO1 port is in the master receiver mode (2) A data byte has been received while the SIO1 port is in the addressed slave receiver mode. G-1.9 CR0, CR1 and CR2 (SIO1 Clock Rate Bits) When the SIO1 port is in master mode, these three bits will determine the serial clock frequency (see the table below). These bits are unimportant when SIO1 is in slave mode. In slave mode, the SIO1 2 port will automatically synchronize with any clock frequency up to 100 KHz on the I C bus. - 20 - W78C354 Table 3. Serial clock rates BIT FREQUENCY (KHz) AT THE SCL PIN CR2 0 0 0 0 1 1 1 CR1 0 0 1 1 0 0 1 CR0 0 1 0 1 0 1 0 16 MHz 63 71 83 100 17 18.432 MHz 72 82 96 19 20 MHz 78 89 20 FORMULA FOSC/256 FOSC/224 FOSC/192 FOSC/160 FOSC/960 FOSC/120 FOSC/60 G-1.10 S1STA (SIO1 Status Register) (D9H) The newly added SFR S1STA is an 8-bit read-only register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possibile status codes. When the S1STA contains F8H, no serial interrupt is requested. All other the S1STA values correspond to defined SIO1 states (refer to the Philips specification for the I2C bus). When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is present in the S1STA one machine cycle after the bit SI is set by hardware and is still present one machine cycle after the bit SI has been reset by software. G-2 DDC1 Port DDC1 is a serial output port that supports DDC1 communication. After the DDC1 control circuit loads the next data byte from the data buffer to the shift register and generates a DDC1INT signal to the CPU, eight data bits and one zero (for the "acknowledge" signal) are shifted out to the DSDA pin sequentially on each rising edge of the VIN signal. In the interrupt service routine, the W78C354 should fetch the next byte of EDID data and write it to SFR DDC1. If the bit ENDDC1 of SFR CONTREG1 is cleared to zero, the shift register is stopped, and the DSDA output is kept high. • • One DDC1 port to support DDC1; ENDDC1 must be set to 1. One SIO1 port support DDC2B/2B+; ENDDC1 must be set to 0. - 21 - Publication Release Date: October 1996 Revision A1 W78C354 SIO1 port SCL IN SCL OUT P1.2/DSCL SDA IN SDA OUT Support DDC2B/2B+ DDC1 port SDA SCL Support DDC1 0 1 P1.3/DSDA ENDDC1 V IN Figure 5. DDC port H. Interrupts The W78C354 has six interrupt sources. Five (except INT1 , at vector address 0013H) are identical to those in the 80C51 series, while the sixth (at vector address 002BH) is newly added. All the interrupt sources and the corresponding interrupt vector addresses for the W78C354 are described in the following table: SOURCE IE0 TF0 *1 TF1 RI+TI *2 Notes: *1. DSCLINT+ADCINT+TIMEOUT+SOAINT+VEVENT+PARAINT+DDC1INT. *2. This is the interrupt generated by the I C in the DDC port. 2 VECTOR ADDRESS 0003H 000BH 0013H 001BH 0023H 002BH DESCRIPTION External interrupt 0 (same as the 80C31) Timer 0 overflow interrupt (same as the 80C31) Replaces INT1 of the 80C31 Timer 1 overflow interrupt (same as the 80C31) Serial port interrupt (same as the 80C31) New (similar to TF2+EXF2 in the 80C32) PRIORITY Highest Lowest - 22 - W78C354 H-1. Interrupt at Vector Address 0013H The interrupt at vector address 0013H is driven by another seven different sources, which are a highto-low transition on the DSCL pin of the DDC port, the A/D converter, the auto-reload timer, the SOA output, Vsync frequencg event, the parabola interrupt generator, and DDC1 in the DDC port. These sources are described below. (1) DSCLINT: Interrupt generated when DSCL-pin changes from high to low and stays high for 12 clock periods. Once DDCLINT interrupt is received, the programmer should disable DDC1 port by writing "0" to the bit ENDDC1 of SFR CONTREG1. 16 MHz DSCL low (2) ADCINT: Refer to section K for a description of the ADC. (3) TIMEOUT: Refer to section I for a description of the auto-reload timer. (4) SOAINT: When an SOA condition occurs, SOAINT will interrupt the CPU to perform the necessary operations. Refer to section M-6 for a description of the SOA function. (5) VEVENT: When the V retrace signal is detected or the V-frequency counter overflows, which means that the Vsync frequency is so low that it is out of range, the W78C354 will generate the VEVENT interrupt. In the interrupt service routine, the programmer can check bit 3 (NOV) of SFR STATUS to determine whether the V frequency is out of range. If NOV = 1, the software should go to DPMS process. If NOV = 0, the software can read the HFCOUNT and VFCOUNT registers, and the bits HP and VP of STATUS will determine the preset mode of the incoming frequency. Refer to section M for a description of the sync processor. (6) PARAINT: The parabola interrupt generator is used to generate interrupts to the W78C354 for loading the parabola waveform data to dynamic DACs. The software should calculate the value of the PARAH and PARAL registers by (Vcount × 16) ÷ section number. Refer to section J for a description of the parabola interrupt generator. (7) DDC1INT: Refer to section G-2 for a description of the DDC1 operation. Programmer must read SFR INTVECT (bits 0−6) to determine the source of the interrupt request. These seven interrupt sources can be enabled individually by setting SFR INTMSK (bits 0−6). The newly added interrupt at vector address 002BH is driven by the I2C circuit in the DDC port. The interrupt enable control bits for the two interrupts at 0013H and 002BH are IE.2 and IE.5 in the IE register, respectively. The interrupt priority control bits are IP.2 and IP.5 in the IP register. The interrupts can be disabled by clearing IE.7 (disable all interrupts). For example, the programmer can enable the A/D converter interrupt by the "MOV INTMSK, #00000010B" instruction. When the 750 nS 18.432 MHz 651 nS 20 MHz 600 nS - 23 - Publication Release Date: October 1996 Revision A1 W78C354 converter is completed, the interrupt will be generated and the bit ADCINT in the INTVECT will automatically be set. To clear the bit ADCINT to receive the next interrupt, the programmer can use the "MOV INTVECT, #00000010B" instruction. See Figure 6. Vector Address IE 0003H IE.0 IP IP.0 IP.1 INTMSK INTVECT DSCLINT source ADCINT source TIMEOUT source SOAINT source VEVENT source PARAINT source DDC1INT source Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 IE0 TF0 High Priority Low Priority 000BH IE.1 Interrupt Polling Sequence DSCLINT ADCINT TIMEOUT SOAINT VEVENT PARAINT DDC1INT OR 0013H IE.2 IP.2 TF1 RI+TI I2C in DDC port 001BH IE.3 IP.3 IP.4 IP.5 IE.7 0023H IE.4 002BH IE.5 Figure 6. Interrupt block diagram H-2. Newly Added External Interrupt 0 Function (INT0) INT0 can be set to be falling-edge or low-level active by setting/clearing the IT0 bit in TCON. If programmers wish to use a rising-edge or high-level signal as interrupt on the pin INT0, INT0 can also be activated by setting/clearing the EINTES bit in SFR CONTREG2 (see Figure 7). In other words, there are four trigger types for INT0 (falling-edge, low-level, rising-edge. and high-level). In the initial state, INT0 will be triggered by a rising-edge or high-level signal. EINTES INT0 (P3.2) 1 0 0 IT0 1 IE0 Figure 7. External interrupt 0 - 24 - W78C354 INTVECT: Interrupt Vector Register (B2H) BIT 0 1 2 3 4 5 6 7 Notes: 1. Each of the above interrupt flags will be set by hardware when the corresponding interrupt source is masked by writing a "1" to the the INTMSK register. 2. To clear the interrupt flag, write a "1" (not "0") to the corresponding bit. NAME DSCLINT ADCINT TIMEOUT SOAINT VEVENT PARAINT DDC1INT - FUNCTION Set by hardware when DSCL is toggled low. Set by hardware when ADC conversion is completed. Set by hardware when autoload timer times out. Set by hardware when SOA is high. Set by hardware when Vsync or vertical frequency counter times out. Set by hardware when parabola interrupt generator times out. Set by hardwrae when DDC port functions in the DDC1 mode . Reserved. INTMSK: Interrupt Mask Register (95H) BIT 0 1 2 3 4 5 6 7 NAME DSCLINT ADCINT TIMEOUT SOAINT VEVENT PARAINT DDC1INT 0: Disable, 1: Enable. Enable/Disable ADCINT interrupt. 0: Disable, 1: Enable. Enable/Disable TIMEOUT interrupt. 0: Disable, 1: Enable. Enable/Disable SOAINT interrupt. 0: Disable, 1: Enable. Enable/Disable VEVENT interrupt. 0: Disable, 1: Enable. Enable/Disable PARAINT interrupt. 0: Disable, 1: Enable. Enable/Disable DDC1INT interrupt. 0: Disable, 1: Enable. Reserved FUNCTION Enable/Disable DSCLINT interrupt. - 25 - Publication Release Date: October 1996 Revision A1 W78C354 I. Timer/Counter The W78C354 has two 16-bit timer/counters, Timer/counter 0 and Timer/counter 1, which are identical with those on the standard 80C32, and one 8-bit auto-reload timer. Once the "MOV AUTOLOAD, #data" instruction is executed, the auto-reload timer will load the specified data and start to count. If the TIMEOUT bit in INTMSK is set, the auto-reload timer will periodically generate an interrupt to the CPU. The auto-reload timer interval is programmable: • • • • Minimum timer interval = 1/(FCLOCK ¡Ò 1024) Desired timer interval = Minimum interval × [(preset value of the AUTOLOAD)+1] Maximum timer interval = Minimum interval × 255 AUTOLOAD: 8-bit auto-reload timer register which stores preset value. 16 MHz Minimum Interval Maximum Interval 64 µS 16.3 mS 18.432 MHz 55 µS 14.2 mS 20 MHz 51.2 µS 13.1 mS J. Parabola Interrupt Generator The parabola interrupt generator is a 16-bit binary count-up auto-reload timer that is used to generate the parabola interrupt to the W78C354 for loading parabola waveform data to dynamic DACs. It periodically generates an interrupt by setting the PARAINT bit in INTMSK, if the "MOV PARAL, #Low byte data" and "MOV PARAH, #High byte data" instructions are executed. The parabola interrupt generator period is programmable: Time base = 1/FCLOCK • • • • Desired interrupt period = Time base × {[preset value of the (PARAH, PARAL)]+1} Maximum period = Time base × 65535 PARAL: Parabola interrupt generator register that stores low byte preset value PARAH: Parabola interrupt generator register that stores high byte preset value K. 6-bit A/D Converter The 6-bit analog-to-digital converter uses the successive approximation method to convert one of the four analog input channels into a digital data value. The A/D converter resolution is ±1 LSB, and the conversion time is 100 usec. The result is read from SFR ADC. Bit-pairs (ADCS1, ADCS2) in SFR CONTREG1 are used to select one of the four channels as the analog input (see Table 3). Conversion is started by setting the bit ADCSTRT in CONTREG1 by software. When the A/D conversion is completed, the ADCSTRT bit is automatically cleared by hardware to stop the A/D converter's operation, and the ADCINT bit in INTVECT is set by hardware at the same time. To enable the A/D converter interrupt, set the ADCINT bit in INTMSK. Table 4. Select A/D converter channel (ADCS1, ADCS0) Selected channel (0, 0) ADC0 - 26 (0, 1) ADC1 (1, 0) ADC2 (1, 1) ADC3 W78C354 L. PWM DACs There are two 12-bit and fourteen 8-bit PWM static DACs and one 12-bit and three 8-bit PWM dynamic DACs on this chip. The number of the PWM outputs is different with the package. 68-PIN PLCC 8-bit SDAC 12-bit SDAC 8-bit DDAC 12-bit DDAC Note : 4* : the SDACS share with P2.4~P2.7 48-PIN DIP 8 + 4* 1 3 1 40-PIN DIP 8 + 4* 1 1 1 14 2 3 1 L-1.1 14-channel 8-bit PWM Static DAC The static DACs (SDAC0 to 13) are used to generate DC voltage control (0 to 5V) by an RC circuit, as shown in Figure 8, and to execute the "MOV SDACn, #Value" instruction. There are 14 registers, corresponding to the 14 channels of 8-bit PWM output. The unused PWM channel can be used as an output pin, since 0 or 5V can be obtained from the pin. • • • Duty cycle of the PWM output = Preset value of SDACn ¡Ò 255, where n = 0 to 13 DC voltage after low-pass filter = VCC × duty cycle SDAC0−SDAC13: 8-bit PWM static DAC registers storing preset values PRESET VALUE 0 1 n 255 DUTY CYCLE 0/255 1/255 n/255 255/255 DC VOLTAGE 0V 1/255 × 5V n/255 × 5V +5V • PWM frequency FPWM = FCLOCK ¡Ò 255 Fclock FPWM TPWM 16 MHz 62.745 KHz 15.94 µS 18.432 MHz 72.282 KHz 13.83 µS 20 MHz 78.431 KHz 12.75 µS - 27 - Publication Release Date: October 1996 Revision A1 W78C354 W78C354 Low-pass filter 8/12bit SDAC R C V OUTPUT Figure 8. SDAC application circuit (where T = RC, VOUTPUT = VCC × n/255, if T >> TPWM) When bit ENM0 of SFR CONTREG2 is set to high, SDAC0 will output PWM in one frame and then keep low for the next frame. Thus SDAC0 can be used for H moire cancellation. SDAC1 can also be configured with the same operation for V moire cancellation by setting bit ENM1. The application circuit is shown below. SDAC0 (H-moire) SDACx (H-phase) H-phase Control Circuit Figure 9. Moire application circuit L-1.2 Two-channel 12-bit PWM/BRM Static DAC The two 12-bit PWM/BRM outputs (BSDAC0,1) are composed of an 8-bit PWM and a 4-bit BRM (bit rate multiplier). The value of the 4-bit BRMs (SFRs SBRM0, 1) determine to which positions one clock pulse will be added in every 16 PWM outputs of 12-bit PWM/BRM static DAC0,1. When the "MOV BSDACn, #value" or "MOV SBRMn, #value" instruction is executed, the related output pin will output the PWM waveform needed by the user. The 12-bit PWM/BRM frequency is the same as that of the 8-bit PWM output. VALUE OF SBRM0 OR SBRM1 (BIT3 BIT2 BIT1 BIT0) 0000 0001 0010 0100 1000 ONE CLOCK PLUSE INCREMENTED IN THE N-TH OUTPUT EVERY 16 PWM OUTPUTS None n=8 n = 4, 12 n = 2, 6, 10, 14 n = 1, 3, 5, 7, 9, 11, 13, 15 - 28 - W78C354 In the following table, in the positions marked with an "¤" one clock pulse will be added to every 16 PWM outputs. SBRM0, SBRM1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 2 ¤ ¤ ¤ ¤ 3 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 4 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ PWM/BRM OUTPUT CYCLE 5 6 7 8 9 10 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 11 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 12 ¤ ¤ ¤ ¤ 13 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 14 ¤ ¤ ¤ ¤ 15 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ L-2. Three-channel 8-bit and One-channel 12-bit PWM Dynamic DACs The 8-bit PWM dynamic DACs (DDAC0-2) and 12-bit PWM dynamic DAC (BDDAC) are used to achieve geometric compensation by generating a parabola output waveform by the integrator circuit shown in Figure 6 and by executing the "MOV DDACn, #value," "MOV BDDAC, #value," or "MOV DBRM, #value" instructions by a software program. The PWM waveforms and operating criteria of the related registers are similar to those of the static DACs. The unused dynamic DACs can be used as static DACs. C W78C354 2.5 V V output 8/12 bit DDAC R Figure 10. Dynamic DAC application circuit - 29 - Publication Release Date: October 1996 Revision A1 W78C354 The objective of the dynamic DAC is to generate geometric compensation parabola waveforms. Several examples are given below. L-3. Examples L-3.1 DDAC0 used to compensate for H size distortion 1. Pincushion (PCC amplitude) 2. Trapezoid (Keystone) 25% 3. CBOW (S-comp) 25% 4. PCC corner L-3.2 DDAC1 used to compensate for H center distortion 1. Pin balance (Bow) 2. Key balance (Tilt) M. Sync Processor The sync processor is composed of a polarity detector, sync separator, H/V frequency counter, H/V dummy frequency generator, H-clamp generator, and SOA generator. Figure 11 is a block diagram of the sync processor. The related control bits are defined in SFR CONTREG2. The sync processor supports powerful functions that enable users to employ the V/H , H-clamp, and SOA outputs to easily control and protect the deflection circuit. - 30 - W78C354 VSPS HSPS DUMMYEN ENVS 0 VIN HIN Polarity Detect & HREST Restoration VREST VSEP Sync Separator 1 0 1 H/V Frequency Counter VDUMMY H/V Dummy Sync Generator 0 HDUMMY 1 0 HOUT 1 H - Clamp 0 VOUT 1 AD[7:0] VDISHC H-Clamp Generator SOA Generator SOA Figure 11. Sync processor M-1. Polarity Detector The H/V polarity is detected automatically and can be read from SFR STATUS. The polarity of the H/V input signals is then restored (they signals become HREST/VREST) for internal processing and output to HOUT/VOUT to drive the deflection circuit. Maximum sync width to HIN pin: (1/FCLOCK ) × 214 Maximum sync width to VIN pin: (1/FCLOCK ) × 214 FCLOCK Max. sync width for HIN Max. sync width for VIN M-2. Sync Separator Vsync is separated from the composite sync automatically, without any additional software programming. Figure 12 shows the waveforms of VOUT that result from a composite or non-composite Hsync input. If ENVS = 1, the limitations on the Vsync signal are: VIN pulse width must be larger than Wvmin = [(1/FCLOCK)¡Ñ128.5] ± 1/(2 × FCLOCK) VOUT is delayed from VIN signal by Tdelay = [(1/FCLOCK)¡Ñ128.5] ± 1/(2 × FCLOCK) 16 MHz 1024 µS 1024 µS 18.432 MHz 888 µS 888 µS 20 MHz 819 µS 819 µS - 31 - Publication Release Date: October 1996 Revision A1 W78C354 FCLOCK 1/Fclock Min. Vsync width (Wvmin) VOUT delay from VIN (Tdelay) 16 MHz 62.5 nS 8031 ± 31 nS 8031 ± 31 nS 18.432 MHz 54 nS 6939 ± 27 nS 6939 ± 27 nS 50 nS 6425 ± 25 nS 6425 ± 25 nS 20 MHz 1. Withot composite sync HIN VIN W vmin H OUT VOUT Tdelay 2. With composite sync H IN (H+V) V IN HOUT VOUT Ò Figure 12. Vsync separator output (when DUMMYEN = 0, ENVS = 1) M-3. Horizontal & Vertical Frequency Counter There are two 16-bit counters that automatically count the horizontal and vertical frequency. When a VEVENT interrupt occurs, the W78C354 reads the count value (HCOUNT and VCOUNT) from the 8-bit counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH, and VFCOUNTL) to calculate the H and V frequency by the formulas listed below. - 32 - W78C354 V frequency: • • • Resolution of V frequency counter: VRESOL = (1/FCLOCK ) × 16 V-frequency: VFREQ = 1/(VCOUNT × VRESOL) Lowest V frequency can be detected: FCLOCK ¡Ò 1048576 H frequency: • • • Resolution of H frequency counter: HRESOL = (1/FCLOCK) ¡Ò 8 H-frequency: HFREQ = 1/(HCOUNT × HRESOL) Lowest H frequency can be detected: FCLOCK ¡Ò 8192 16 MHz Vresol Lowest VFREQ Hresol Lowest HFREQ 1 µS 15 Hz 7.8 nS 1.9 KHz 18.432 MHz 868 nS 17.6 Hz 6.8 nS 2.3 KHz 20 MHz 800 nS 19 Hz 6.3 nS 2.4 KHz M-4. Dummy Frequency Generator The dummy H and V frequencies are generated for factory burn-in measurement and for displaying a warning message when there is no input H/V frequency. The dummy sync generator includes two newly added SFRs, DHREG and DVREG. DHREG is a 4-bit register used to determine the dummy Hsync output frequency. DVREG is an 8-bit register that can be used to preset a constant into DVREG to determine the dummy Vsync output frequency by the formulas listed below. • • Dummy Hsync frequency FdH = FCLOCK ¡Ò 32 ¡Ò (DHREG+1) Dummy Vsync frequency FdV = FdH ¡Ò 8 ¡Ò (DVREG+1) Example: Assume system clock = 16 Mhz DHREG 15 12 10 9 7 5 4 FDH 31.25K 38.5K 45.5K 50K 62.5K 82K 100K DVREG 48 59 70 77 96 127 155 FDV 79.7 Hz 80.2 Hz 80.1 Hz 80.1 Hz 80.5 Hz 80.1 Hz 80.1 Hz - 33 - Publication Release Date: October 1996 Revision A1 W78C354 The relations between the bit DUMMYEN and the outputs of the H/V frequencies are listed below: HOUT DUMMYEN = 0 DUMMYEN = 1 M-5. H-clamp Pulse Generator If the P14SF bit is set in the newly added SFR CONTREG4 (bit-addressable), the output pin P1.4 can be used as the H-clamp pulse output (refer to Figure 13). The Hsync trigger type can be selected to generate the H-clamp output pulse, and the pulse width of the H-clamp output can be determined by programming the bits HCES, HCWS1, and HCWS2 in SFR CONTREG1. For details, see the following figure and description. CONDITION Of P14SF P14SF = 0 P14SF = 1 & P1.4 = 0 PORT 1.4 I/O PIN FUNCTION General I/O pin H-clamp pulse output HREST HDUMMY VOUT VREST (if ENVS = 0) VSEP (if ENVS = 1) VDUMMY P14SF P1.4 output latch H-Clamp pulse 0 1 P1.4/HCLAMP Figure 13. Alternate function of P1.4 1. Select the leading edge or trailing edge of Hsync: • • HCES = 0: select leading edge HCES = 1: select trailing edge - 34 - W78C354 (a) Negative polarity Hsync Hsync (b) Postive polarity Hsync Hsync P1.4 (Leading-edge) P1.4 (Leading-edge) P1.4 (Trailing-edge) P1.4 (Trailing-edge) Figure 14. Pin P1.4 outputs the H-clamp pulse at the leading edge or trailing edge of Hsync. 2. Pulse width of H-clamp pulse: • • Select the weighting of H-clamp pulse by programming bits HCWS0 and HCWS1 in CONTREG1 Pulse width of H-clamp output: [(1/FCLOCK) × Weighting] ± [ 1/(2 × FCLOCK)] WEIGHTING 4.5 8.5 16.5 32.5 16 MHz 281 ±31 nS 531 ±31 nS 1031 ±31 nS 2031 ±31 nS 18.432 MHz 244 ±27 nS 461 ±27 nS 896 ±27 nS 1764 ±27 nS 20 MHz 225 ±25 nS 425 ±25 nS 825 ±25 nS 1625 ±25 nS (HCWS1, HCWS0) (0, 0) (0, 1) (1, 0) (1, 1) Hsync H-clamp output Figure 15. Pulse width of H-clamp output - 35 - Publication Release Date: October 1996 Revision A1 W78C354 If the bit VDISHC of SFR CONTREG2 is set high, the H-clamp pulse output will be disabled in the V sync pulse period. VDISHC VIN HIN H-clamp Figure 16. Disable H-clamp output M-6. Safe Operation Area (SOA) Output The purpose of the SOA output is to protect the HOT (horizontal oscillating transistor) and other critical circuitry by responding quickly if the Hsync frequency suddenly drops below a preset boundary frequency. When the Hsync frequency is lower than the preset boundary frequency for three consecutive cycles or stops for a certain period, the SOA pin (P1.5) will change to a "high" state to activate an external circuit to protect the monitor. If the bit P15SF is set in SFR CONTREG4, the pin P1.5 can be used as the SOA output (refer to Figure 17). The SOA pin can be released by writing any value to SFR SOACLR. CONDITION Of P15SF P15SF = 0 P15SF = 1 & P1.5 = 0 PORT 1.5 I/O PIN FUNCTION General I/O pin SOA output P15SF P1.5 output latch SOA output 0 P1.5/SOA 1 Figure 17. Alternate function of P1.5 • Boundary frequency HBOUN D = 2 MHz ÷ (Value of SOAREG) Example: If 50 KHz is considered the boundary frequency, then value of SOAREG = 2M ¡Ò 50K = 40. • No Hsync response time = 2048 × (1/FCLOCK). - 36 - W78C354 16 MHz No Hsync response time 128 µS 18.432 MHz 111 µS 20 MHz 102 µS M-7. Self-test Pattern Output When the dummy frequency generator is enabled, if bit P23SF of SFR CONTREG4 is set, the STP output will provide a checkerboard pattern for burn-in or self-diagnostic purposes. The bit INVSTP of CONTREG4 can invert the checkerboard pattern to avoid phosphor damage during factory burn-in. CONDITION Of P23SF P23SF = 0 P23SF = 1 & P2.3 = 0 PORT 2.3 I/O PIN FUNCTION General I/O pin STP output P23SF P2.3 output latch STP output 0 P2.3/STP 1 Figure 18. Alternate function of P2.3 INVSTP = 0 INVSTP = 1 Figure 19. Checkerboard pattern - 37 - Publication Release Date: October 1996 Revision A1 W78C354 N. Power Supervisor, Watchdog Timer, and Reset Circuitry Reset signals can come from three sources: an external reset input (active low), power-low detection, or the watchdog timer. Figure 20 is a block diagram of the reset circuitry. The power-low detection circuit generates a reset signal if VCC falls below 3.8V, and the reset signal will keep twenty-four machine cycle after VCC rises to 4.3V. Thus we can make sure the chip can be reseted perfectly when the monitor is first powered on, and avoid the w78c354's overwriting the E2PROM mistakenly when the monitor is powered down. The power-low detection circuit can be enabled or disabled by code option 1. The purpose of the watchdog timer is to reset the W78C354 if it enters an abnormal processor state (caused by electrical noise or RFI, for example). The clock source of the watchdog timer comes from the internal system clock. The timer can be enabled or disabled by the code option 2. When enabled, the watchdog circuitry will generate a system reset if the user's program fails to reload the watchdog timer within a specified length of time after executing the "MOV WDTCLR, # Value" instruction. This length of time is known as the "watchdog interval" (TWDT ). Four selections are available for the watchdog interval (type A, B, C, and D); the selections, which are programmed by code option 3, are indicated by the formulas in table below. There are three code options in the reset circuitry: • • • Code option 1: Enable/disable the power-low detector. Code option 2: Enable/disable the watchdog timer. Code option 3: Select one watchdog interval (type A, B, C, D as listed in the table below.) External reset Code option 3 Watchdog interval Watchdog Timer Code option 2 Enable/Disable System Reset Power-low Detector Code option 1 Enable/Disable Figure 20. Reset circuitry - 38 - W78C354 Table4. Watchdog Interval T WDT CODE OPTION 3 Type-A Type-B Type-C Type-D FORMULA 2 /FCLOCK 2 /FCLOCK 2 /FCLOCK 2 /FCLOCK 24 23 21 19 FCLOCK 16 MHz 32 mS 131 mS 524 mS 1048 mS 18.432 MHz 28 mS 113 mS 452 mS 905 mS 20 MHz 26 mS 104 mS 417 mS 834 mS ABSOLUTE MAXIMUM RATINGS PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VCC−VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VCC +0.3 70 +150 UNIT V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC ELECTRICAL CHARACTERISTICS VCC−VSS = 5V ± 10%, TA = 25° C, FOSC = 20 MHz, unless otherwise specified PARAMETER Operating Voltage Operating Current Idle Current Logic 0 Input Current P1, P2, P3 (except P1.0 to P1.3,P1.5) SYM. VDD IDD IIDLE IIN1 CONDITIONS MIN. 4.5 TYP . 5 - MAX. 5.5 65 30 -10 UNIT V mA mA µA No load, VDD = 5.5V Idle mode, VDD = 5.5V VDD = 5.5V VIN = 0V -75 Input Current RESET [*1] IIN2 VDD = 5.5V VIN = 0V -250 - - µA µA µA Input Current HIN, VIN [*2] IIN3 ILK VDD = 5.5V VIN = VDD VDD = 5.5V 0V < VIN < VDD -10 - +30 +10 Input Leakage Current P1.0 to P1.3, ADC0 to ADC3 - 39 - Publication Release Date: October 1996 Revision A1 W78C354 DC Electrical Characteristics, continued PARAMETER Logical 1-to-0 Transition Current P1, P2, P3 [*3] (except P1.0 to P1.3, P1.5) SYM. ITL CONDITIONS VDD = 5.5V VIN = 2.0V MIN. -650 TYP. - MAX. - UNIT µA Input Low Voltage RESET , OSCIN [*4] (except P1.0 to P1.3, P1.5) VIL1 VDD = 4.5V 0 - 0.8 V Input Low Voltage HIN, VIN [*5] VIL2 VIL3 VIH1 VDD = 4.5V VDD = 4.5V VDD = 5.5V 0 0 2.4 - 0.8 1.5 VDD +0.2 V V V Input Low Voltage P1.0 to P1.3 Input High Voltage P1, P2, P3 (except P1.0 to P1.3, P1.5) Input High Voltage RESET , OSCIN [*4] Input High Voltage HIN, VIN [*5] VIH2 VDD = 5.5V 3.5 - VDD +0.2 V VIH3 VIH4 VOL1 VDD = 5.5V VDD = 5.5V VDD = 4.5V IOL = +4 mA 2.4 3.0 - - VDD +0.2 VDD +0.2 0.45 V V V Input High Voltage P1.0 to P1.3 Output Low Voltage P1.4, P1.5, P2.2 to P2.7 SDAC0 to SDAC13 HOUT, VOUT Output Low Voltage P1.0, P1.1 Output Low Voltage P1.2, P1.3 Output Low Voltage P2.0, P2.1 Output Low Voltage P3, P4 VOL2 VOL3 VOL4 VOL5 VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +6 mA VDD = 4.5V IOL = +15 mA VDD = 4.5V IOL = +2 mA - - 0.4 0.4 0.45 0.45 V V V V - 40 - W78C354 DC Electrical Characteristics, continued PARAMETER Output Low Voltage BSDAC0-1, DDAC0-2, BDDAC Output High Voltage P1.4, P2, P3 Output High Voltage P1.5, SDAC0-13, HOUT, VOUT, Special Function of P1.4 and P2.3~P2.7 Output High Voltage, BSDAC0-1, DDAC0-2, BDDAC Output High Voltage P4 SYM. VOL6 CONDITIONS VDD = 4.5V IOL = +8 mA MIN. - TYP. - MAX. 0.45 UNIT V VOH1 VOH2 VDD = 4.5V IOH = -100 µA VDD = 4.5V IOH = -4 mA 2.4 2.4 - - V V VOH3 VDD = 4.5V IOH = -8 mA 2.4 - - V VOH4 VDD = 4.5V IOH = -2mA 2.4 - - V Notes: 1. The RESET pin has an internal pull-up resistor with a resistance of about 30 KΩ. 2. Pins HIN and VIN have an internal pull-down resistor with a resistance of about 200 KΩ. 3. Pins P1, P2, and P3 (except P1.0-P1.3 and P1.5) source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 4. RESET is a Schmitt trigger input, and OSCIN is a CMOS input. 5. HIN and VIN are Schmitt trigger inputs. - 41 - Publication Release Date: October 1996 Revision A1 W78C354 TYPICAL APPLICATION CIRCUIT W78C354 MC141540 VFLB HFLB SDA P2.0 P2.1 P2.2 HOUT VOUT OSCOUT 16M OSCIN 30P 30P VDD P3.3 P3.4 P3.5 P4.0 P4.1 P4.2 P1.4 P1.5 P2.3 Power saving Degauss Mute CS0 CS1 CS2 SOA Output H-Clamp Output STP Output SDAC0 SDAC1 SDAC2 SDAC3 SDAC4 SDAC5 SDAC6 SDAC7 P2.4/SDAC10 P2.5/SDAC11 P2.6/SDAC12 P2.7/SDAC13 BDDAC DDAC0 H-Size V-Size H-Phase V-Center Brightness Contrast Rotation R-Gain B-Gain R-Cut off G-Cut off B-Cut off TRAP\CBOW\PIN TILT\BOW OSD SCL SS 24C04 2 E PROM R7 SDA SCL R6 P1.1/ISDA P1.0/ISCL VDD R9 R8 P1.3/DSDA HIN VIN P1.2/DSCL / R S T A D C 0 P3.0/RXD P3.1/TXD Auto Alignment VGA VDD 10k R2 VDD S0 10uF R1 R3 S1 R4 S2 R5 S3 - 42 - W78C354 PACKAGE DIMENSIONS 68-pin PLCC HD D 9 1 68 61 10 60 Symbol Dimension In Inches Min. Nom. Max. Dimension In mm Min. Nom. Max. E HE GE 26 44 A A1 A2 b1 b c D E e GD GE HD HE L y Notes: 0.185 0.020 0.143 0.148 0.153 0.026 0.028 0.032 0.016 0.018 0.022 0.006 0.008 0.012 0.51 3.63 0.66 0.41 0.15 3.76 0.71 0.46 0.20 4.70 3.89 0.81 0.56 0.30 0.949 0.954 0.959 24.10 24.23 24.36 0.949 0.954 0.959 24.10 24.23 24.36 0.044 0.050 0.056 1.12 1.27 1.42 0.895 0.915 0.935 22.73 0.895 0.915 0.935 22.73 0.980 0.990 1.000 24.90 0.980 0.990 1.000 24.90 0.090 0.100 0.110 0.004 0 10 0 2.29 23.24 23.75 23.24 23.75 25.15 25.40 25.15 25.40 2.54 2.79 0.10 10 27 43 c θ L A2 A 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ Seating Plane e GD b b1 A1 y 48-pin DIP Symbol Dimension In Inches Min. Nom. Max. Dimension In mm Min. Nom. Max. A A1 A2 B B1 c D 48 25 0.21 0.01 0.15 0.01 0.04 0.00 0.59 0.54 0.09 0.12 0 0.63 0.15 0.16 0.01 0.02 0.05 0.05 0.01 2.45 0.60 0.55 0.2 3.8 0.4 1.2 3.9 0.4 1.2 5.3 4.0 0.5 1.3 0.3 62.4 15.4 14.1 2.7 3.5 15 D E E1 e1 L a eA S 0.01 0.2 0.2 2.46 62.2 0.61 14.9 15.2 0.55 13.8 13.9 2.2 3.0 0 2.5 3.3 E 1 0.10 0.11 0.13 0.14 15 0.65 0.67 16.0 0.08 16.5 17.0 2.1 1 24 S A1 A A2 L B B1 Base Plane Seating Plane E e1 a eA Notes: 1. Dimensions D Max. & S include mold flash or the bar burrs. C 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. - 43 - Publication Release Date: October 1996 Revision A1 W78C354 40-pin DIP Dimension In Inches Min. 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090 Symbol Dimension in mm Min. Nom. Max. 5.334 0.254 3.81 0.406 1.219 0.203 3.937 0.457 1.27 0.254 52.20 14.986 15.24 13.72 2.286 3.048 0 16.00 16.51 13.84 2.54 3.302 4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556 15 17.01 2.286 Nom. Max. 0.210 D 40 21 E1 A A1 A2 B B1 c D E E1 e1 L a 1 S A A2 L B B1 e1 20 E c A1 eA S Notes: Base Plane Seating Plane eA a 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 44 -