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PHY6212MAQB

PHY6212MAQB

  • 厂商:

    PHYPLUS(奉加微)

  • 封装:

    QFN48_7X7MM_EP

  • 描述:

  • 数据手册
  • 价格&库存
PHY6212MAQB 数据手册
PHY6212 Bluetooth LE 5.2 System on Chip Key Features • • • • • • • • • • • ARM® Cortex™-M0 32-bit processor Memory  512KB/2MB in-system flash memory  128KB ROM  138KB SRAM, all programmable retention in sleep mode  8-channel DMA 33/19 general purpose I/O pins  All pins can be configured as serial interface and programmable IO MUX function mapping  All pins can be configured for wake-up  18 pins for triggering interrupt  3 quadrature decoder(QDEC)  6-channel PWM  4-channel I2S  2-channel PDM  2-channel I2C  2-channel SPI  1-channel UART  JTAG DMIC/AMIC with microphone bias 3/8-channel 12bit ADC with low noise voice PGA 4-channel 24bit timer, one watchdog timer Real timer counter (RTC) Power, clock, reset controller Flexible power management  Supply voltage range 1.8V to 3.6V  Embedded buck DC-DC and LDOs  Battery monitor: Supports low battery detection Power consumption  0.7μA @ OFF Mode (IO wake up only)  2μA @ Sleep Mode with 32KHz RTC  Receiver: 6.7mA @sensitivity level  Transmitter: 6.7mA @0dBm TX power RC oscillator hardware calibrations  32KHz RC osc for RTC with +/-500ppm accuracy 32MHz RC osc for HCLK with 3% accuracy • High Speed Throughput  Support BLE 2Mbps Protocol  Support Data Length Extension  Throughput up to 1.6Mbps(DLE+2Mbps) • Support SIG-Mesh Multi-Feature  Friend Node  Low Power Node  Proxy Node  Relay Node • 2.4 GHz transceiver  Compliant to Bluetooth 5.2  Sensitivity: -97dBm@BLE 1Mbps data rate -103dBm@BLE 125Kbps data rate  TX Power -20 to +10dBm in 3dB steps  Single-pin antenna: no RF matching or RX/TX switching required  RSSI (1dB resolution) • AES-128 encryption hardware • Link layer hardware  Automatic packet assembly  Automatic packet detection and validation  Auto Re-transmit  Auto ACK  Hardware Address Matching  Random number generator • Operating temperature:  -40˚C ~+85 ˚C (Consumer)  -40 ˚C ~+105 ˚C (Industrial) • RoHS Package: QFN48/ QFN32 • Applications: wearables, beacons, appliances, home and building, health and medical, sports and fitness, industrial and manufacturing, retail and payment, security, data transmission, remote control, PC/mobile/TV peripherals, internet of things (IoT)  Copyright © 2021 Phyplus Microelectronics Limited All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. PHY6212 Product Specification v1.6 Liability Disclaimer Phyplus Microelectronics Limited reserves the right to make changes without further notice to the product to improve reliability, function or design. Phyplus Microelectronics Limited does not assume any liability arising out of the application or use of any product or circuits described herein. Life Support Applications Phyplus Microelectronics Limited’s products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Phyplus Microelectronics Limited customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Phyplus Microelectronics Limited for any damages resulting from such improper use or sale. Contact Details For your nearest dealer, please see www.Phyplusinc.com. Information regarding product updates, downloads, and technical support can be accessed through our homepage. Main Office: Shanghai 3F&4F, Building 23, Lane 676, Wuxing Road, Pudong, Shanghai Phone: +86 21 5899 0018 Email: info@phyplusinc.com Shenzhen Room 1205, No.10 Li Shan Road, Shenzhen China PHY6212 Product Specification v1.6 Revision History Date Version 2018.05 1.0 2019.06 1.1 Added “GPIO DC Characteristics” 2019.07 1.1 1. Added “Power consumption” in the home page 2. Added information about accuracy of RC osc in the home page 2019.08 1.2 Added “DMIC/AMIC Data Path” 2019.10 1.3 2019.11 1.4 2021.4 1.5 2021.7 1.6 Description 1. Updated the information of “Ordering information” 2. Updated the information of “in-system flash memory” and “Power consumption” Corrected the information of “PHY6212 (QFN32) Pin Functions – Pin2, 3, 4, 5, 7, 8” The following content has been added, updated or corrected:  “Operating Temperature” on cover: Added the temperature information of “Consumer” and “Industrial".  “6 Operating Conditions” on page 63: Added the temperature specification of “Consumer” and “Industrial” in Table 30.  Message of 2.4GHz transceiver has been updated to “Compliant to Bluetooth 5.2”, on cover. The following content has been added, updated or corrected:  “9 Ordering Information” and “10 Chip Marking” have been consolidated into one, on page 72.  Maximum MSL parameter updated: “Moisture Sensitivity Level: 3”. PHY6212 Product Specification v1.6 Table of Contents 1 Introduction ................................................................................................................................. 1 2 2.1 2.2 Product Overview ......................................................................................................................... 2 Block Diagram................................................................................................................................ 2 Pin Assignments and Functions ..................................................................................................... 3 2.2.1 PHY6212 (QFN48).......................................................................................................................... 3 2.2.1.1 Pin Assignment ...................................................................................................................... 3 2.2.1.2 Pin Function .......................................................................................................................... 4 2.2.2 PHY6212 (QFN32).......................................................................................................................... 6 2.2.2.1 Pin Assignment ...................................................................................................................... 6 2.2.2.2 Pin Functions ......................................................................................................................... 7 3 3.1 3.2 System Blocks............................................................................................................................... 8 CPU ................................................................................................................................................ 8 Memory ......................................................................................................................................... 8 3.2.1 ROM ............................................................................................................................................ 10 3.2.2 SRAM ........................................................................................................................................... 10 3.2.3 FLASH .......................................................................................................................................... 10 3.2.4 Memory Address Mapping.......................................................................................................... 10 3.3 Boot and Execution Modes ......................................................................................................... 11 3.3.1 Mirror Mode................................................................................................................................ 11 3.3.2 FLASH Mode ................................................................................................................................ 11 3.3.3 Boot loader.................................................................................................................................. 11 3.4 Power, Clock and Reset (PCR) ..................................................................................................... 12 3.5 Power Management (POWER) .................................................................................................... 12 3.6 Low Power Features .................................................................................................................... 14 3.6.1 Operation and Sleep States ......................................................................................................... 14 3.6.1.1 Normal State ....................................................................................................................... 14 3.6.1.2 Clock Gate State .................................................................................................................. 14 3.6.1.3 System Sleep State .............................................................................................................. 14 3.6.1.4 System Off State .................................................................................................................. 14 3.6.2 State Transition ........................................................................................................................... 14 3.6.2.1 Entering Clock Gate State and Wake-up.............................................................................. 14 3.6.2.2 Entering Sleep/off States and Wake-up .............................................................................. 15 3.7 Interrupts..................................................................................................................................... 15 3.8 Clock Management (CLOCK)........................................................................................................ 16 3.9 IOMUX ......................................................................................................................................... 17 3.10 GPIO............................................................................................................................................. 20 3.10.1 ................................................................................................................. 21 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Peripheral Blocks ........................................................................................................................ 23 2.4GHz Radio ............................................................................................................................... 23 Timer/Counters (TIMER) ............................................................................................................. 23 Real Time Counter (RTC) ............................................................................................................. 23 AES-ECB Encryption (ECB) ........................................................................................................... 23 Random Number Generator (RNG) ............................................................................................. 24 Watchdog Timer (WDT)............................................................................................................... 24 SPI (SPI) ........................................................................................................................................ 24 PHY6212 Product Specification v1.6 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 I2C (I2c0, I2c1 Two Independent Instances) ............................................................................... 24 I2S ................................................................................................................................................ 24 UART (UART)................................................................................................................................ 24 DMIC/AMIC Data Path................................................................................................................. 25 4.11.1 Filter Chain Design ...................................................................................................................... 25 4.11.2 Auto Mute Process ...................................................................................................................... 26 4.11.3 Digital Gain Control ..................................................................................................................... 26 4.11.4 Voice Compression ...................................................................................................................... 26 Pulse Width Modulation (PWM) ................................................................................................. 26 Quadrature Decoder (QDEC) ....................................................................................................... 27 Key Scan (KSCAN) ........................................................................................................................ 27 Analog to Digital Converter (ADC) with Programmable Gain Amplifier (PGA) ........................... 28 4.15.1 PGA Path ..................................................................................................................................... 28 4.15.2 ADC Path ..................................................................................................................................... 29 4.15.3 ADC Channel Connectivity ................................................................................................ 32 5 Absolute Maximum Ratings ........................................................................................................ 34 6 Operating Conditions .................................................................................................................. 35 7 7.1 7.2 7.4 Radio Transceiver ....................................................................................................................... 36 Radio Current Consumption ........................................................................................................ 36 Transmitter Specification ............................................................................................................ 36 7.2.1 BLE TX .......................................................................................................................................... 36 Receiver Specification ................................................................................................................. 36 7.3.1 BLE 1Mbps GFSK RX .................................................................................................................... 36 7.3.2 BLE 2Mbps GFSK RX .................................................................................................................... 37 7.3.3 BLE 500Kbps GFSK RX .................................................................................................................. 38 7.3.4 BLE 125Kbps GFSK RX .................................................................................................................. 38 RSSI Specifications ....................................................................................................................... 39 8 Glossary ..................................................................................................................................... 40 9 9.1 9.2 9.3 Ordering information.................................................................................................................. 41 Chip Marking Example................................................................................................................. 41 Chip Marking Rule ....................................................................................................................... 41 Order Code .................................................................................................................................. 42 7.3 10 Package dimensions ................................................................................................................... 43 10.1 QFN32 package dimensions ........................................................................................................ 43 10.2 QFN48 package dimensions ........................................................................................................ 43 11 Sample Application and Layout Guide ......................................................................................... 44 11.1 Sample Application...................................................................................................................... 44 11.2 Layout Guide ............................................................................................................................... 44 11.2.1 Placement ................................................................................................................................... 44 11.2.2 Bypass Capacitor ......................................................................................................................... 45 11.2.3 Layer Definition ........................................................................................................................... 45 11.2.4 Reference clock and trace ........................................................................................................... 45 11.2.5 Power line or plane ..................................................................................................................... 45 11.2.6 Ground Via .................................................................................................................................. 45 PHY6212 Product Specification v1.6 1 Introduction PHY6212 is a System on Chip (SoC) for Bluetooth LE 5.2 applications. PHY6212 has 32-bit ARM® Cortex™M0 CPU with 138KSRAM/Retention SRAM and an ultra-low power, high performance, multi-mode radio. PHY6212 can support BLE with security, application and over-the-air download update. Serial peripheral IO and integrated application IP enables customer product to be built with minimum bill-of-material (BOM) cost. 1 / 45 PHY6212 Product Specification v1.6 Product Overview Block Diagram RNG 12 QDEC 11 DMIC 10 I2S 9 GPIO 8 SPI1 7 PCR 0 IOMUX 3 AON (3.3v) COM APB 16MHz Cr yst al Oscillat or PAD 6 5 32KHz RC Oscillat or 6x LDO Buck DC-DC Fast Boost DC-DC TIMER 1 WDT 2 COM 3 Keyscan 4 PWM 14 RTC Pcrm APB SPI0 32MHz RC Oscillat or 8x 12-bit ADC PM I2C0/1 32KHz Cr yst al Oscillat or APB 2 2.1 AHB AHB M4 M5 M6 M7 S5 M9 Bus Matrix M8 M14 DMA(2chnl) M0 M11 M12 M13 AHB S3 AHB S4 SPI Flash Controller Modem AES ADDC Voice NOR FLASH (512KB) RF Transceiver Figure 1: PHY6212 block diagram 2 / 45 AHB2APB1 AHB M3 ARM® Cor t ex®-M0 AHB M2 SRAM4 (2KB) AHB AHB M1 SRAM3 (8KB) SRAM2 (64KB) AHB AHB M10 SRAM1 (32KB) AHB AHB SRAM0 (32KB) AHB AHB2APB0 ROM1 (120KB) AHB 1 ROM0 (8KB) AHB AP0_TIMER AHB2APB2 AHB 2 AHB 4 AHB UART AP0_WDT PHY6212 Product Specification v1.6 2.2 Pin Assignments and Functions This section describes the pin assignment and the pin functions for the different package types. 2.2.1 PHY6212 (QFN48) 2.2.1.1 Pin Assignment Figure 2: Pin assignment - PHY6212 QFN48 package 3 / 45 PHY6212 Product Specification v1.6 2.2.1.2 Pin Function Pin Pin name Description 1 P34 all functions configurable 2 P00 all functions configurable/ JTAG_TDO 3 P01 all functions configurable/ JTAG_TDI 4 P02 all functions configurable/JTAG_TMS 5 P03 all functions configurable/JTAG_TCK 6 P04 all functions configurable 7 P05 all functions configurable 8 P06 all functions configurable 9 TM Test_Mode 10 P09 all functions configurable 11 P10 all functions configurable 12 DVDD3 3V power supply for digital IO, DCDC, Charge pump 13 DCDC_SW Buck dcdc output 14 PVSS Buck dcdc and charge pump power vss 15 cp_out charge pump output 16 DVSS digital vss 17 VDDDEC 1.2V VDD_CORE, digital LDO output 18 DVDD_LDO digital LDO input 19 P11 all functions configurable/AIO 20 P12 all functions configurable/AIO 21 P13 all functions configurable/AIO 22 P14 all functions configurable/AIO 23 P15 all functions configurable/AIO 24 AVDD3 3V power supply for analog IO, bg, rcosc, etc 25 XC1 16M crystal input 26 XC2 16M crystal output 27 P16 all functions configurable/AIO/32K crystal input 28 P17 all functions configurable/AIO/32k crystal output *Note: Not support interrupt and ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function 4 / 45 PHY6212 Product Specification v1.6 Pin Pin name Description 29 P18 all functions configurable/AIO/PGA differential positive input 30 P20 all functions configurable/AIO/Micphone bias output 31 P19 all functions configurable/AIO/PGA differential negative input 32 RST_N reset pin 33 RF RF antenna 34 LNA_VDD LNA_VDD 35 TRX_VDD TRX_VDD 36 P21 all functions configurable 37 P22 all functions configurable 38 P23 all functions configurable 39 P24 all functions configurable/test_mode_select[0] 40 P25 all functions configurable/test_mode_select[1] 41 P26 all functions configurable 42 P27 all functions configurable 43 P28 all functions configurable 44 P29 all functions configurable 45 P30 all functions configurable 46 P31 all functions configurable 47 P32 all functions configurable 48 P33 all functions configurable *Note: Not support interrupt function *Note: Not support interrupt function *Note: Not support interrupt function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function *Note: Not support interrupt function and ADC function Table 1: Pin functions PHY6212 QFN48 package 5 / 45 PHY6212 Product Specification v1.6 2.2.2 PHY6212 (QFN32) 2.2.2.1 Pin Assignment Figure 3: Pin assignment - PHY6212 QFN32 package 6 / 45 PHY6212 Product Specification v1.6 2.2.2.2 Pin Functions Pin Pin name Description 1 P34 all functions configurable 2 P00 all functions configurable/ JTAG_TDO 3 P01 all functions configurable/ JTAG_TDI 4 P02 all functions configurable/ JTAG_TMS 5 P03 all functions configurable/ JTAG_TCK 6 TM 7 P09 Test_Mode all functions configurable 8 P10 all functions configurable 9 10 11 12 13 14 15 16 17 18 19 20 DVDD3 DCDC_SW cp_out VDDDEC DVDD_LDO P14 P15 AVDD3 XC1 XC2 P16 P17 21 P18 3V power supply for digital IO, DCDC, Charge pump Buck dcdc output charge pump output 1.2V VDD_CORE, digital LDO output digital LDO input all functions configurable/AIO all functions configurable/AIO 3V power supply for analog IO, bg, rcosc, etc 16M crystal input 16M crystal output all functions configurable/AIO/32K crystal input all functions configurable/AIO/32k crystal output all functions configurable 22 23 24 25 26 P20 RST_N RF LNA_VDD TRX_VDD 27 P23 all functions configurable/AIO/Micphone bias output reset pin RF antenna LNA_VDD TRX_VDD all functions configurable 28 P24 all functions configurable/test_mode_select[0] 29 P25 all functions configurable/test_mode_select[1] 30 P31 all functions configurable 31 P32 all functions configurable 32 P33 all functions configurable *Note: Not support interrupt and ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support ADC function *Note: Not support interrupt function *Note: Not support interrupt and ADC function *Note: Not support interrupt and ADC function *Note: Not support interrupt and ADC function *Note: Not support interrupt and ADC function *Note: Not support interrupt and ADC function *Note: Not support interrupt and ADC function Table 2: Pin functions PHY6212 QFN32 package 7 / 45 PHY6212 Product Specification v1.6 3 System Blocks The system block diagram of PHY6212 is shown in Figure 1. 3.1 CPU The PHY6212 has an ARM Cortex-M0 CPU. The CPU, memories, and all peripherals are connected by AMBA bus fabrics. The ARM® Cortex™-M0 CPU has a 16-bit instruction set with 32-bit extensions (Thumb-2® technology) that delivers high-density code with a small-memory-footprint. By using a single-cycle 32-bit multiplier, a 3stage pipeline and a Nested Vector Interrupt Controller (NVIC), the ARM Cortex™-M0 CPU makes program execution simple and highly efficient. The main features of ARM® Cortex™-M0 CPU are listed below.             Up to 96Mhz ARM Cortex™-M0 processor core. o Low gate count and high energy efficient. o ARMv6M architecture, Thumb ISA but no ARM ISA. o No cache and no TCM. o Up to 32 interrupts embedded NVIC. o SysTick timer. o Sleep/deep sleep mode. o Support low power WFI and WFE. Tight integration of system peripherals reduces area and development costs Thumb instruction set combines high code density with 32-bit performance power control optimization of system components Integrated sleep modes for low power consumption Fast code execution permits slower processor clock or increases sleep mode time Hardware multiplier Deterministic, high-performance interrupt handling for time-critical applications Serial Wire Debug reduces the number of pins required for debugging. APB interface to/from BLE modem. Dynamic and static clock gating to save power. No TRACE. Some of these features are shared with the AP subsystem. 3.2 Memory PHY6212 has total 128KB ROM, 138KB SRAM and up to 512KB FLASH. The physical address space of these memories is shown in Figure4. 8 / 45 PHY6212 Product Specification v1.6 Figure 4: PHY6212 memory space 9 / 45 PHY6212 Product Specification v1.6 3.2.1 ROM PHY6212 has 2 ROMs. SIZE ROM0 8KB ROM1 120KB 3.2.2 CONTENT Reserved Boot ROM for M0. Protocol stack. Common peripheral drivers. Table 3: List of ROMs SRAM PHY6212 has 5 SRAM blocks. All 5 SRAM blocks have retention capability. which can be configured individually. All SRAM blocks can be used to store program or data. SIZE SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 CONTENT 32KB 32KB 64KB 8KB 2KB Table 4: List of SRAMs 3.2.3 FLASH PHY6212 has FLASH to provide non-volatile program and data storage. The size of the FLASH can be 256KB or 2MB. PHY6212 supports 2-wire reading. 3.2.4 Memory Address Mapping Name Size(KB) ROM0 ROM1 RAM0 RAM1 RAM2 RAM3 RAM4 FLASH 8 120 32 32 64 8 2 512 Master M0 M0 M0 M0 M0 M0 M0 M0 Physical Address CM4 Alias 1000_0000~1000_1FFF 0x0 1000_2000~1001_FFFF 1FFF_0000~1FFF_7FFF 1FFF_8000~1FFF_FFFF 2000_0000~2000_FFFF 2001_0000~2001_1FFF 2001_2000~2001_27FF 1100_0000~1107_FFFF 6000_0000~6007_FFFF Table 5: Memory address mapping 10 / 45 M0 Remap 0 1 2 0x0 0x0 0x0 PHY6212 Product Specification v1.6 3.3 Boot and Execution Modes During the boot, the ROM1 is aliased to 0x0 address. The M0 starts to execute the program from the ROM1. Figure 5: PHY6212 boot mode 3.3.1 Mirror Mode The mirror mode is not tied to the chip variations. Any chip variation can use mirror mode to execute program. In the mirror mode, the program is copied from the FLASH to the SRAM, then is executed in the SRAM. For the M0 processor, one of the SRAM blocks must be aliased to 0x0 address. 3.3.2 FLASH Mode The FLASH mode is not tied to the chip variations. Any chip variation can use FLASH mode to execute program. In the FLASH mode, the program is executed in the FLASH. For the M0 processor, the FLASH must be aliased to 0x0 address. 3.3.3 Boot loader The boot loader in the ROM has the basic structure as shown below. The content in the FLASH should be specifically defined to allow boot loader to identify whether the FLASH content is valid, as shown in the example below. If the FLASH is valid, the ROM boot loader will put the chip in the normal mode and start normal program execution. If the FLASH is not valid, the boot loader will enter FLASH programming mode. 11 / 45 PHY6212 Product Specification v1.6 Address 0 4 8 C START Variable PRODUCT_MODE CODE_BASE CODE_LEN BOOT_MODE Flash valid? Enable SPIF Content Identify the chip mode The base address of the code The length of the code Identify mirror or FLASH mode Table 6: Flash content example Receive RAMRUN from UART or SPI N Jump to RAMRUN code Receive and Write data to flash Flash write ok? END NORMAL FLOW Figure 6: Bootloader flow 3.4 Power, Clock and Reset (PCR) i_wdt_rst_n & en i_sys_srst_n i_cpu_lockup & en i_hresetn & efuse_ctrl_over rst_expd & & rst_sync & i_cpu_srst_n i_cpu_req_rst & rst_expd clk_gen_rstn cpu_por_rstn cpu_rst0_n rst_sync core_sys_n & cpu_rst1_n rst_sync cpu_hbus_rstn sys_pbus_rstn rst_sync sys_hbus_rstn rst_sync hbus_dma_rst_n & rst_sync hbus_aes_rst_n & rst_sync & rst_sync rst_sync rst_sync rst_sync rst_sync rst_sync rst_sync hbus_spif_rst_n pbus_timer_rst_n timer_rst_n pbus_wdt_rst_n wdt_rst_n pbus_uart_rst_n pbus_com_rst_n & rst_sync pbus_spi0_rst_n & rst_sync pbus_spi1_rst_n & rst_sync pbus_i2c0_rst_n & & rst_sync rst_sync rst_sync rst_sync rst_sync & rst_sync pbus_i2c1_rst_n pbus_gpio_rst_n gpio_rst_n pbus_i2s_rst_n i2sr_rst_n pbus_qdec_rst_n & rst_sync pbus_rng_rst_n & rst_sync hbus_adcc_rst_n & rst_sync pbus_pwm_rst_n rst_sync rst_sync & rst_sync rst_sync & rst_sync rst_sync sys_pbus_rstn sys_hbus_rstn pbus_timer_rst_n timer_rst_n pbus_wdt_rst_n wdt_rst_n & rst_sync pbus_com_rst_n & rst_sync hbus_bb_rst_n rst_sync rst_sync bb_rst_n rf_rst_n & & & & & i_wdt_rst_n i_sys_srst_n i_cpu_lockup rst_exp d & & rst_sync i_cpu_srst_n i_cpu_req_rst & & rst_exp d clk_gen_rstn cpu_rst0_n rst_sync cpu_por_rstn core_sys_n & cpu_rst1_n rst_sync cpu_hbus_rstn Figure 7: PHY6212 power, clock and reset 3.5 Power Management (POWER) The power management system is highly flexible with functional blocks such as the CPU, radio transceiver, and peripherals saving separate power state control in addition to the System Sleep mode 12 / 45 PHY6212 Product Specification v1.6 and OFF modes. When in System Normal mode, all functional blocks will independently be turned on depending on needed application functionality. Microphone Bias PAD POR BATT 1.8~3.6v AON/PM CTRL 1 RC32M 2 RC32K 3 XT32K 4 Bandga p 5 SRAM0 (32K) SRAM1 (32K) SRAM2 (64K) SRAM3 (8K) SRAM4 (2K) 20 21 22 23 24 LC-LDO 1.2/0.6v(setting) 6 DC/DC 8 Charge pump 9 CMP 10 RTC 1.35v 7 1.2v DIGLDO RF-LDO 1.2v 1.2v Digital Core RF AnaLDO 1.2v 16M XTAL PGA PLL RNS ADC Figure 8: Power system The following diagram is Normal, Sleep and Off mode. Switches are optional depending on user’s request. Switch 1RC32M 2RC32K 3XT32K 4bandgap Normal On On On On Sleep Off Optional Optional Off 13 / 45 Off Off Off Off Off TEMP SENSOR PHY6212 Product Specification v1.6 Switch 5LC-LDO 6DC/DC 7DIG-LDO 8charge pump 9CMP 10RTC 20SRAM-32K 21SRAM-32K 22SRAM-64K 23SRAM-8K 24SRAM-2K 3.6 3.6.1 3.6.1.1 3.6.1.2 Normal Sleep On on On Off On Off On Off On Optional On Optional 1.2v 0.6v 1.2v 0.6v 1.2v 0.6v 1.2v 0.6v 1.2v 0.6v Table 7: Flash Switches of different power modes Off Off Off Off Off Off Off 0 0 0 0 0 Low Power Features Operation and Sleep States Normal State Clock Gate State The CPU executes WFI/WFE to enter clock gate state. After wake-up from clock-gate state, the CPU continues to execute the program from where it stopped. The wake-up sources includes interrupts and events. The wake-up sources are configured by the software according to applications. 3.6.1.3 System Sleep State The wake-up sources include:  IO  RTC  RESET  UVLO reset 3.6.1.4 System Off State The wake-up sources include:  IOs  RESET  UVLO reset 3.6.2 State Transition 3.6.2.1 Entering Clock Gate State and Wake-up CPU executes WFI/WFE. 14 / 45 PHY6212 Product Specification v1.6 3.6.2.2 Entering Sleep/off States and Wake-up The PM registers identify whether the CPU is in mirror mode or FLASH mode before sleep or off, and record the remap and vectors. The CPU configures the corresponding PM registers to put the chip into sleep or off mode. After wake-up, the chip enters boot mode to execute boot code in the ROM. The ROM code checks the mode before sleep/off and the remap information, perform corresponding configurations, and starts to execute the program. 3.7 Interrupts Interrupt Name Reserved Reserved cp_timer_irq cp_wdt_irq bb_irq kscan_irq rtc_irq Reserved Reserved timer_irq wdt_irq uart_irq i2c0_irq i2c1_irq spi0_irq spi1_irq gpio_irq i2s_irq spif_irq dmac_intr dmac_inttc dmac_interr fpidc fpdzc fpioc fpufc fpofc fpixc aes_irq adcc_irq qdec_irq rng_irq M0 Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 8: Interrupts 15 / 45 PHY6212 Product Specification v1.6 3.8 Clock Management (CLOCK) Figure 9: Clock management There are two crystal clock sources: 16MHz crystal oscillator (XT16M) and 32.768kHz crystal oscillator (XT32k), of which the 32.768k crystal oscillator is optional. There are also two on chip RC oscillators: 32MHz RC oscillator (RC32M) and 32kHz RC oscillator (RC32k), both of which can be calibrated with respect to 16MHz crystal oscillator. If 32.768kHz crystal is not installed, RC32k oscillator would be periodically calibrated and used for RTC. At initial power up or wake up before XT16M oscillator starts up, RC32M is used as the main clock. An on-chip DLL generates higher frequency clocks such as 32/48/64/96MHz from the XT16M clock source. 16 / 45 PHY6212 Product Specification v1.6 div25 xtal_16m rc_32m dll_32m dll_48m dll_64m dll_96m 5to1 mux clk_1p28m to iomux 2to1 mux div2 o_hclk pclk_l 16M pm_clk hclk_sel divN div4 rc32k xt32k adc_clk 320K 160K 80K div div16 PCRM m4_enable | combo fclk_cpu G GATEHCLK cpu_hready G hclk_cpu G software_gate hclk_dma G hclk_aes G hclk_spif G hclk_adcc G div rng_clk G timer_clk G timer_clk_g gpio_clk G gpio_clk_g i2s_clk_mst 1.41M i2s_clk_slv 2to1 mux hclk_bus rng_clk_g G gate& div pclk_bus G G G G G i2s_clk_g G G G 2to1 mux G G G G G G G m0_enable | r_enable_by_m4 GATEHCLK G pclk_timer pclk_wdt clk_wdt pclk_com pclk_uart pclk_spi0 pclk_spi1 pclk_i2c0 pclk_i2c1 pclk_i2s pclk_qdec pclk_rng pclk_pwm pclk_gpio fclk_cpu hclk_cpu hclk_bus hclk_bb G gate& div i_rf_clk i_bb_clk pclk_bus G pclk_timer G G G G pclk_wdt G G clk_wdt pclk_com pclk_ks rf_clk bb_clk Figure 10: Clock structure diagram 3.9 IOMUX The IOMUX provides a flexible I/O configuration, as the ports of most of the peripherals can be configured and mapped to any of the physical I/O pads (I/O at die boundary). These peripheral modules include I2C 01, I2S, UART, PWM 0-5, SPI 0-1, Quadrature Decoder etc. However for other specific purpose peripherals, their IOs mappings are fixed when they are enabled. These specific purpose peripherals include JTAG, analog_ios, GPIOs and key scan. Figure 11 below shows the IOMUX functional diagram. 17 / 45 PHY6212 Product Specification v1.6 APB_bus CFG_reg IOMUX GPIO MUX P00~P34 UART SPI peripherals Figure 11: IOMUX structure diagram There are 34 configurable pads which are from P00 to P07 and from P09 to P34. P08 pad is assigned for TM pin which is a test mode pin. The table blow shows the mapping of the peripheral IOs that can be mapped through IOMUX. These include I2C 0-1, I2S, UART, PWM 0-5, SPI 0-1, Quadrature Decoder, 1.28MHz clock and dmic_out. Signal Name iic0_scl iic0_sda iic1_scl iic1_sda i2s_sck i2s_ws i2s_sdo0 i2s_sdo1 i2s_sdo2 i2s_sdo3 i2s_sdi0 i2s_sdi1 i2s_sdi2 i2s_sdi3 uart_tx uart_rx pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 spi_0_sck spi_0_ssn IO B B B B B B O O O O I I I I O I O O O O O O B B FULLMUX 0 1 2 3 4 5 6 35 36 37 7 38 39 40 8 9 10 11 12 13 14 15 16 17 18 / 45 PHY6212 Product Specification v1.6 Signal Name spi_0_tx spi_0_rx spi_1_sck spi_1_ssn spi_1_tx spi_1_rx chax chbx chix chay chby chiy chaz chbz chiz clk_1p28m adcc_dmic_out IO FULLMUX O 18 I 19 B 20 B 21 O 22 I 23 I 24 I 25 I 26 I 27 I 28 I 29 I 30 I 31 I 32 O 33 I 34 Table 9: Peripheral IO mapped through IOMUX On the other hand, there are also special purpose peripherals, whose IOs are fixed to certain physical pads, when these peripheral functions are enabled. These special purpose peripherals include: JTAG, analog I/Os (ADC inputs), GPIO, and key scan. When they are enabled, their IOs are mapped to physical pads according to the following table (by default JTAG is enabled). QFN48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QFN32 √ √ √ √ √ √ √ √ √ √ √ √ GPIO_P00 GPIO_P01 GPIO_P02 GPIO_P03 GPIO_P04 GPIO_P05 GPIO_P06 GPIO_P07 TEST_MODE GPIO_P09 GPIO_P10 GPIO_P11 GPIO_P12 GPIO_P13 GPIO_P14 GPIO_P15 GPIO_P16 GPIO_P17 GPIO_P18 GPIO_P19 jtag_dout jtag_din jtag_tm jtag_clk GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO XTALI(ANA) XTALO(ANA) GPIO GPIO 19 / 45 Name mk_in[0] mk_out[0] mk_in[1] mk_out[1] mk_out[9] mk_in[10] mk_out[10] mk_in[11] GPIO GPIO GPIO GPIO analog_io[0] analog_io[1] analog_io[2] analog_io[3] analog_io[4] GPIO GPIO analog_io[7] analog_io[8] mk_out[4] mk_in[4] mk_out[11] mk_in[12] mk_out[12] mk_out[2] mk_in[2] mk_out[16] mk_out[17] mk_in[5] mk_in[13] PHY6212 Product Specification v1.6 QFN48 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 QFN32 √ GPIO_P20 GPIO analog_io[9] GPIO_P21 GPIO GPIO_P22 GPIO √ GPIO_P23 GPIO √ GPIO_P24 GPIO √ GPIO_P25 GPIO GPIO_P26 GPIO GPIO_P27 GPIO GPIO_P28 GPIO GPIO_P29 GPIO GPIO_P30 GPIO √ GPIO_P31 spi_t_ssn GPIO √ GPIO_P32 spi_t_rx GPIO √ GPIO_P33 spi_t_tx GPIO √ GPIO_P34 spi_t_sck GPIO Table 10: Peripheral IO mapped through IOMUX (special purpose) Name mk_out[5] mk_out[13] mk_in[14] mk_in[6] mk_out[3] mk_in[3] mk_out[14] mk_in[9] mk_out[8] mk_in[15] mk_out[15] mk_out[7] mk_in[7] mk_out[6] mk_in[8] In the IOMUX table above, the first column is the IO pad mapping in default mode, when no IOMUX function is selected and no special purpose peripherals such as analog IO, GPIO, key scan, are enabled. In this mode, pin are used for JTAG. When analog IOs are enabled, pins, are connected to internal analog IOs. More specifically, analog_io are connected to ADC inputs, analog_io are connected to PGA inputs. In JTAG mode, data output for JTAG test mode is mapped to P00; data input for JTAG test mode is mapped to P01; mode control input for JTAG test mode is mapped to P02; clock input for JTAG test mode is mapped to P03. 3.10 GPIO The General Purpose I/Os are a type of peripheral that can be mapped to physical I/O pads and programmed by software. The flexible GPIO are organized as two PORTs. Among them, PortA has bidirection 18 bit lines, e.g., GPIO_PORTA[17:0], while PortB has 17 bi-directional bit lines, e.g., PIO_PORTB[16:0]. With default setting, physical pads: P00-P17 are connected to PortA; Pads P18-34 are connected to PortB, when all GPIOs are enabled, as described in the IOMUX table in IOMUX section. All PortA and PortB pins can be configured as bi-directional serial interface, by selecting as input or output direction, and their corresponding data can be either read from or written to registers. All PortA and PortB pins support wake-up, but only 18 PortA pins support interrupt. Also only PortA pins support debounce function. Each GPIO pins can be pulled up to AVDD33 or pulled down to ground by adding pull up or pull down resistors to have default functions/states. For more detailed info, please refer to “PHY62xx GPIO Application Notes”, in software SDK document folder. 20 / 45 PHY6212 Product Specification v1.6 # QFN48 QFN32 Default MODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GPIO_P00 GPIO_P01 GPIO_P02 GPIO_P03 GPIO_P04 GPIO_P05 GPIO_P06 GPIO_P07 TEST_MODE GPIO_P09 GPIO_P10 GPIO_P11 GPIO_P12 GPIO_P13 GPIO_P14 GPIO_P15 GPIO_P16 GPIO_P17 GPIO_P18 GPIO_P19 GPIO_P20 GPIO_P21 GPIO_P22 GPIO_P23 GPIO_P24 GPIO_P25 GPIO_P26 GPIO_P27 GPIO_P28 GPIO_P29 GPIO_P30 GPIO_P31 GPIO_P32 GPIO_P33 GPIO_P34 √ √ √ √ jtag_dout jtag_din jtag_tm jtag_clk GPIO GPIO GPIO GPIO √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Default IN_OUT OUT IN IN IN IN IN IN IN IRQ Wakeup √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ GPIO √ IN GPIO √ IN GPIO √ IN GPIO √ IN GPIO √ IN GPIO √ IN GPIO √ IN XTALI(ANA) √ ANA XTALO(ANA) √ ANA GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN GPIO IN phyplus_spi_t_ssn IN phyplus_spi_t_rx IN phyplus_spi_t_tx OUT phyplus_spi_t_sck IN Table 11: PHY62xx GPIO Application Notes √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ ANA_IO ADC_CH1N_P11 ADC_CH1P_P12 ADC_CH2N_P13 ADC_CH2P_P14 ADC_CH3N_P15 ADC_CH3P_P20 3.10.1 TA=25℃, VDD=3 V PARAMETER Logic-0 input voltage Logic-1 input voltage Logic-0 input current TEST CONDITIONS Min. Input equals 0 V 2.4 -50 21 / 45 TYP Max. 0.5 50 Unit V V nA PHY6212 Product Specification v1.6 PARAMETER Logic-1 input current Logic-0 output voltage, 10-mA pins Logic-1 output voltage, 10-mA pins TEST CONDITIONS Min. Input equals VDD -50 Output load 10 mA Output load 10 mA 2.5 Table 12: DC Characteristics 22 / 45 TYP Max. 50 0.5 Unit nA V V PHY6212 Product Specification v1.6 4 4.1 Peripheral Blocks 2.4GHz Radio The 2.4 GHz RF transceiver is designed to operate in the worldwide ISM frequency band at 2.4 to 2.4835 GHz. Radio modulation modes and configurable packet structure make the transceiver interoperable with Bluetooth LE 5.2 protocol implementations.  General modulation format  FSK (configurable modulation index) with configurable Gaussian Filter Shaping  OQPSK with half-sine shaping  On-air data rates  125kbps/250kbps/500kbps/1Mbps/2Mbps  Transmitter with programmable output power of -20dBm to +10dBm, in 3dB steps  RSSI function (1 dB resolution, ± 2 dB accuracy)  Receiver sensitivity  -103dBm@125Kbps GFSK  -98dBm@500Kbps GFSK  -97dBm@1Mbps BLE  -94dBm@2Mbps BLE  Embedded RF balun  Integrated frac-N synthesizer with phase modulation 4.2 Timer/Counters (TIMER) The implementation can include a 24-bit SysTick system timer, that extends the functionality of both the processor and the NVIC. When present, the NVIC part of the extension provides:  A 24-bit system timer (SysTick)  Additional configurable priority SysTick interrupt.  See the ARMv7-M ARM for more information. General purpose timers are included in the design. With the input clock running at 4Mhz. 4.3 Real Time Counter (RTC) The Real Time Counter (RTC) module provides a generic, low power timer on the low-frequency clock source (LFCLK). The RTC features a 24 bit COUNTER, 12 bit (1/X) prescaler, capture/compare registers, and a tick event generator for low power, tickless RTOS implementation. 4.4 AES-ECB Encryption (ECB) The ECB encryption block supports 128 bit AES encryption. It can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. 23 / 45 PHY6212 Product Specification v1.6 4.5 Random Number Generator (RNG) The Random Number Generator (RNG) generates true non-deterministic random numbers based on internal thermal noise. These random numbers are suitable for cryptographic purposes. The RNG does not require a seed value. 4.6 Watchdog Timer (WDT) A count down watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up. The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. 4.7 SPI (SPI) The SPI interface supports 3 serial synchronous protocols which are SPI, SSP and Microwire serial protocols. SPI wrapper contains one SPI master and one SPI slave. They are logically exclusive. Only one block is alive at a time. The operation mode for master mode and slave mode is controlled by PERI_MASTER_SELECT Register in COM block. bit Reset value Definition 1 0 SPI1 is master mode when set 0 0 SPI0 is master mode when set Table 13: PERI_MASTER_SELECT Register bit definition (base address = 0x4000_302C) 4.8 I2C (I2c0, I2c1 Two Independent Instances) This I2C block support 100Khz, and 400Khz modes. It also supports 7-bit address and 10-bit address. It has built-in configurable spike suppression function for both lines. 4.9 I2S I2S wrapper contains one I2S master and one I2S slave. They are logically exclusive. Only one block is alive at a time. The operation mode for master mode and slave mode is controlled by PERI_MASTER_SELECT Register in COM block. bit Reset value Definition 3 0 I2S1 is master mode when set 2 0 I2S0 is master mode when set Table 14: PERI_MASTER_SELECT Register bit definition (base address = 0x4002_302C) 4.10 UART (UART) The Universal Asynchronous Receiver/Transmitter offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in HW up to 1Mbps baud. Parity checking and generation for the 9th data bit are supported. The GPIOs used for each UART interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pin out and enables efficient use of 24 / 45 PHY6212 Product Specification v1.6 board space and signal routing. 4.11 DMIC/AMIC Data Path The voice in interface supports one analog MIC (SAR-ADC) and two digital MIC (L+R), different output sample rate (64KHz, 32KHz, 16KHz and 8KHz), and different voice compress algorithm. For the Digital MIC, PDM signal is sampled at 1.28MHz(4x320KHz). L channel is sampled at raising edge, R channel is sampled at falling edge. For PCM-LOG and CVDS, output data rate is 64Kbps (8KHz x 8bit). Figure 12: Block Diagram of Voice In Interface 4.11.1 Filter Chain Design For D-MIC input, PDM Decimation (CIC) will convert the 1-bit PDM signal to 12 bit PCM signal. And the sample rate will be converted from 1.28MHz to 320KHz. The output data of the PDM Decimation will be connected to the Digital Filter chain. For the A-MIC input, SAR-ADC will convert the signal to 12bit 320KHz digital samples. The Digital Filter chain will process the data same as the D-MIC path. The Output sample rate of the Digital filter chain is programmable. 64KHz, 32KHz, 16KHz, 8KHz. The maximum value of the sample’s bit-width is 16bit. Figure 13: Digital Filter Chain 25 / 45 PHY6212 Product Specification v1.6 4.11.2 Auto Mute Process Signal Level Estimate will check the input signal level with configurable window size. Mute threshold can be updated according to the signal level estimation or being configured by the register. There are two thresholds, one for MUTE_ON, another for MUTE_OFF. Gain step of MUTE_ON and MUTE_OFF can be configured individually. Figure 14: Auto Mute Process 4.11.3 Digital Gain Control Digital gain is implemented by one Look up table. The gain error has been controled within 0.05dB. 4.11.4 Voice Compression PCM-LOG support u-Law and a-Law. According to the ITU-G711 standard. The input data is 13~14bit @ 8KHz. The output data is 8bit @ 8KHz, 64Kbps. Also, it support 64Kbps CVSD according to the BT standard. Its Input is 16bit @64KHz, and its output is 1bit @ 64KHz. PCM-Linear is for the raw data without compression. 4.12 Pulse Width Modulation (PWM) Phy62xx supports 6 channels of Pulse Width Modulation (PWM) outputs. PWM outputs generate waveforms with variable duty cycle or pulse width programmed by registers. And each of the 6 PWM outputs can be individually programmed. Their duty cycles are controlled by programming individual counters associated with each channel. The master clock is 16MHz. For each PWM outputs, first there is a prescaler (pre-divider) with division ratio of 2 to 128 (only 2^N division ratios are supported), followed by another 16bit counter with programmable max count, denoted as top_count. When the 16bit counter counts from 0 to top_count, it resets back to 0. So the frequency of the PWM is given by: Freq_PWM = 16MHz / (N_prescaler * N_top_count); A threshold counter number can be programmed, when the 16bit counter reaches the threshold, PWM output toggles. So the duty cycle is: Duty_cycle_PWM = N_threshold/N_top_count; The polarity of the PWM can also be programmed, which indicates output 1 or 0 when counter is below/above the threshold. A PWM waveform vs counter values are illustrated in the following Figure 13, where the polarity is positive. Also in this case the counter ramps up and then resets, we call it “up mode”. 26 / 45 PHY6212 Product Specification v1.6 There is also a “up and down mode”, where the counter ramps up to count_top and then ramps down, instead of reset. As discussed above, the key register bits for one PWM channel are: 16bit top_count, 16bit threshold count, 3bit prescaler count, PWM polarity, PWM mode (up or up/down), PWM enable, and PWM load enable (load new settings). All 6 PWM channels can be individually programmed by registers with addresses from 0x4000_E004 to 0x4000_E044. In addition, one should enable registers 0x4000_E000 to allow all PWM channels can be programmed. For details please refer to documents of PHY62xx register tables. top value compare value pwm output Figure 15: PWM operation 4.13 Quadrature Decoder (QDEC) The quadrature decoder provides buffered decoding of quadrature-encoded sensor signals with input debounce filters. It is suitable for mechanical and optical sensors. The sample period and accumulation are configurable to match application requirements. The quadrature decoder has three-axis capability and index channel support. It can be programmed as 4x/2x/1x count mode. 4.14 Key Scan (KSCAN) Keyscan supports key matrix with upto 16 rows by 18 columns. Each individual rows or columns can be enabled or disabled through register settings. GPIO pins can be configured to be used for key scan. A few key scan Parameters can be set through registers, including polarity (low or high indicating key pressed); support multi-key-press or only single-key-press; de-bounce time (the time duration a key press is deemed valid) from 0 to 128mS with 255us step. A valid key press can trigger an interrupt when keyscan interrupt is enabled. After a keyscan interrupt 27 / 45 PHY6212 Product Specification v1.6 is serviced, writing 1 to the interrupt state register bit can clear the state bit. The keyscan has a manual mode and an auto mode. For manual mode, when a keyscan interrupt is received, it is upo the MCU/software to scan the keyscan output pins and check the input pins, to determine which keys have been pressed. Manual mode is relatively slow and need CPU to process. On the contrary, in automode keyscan will automatically scan the output/input pins, and store the row/column info corresponding to the key pressed into read only registers, then trigger an interrupt for software to retrieve key press information. 4.15 Analog to Digital Converter (ADC) with Programmable Gain Amplifier (PGA) The 12bit SAR ADC has total 10 inputs. Among them, there are two for PGA inputs, and two differential inputs for the on-chip temperature sensor. The other six inputs can be programmed to 3 pair differential inputs or six single-ended inputs. There is a manual mode with which the ADC can be configured to convert a specific input in single-ended or differential and with a specific ADC clock rate. There is also an auto sweep mode, namely all enabled input channels can be swept automatically in order by the ADC and the converted data will be stored at corresponding memory locations. PGA_inp PGA_inm PGA_inp PGA PGA_inm adc_out ADC ch_m ch_p Figure 16: ADC 4.15.1 PGA Path The PGA provides 42dB gain range from 0dB to 42dB in 3dB steps. 28 / 45 adc_clkout PHY6212 Product Specification v1.6 Stage 1 Stage 2 PGA_gain1 PGA_gain2 Buffer PGA_inp PGA_inm PGA_SEenable VCM Figure 17: PGA path pga_gain1< 1> 0 0 1 pga_gain1 0 1 0 Stage1 gain (dB) 0 12 24 pga_gain2 pga_gain2 pga_gain2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 Table 15: PGA gain 0 1 0 1 0 1 0 Stage2 gain(dB) 0 3 6 9 12 15 18 Set PGA_SEenable to “1”, PGA will be set to Single-ended mode by pulling the PGA into its Commonmode voltage. 4.15.2 ADC Path By default the ADC is configured in manual mode. In this mode, the ADC clock rate can be configured to 80k/160k/320k sample per second. Select the pair of inputs and configure it to differential or singled-ended (positive or negative). By default it is differential. After enabling, the ADC will take samples with the configured clock rate and store the data to a channel dependent memory location. For each channel a memory size of 128Byte is allocated, when it is full an interrupt bit will be flagged. Each sample of 12bits takes 2 Byte memory space. Register Description 0x4000_F07C [4] adc_ctrl_override [3] adc_tconv_sel [2:1] [0] 0x4000_F048 adc_clk_sel max_rate_256k_320k [11] adc12b_semode_enm Set manual mode: 1: manual, 0: auto. Default 1 For auto mode only, adc conversion time sel: 0: 1.56us, 1: 2.34us For manual mode only, clksel: 00: 80k, 01: 160k, 10: 320k For auto mode only, max rate base: 0, 256k, 1, 320k Register Description For manual mode only: 12 bit ADC signle-ended mode negative side enable. Bit Bit cannot both be 1; 1: Enable single-ended mode 0: Differential mode 29 / 45 PHY6212 Product Specification v1.6 [8] Adc12b_semode_epm [7:5] Channel configure [3] ADC enable Memory start/end addresses 4005_0400 – 4005_047F 4005_0480 – 4005_04FF 4005_0500 – 4005_057F 4005_0580 – 4005_05FF 4005_0600 – 4005_067F 4005_0680 – 4005_06FF 4005_0700 – 4005_077F 4005_0780 – 4005_07FF ADC interrupt status 0x4005_003C [7] [6] [5] [4] [3] [2] [1] [0] 0x4005_0038 ADC interrupt write clear input C, negative Input C, positive or differential Input B, negative Input B, positive or differential Input A, negative Input A, positive or differential Temperature sensing, differential PGA inputs, differential Register Description ADC interrupt write clear input C, negative, write 1 to clear Input C, positive or differential, write 1 to clear Input B, negative, write 1 to clear Input B, positive or differential, write 1 to clear Input A, negative, write 1 to clear Input A, positive or differential, write 1 to clear Register Description [7] [6] [5] [4] [3] [2] 0x4005_0038 [1] [0] For manual mode only: 12 bit ADC signle-ended mode positive side enable. Bit Bit cannot both be 1; 1: Enable single-ended mode 0: Differentail mode For manual mode only: 12 bit ADC input channel select control bits. adc12_ctrl Selected channel 000 PGA inputs, differential 001 Temperature sensing inputs, differential 010 input A, positive and negative 011 input B, positive and negative 100 input C, positive and negative 12b ADC power up control. 1: Power up ADC 0: Power down ADC ADC channels PAG inputs, differential Temperature sensing, differential Input A, positive or differential Input A, negative Input B, positive or differential Input B, negative Input C, positive or differential Input C, negative Register Description Temperature sensing, differential, write 1 to clear PGA inputs, differential, write 1 to clear Table 16: ADC manual mode 30 / 45 PHY6212 Product Specification v1.6 ADC can also be configured into auto channel sweep mode by setting the “adc_ctrl_override” bit to 0, with which the enabled channels will be sampled in the configured order automatically. The ten ADC input channels can be configured by programming their corresponding registers. Their configurations include sampling time, enable/disable, differential/single-ended, and continuous sampling/singleshot, based on the following register table. The sampled data is stored in the corresponding memory locations as in manual mode. 0x4000_F06C ADC_CTL0 [31:16] Temperature sensing, auto mode, differential [15:0] PGA inputs, differential 0x4000_F070 [31:16] [15:0] 0x4000_F074 [31:16] 0x4000_F074 [15:0] ADC_CTL1 Inputs A, negative Input A, positive or differential ADC_CTL2 Input B, negative Register Description channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only Register Description channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only Register Description channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only ADC_CTL2 Input B, positive or differential Register Description channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one 31 / 45 PHY6212 Product Specification v1.6 shot 1. For auto channel sweep mode only 0x4000_F078 [31:16] [15:0] ADC_CTL3 Input C, negative Register Description channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate 256k, 3T to 63T, step 4T, T is period of 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only channel config: [3:0] sample time, for max rate 320k: 2T to 62T, step 4T; for max rate Input C, positive or 256k, 3T to 63T, step 4T, T is period of differential 1.28MHz; [4] channel enable; [5] differential 1 or single-ended 0; [6] continuous 0 or one shot 1. For auto channel sweep mode only Table 17: ADC channel configurations 4.15.3 ADC Channel Connectivity PGA inputs hardwired temp sensing hardwired aio Input A negative aio Input A positive aio Input B negative aio Input B positive aio Input C negative aio Input C positive Table 18: ADC channel connectivity Aio and PGA inputs(Aio) can be selected through an analog Mux by programming aio_pass or aio_attn. For example, register 0x4000_F020 set to 01, then Aio is connected to ADC input A positive node. Register Description 0x4000_F020 32 / 45 PHY6212 Product Specification v1.6 [13:8] Attenuation ctrl [5:0] pass ctrl attn[5:0]. analogIO control for {aio, aio, aio, aio, aio, aio}. {attn[x], pass[x]}: 00 switch off 01 pass 10 attenuate to 1/4 11 NC pass[5:0]. analogIO control for {aio, aio, aio, aio, aio, aio}. {attn[x], pass[x]}: 00 switch off 01 pass 10 attenuate to 1/4 11 NC note: analog IO sharing gpio/aio gpio/aio gpio/aio gpio/aio gpio/aio gpio/aio/32K XTAL input gpio/aio/32K XTAL output gpio/aio/pga in+ gpio/aio/pga ingpio/aio/mic bias Table 19: analog Mux 33 / 45 PHY6212 Product Specification v1.6 5 Absolute Maximum Ratings Maximum ratings are the extreme limits to which PHY6212 can be exposed without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the PHY6212. Table 20 specifies the absolute maximum ratings for PHY6212. Symbol Supply voltages VDD3 DEC VSS I/O pin voltage VIO Environmental Storage temperature MSL ESD HBM Parameter Min. Max. Unit -0.3 +3.6 1.32 0 V V V -0.3 VDD + 0.3 V -40 +125 °C Moisture Sensitivity Level Human Body Model Class 2 Charged Device Model (QFN48, 7x7 mm package) 3 2 kV 500 V Endurance 100 000 write/erase cycles Retention Number of times an address can be written between erase cycles 10 years at 40 °C ESD CDMQF Flash memory 2 Table 20: Absolute maximum ratings 34 / 45 times PHY6212 Product Specification v1.6 6 Operating Conditions The operating conditions are the physical Parameters that PHY6212 can operate within as defined in Table 21. Symbol VDD3 tr_VDD TA Parameter Supply voltage, normal mode Supply rise time (0 V to 1.8 V) Min. 1.8 Operating temperature (consumer) -40 Operating temperature (Industrial) -40 Table 21: Operating conditions 35 / 45 Typ. 3 Max. 3.6 100 Units V ms 27 27 85 105 °C °C PHY6212 Product Specification v1.6 7 7.1 Radio Transceiver Radio Current Consumption Parameter Tx only at 0dBm Rx Only 7.2 7.2.1 Description MIN with internal DC-DC @3V with internal DC-DC @3V Table 22: Radio current consumption TYP 6.7 6.7 MAX UNIT mA mA Transmitter Specification BLE TX Parameter RF Max Output Power RF Min Output Power OBW for BLE 1Mbps OBW for BLE 2Mbps OBW for GFSK 500Kbps OBW for GFSK 125bps Error Vector Measure FDEV for BLE 1Mbps FDEV for BLE 2Mbps Description MIN TYP MAX UNIT 10 dBm -20 dBm 20dB occupy-bandwidth for BLE modulation 1Mbps 1100 KHz 20dB occupy-bandwidth for BLE modulation 2Mbps 2300 KHz 20dB occupy-bandwidth for GFSK modulation 2Mbps 1100 KHz 20dB occupy-bandwidth for GFSK modulation 2Mbps 1100 KHz Offset EVM for OQPSK modulation 0.02 Frequency deviation for GFSK modulation 1Mbps 160 250 KHz Frequency deviation for GFSK modulation 2Mbps 320 500 KHz MAX UNIT Table 23: BLE Transmitter specification 7.3 7.3.1 Receiver Specification BLE 1Mbps GFSK RX Parameter Rx Sensitivity co-channel rejection Selectivity +-1MHz Selectivity +-2MHz Selectivity +-3MHz Description Sensitivity test 1Mbps BLE ideal transmitter, 37 Byte BER=1E-3 modulated interferer in channel, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 1MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 2MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 3MHz, 37 Byte BER=1E-3 36 / 45 MIN TYP -97 -6 7 45 50 dBm I/C dB I/C dB I/C dB I/C dB PHY6212 Product Specification v1.6 Parameter Selectivity +-4MHz Selectivity +-5MHz or More Selectivity Imag frequency Intermodulation Description Wanted signal at -67dBm, modulated interferer at +/- 4MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at >=+/- 5MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at imagefrequency, 37 Byte BER=1E-3 Wanted signal at 2402MHz, -64dBm, Two interferers at 2405 and 2408 MHz respectively, at the given power level, 37 Byte BER=1E-3 MIN TYP MAX 50 55 22 -20 Carrier Frequency Offset Tolerance Sample Clock Offset Tolerance UNIT I/C dB I/C dB I/C dB dBm +350 +120 KHz ppm Table 24: BLE 1Mbps GFSK RX 7.3.2 BLE 2Mbps GFSK RX Parameter Rx Sensitivity co-channel rejection Selectivity +-1MHz Selectivity +-2MHz Selectivity +-3MHz Selectivity +-4MHz Selectivity +-5MHz or More Selectivity Imag frequency Intermodulation Description Sensitivity test 2Mbps BLE ideal transmitter, 37 Byte BER=1E-3 modulated interferer in channel, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 1MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 2MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 3MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/- 4MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at >=+/- 5MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at imagefrequency, 37 Byte BER=1E-3 Wanted signal at 2402MHz, -64dBm, Two interferers at 2405 and 2408 MHz respectively, at the given power level, 37 Byte BER=1E-3 Carrier Frequency Offset Tolerance Sample Clock Offset Tolerance MIN TYP -94 -6 -5 9 30 40 55 22 -20 +350 +120 Table 25: BLE 2Mbps GFSK RX 37 / 45 MAX UNIT dBm I/C dB I/C dB I/C dB I/C dB I/C dB I/C dB I/C dB dBm KHz ppm PHY6212 Product Specification v1.6 7.3.3 BLE 500Kbps GFSK RX Parameter Rx Sensitivity co-channel rejection Selectivity +1MHz Selectivity +2MHz Selectivity +3MHz Selectivity +4MHz Selectivity +5MHz or More Selectivity Imag frequency Description Sensitivity test 500Kbps BLE ideal transmitter, 37 Byte BER=1E-3 modulated interferer in channel, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/1MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/2MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/3MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/4MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at >=+/- 5MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at imagefrequency, 37 Byte BER=1E-3 Wanted signal at 2402MHz, -64dBm, Two interferers Intermodulation at 2405 and 2408 MHz respectively, at the given power level, 37 Byte Ber=1E-3 Carrier Frequency Offset Tolerance Sample Clock Offset Tolerance Table 26: BLE 500Kbps GFSK RX 7.3.4 MIN TYP MAX UNIT -98 dBm -4 I/C dB 10 I/C dB 45 I/C dB 50 I/C dB 50 I/C dB 55 I/C dB 24 I/C dB -19 dBm +-350 KHz +-120 ppm BLE 125Kbps GFSK RX Parameter Rx Sensitivity co-channel rejection Selectivity +1MHz Selectivity +2MHz Selectivity +3MHz Selectivity +4MHz Selectivity +5MHz or More Description Sensitivity test 125Kbps BLE ideal transmitter, 37 Byte BER=1E-3 modulated interferer in channel, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/1MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/2MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/3MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at +/4MHz, 37 Byte BER=1E-3 Wanted signal at -67dBm, modulated interferer at >=+/- 5MHz, 37 Byte BER=1E-3 38 / 45 MIN TYP -103 -1 -11 45 50 50 55 MAX UNIT dBm I/C dB I/C dB I/C dB I/C dB I/C dB I/C dB PHY6212 Product Specification v1.6 Parameter Selectivity Imag frequency Intermodulation Description Wanted signal at -67dBm, modulated interferer at imagefrequency, 37 Byte BER=1E-3 Wanted signal at 2402MHz, -64dBm, Two interferers at 2405 and 2408 MHz respectively, at the given power level, 37 Byte BER=1E-3 MIN TYP MAX 28 -18 Carrier Frequency Offset Tolerance Sample Clock Offset Tolerance UNIT I/C dB dBm +350 +120 KHz ppm Table 27: BLE 125Kbps GFSK RX 7.4 RSSI Specifications Parameter RSSI Dynamic Range RSSI Accuracy RSSI Resolution RSSI Period Description RSSI Accuracy Valid in range -100 to -30dBm Totally 7bit, from 0 to 127 Table 28: RSSI specifications 39 / 45 MIN TYP 70 +/-2 1 8 MAX UNIT dB dB dB us PHY6212 Product Specification v1.6 8 Glossary Term AHB AHB-AP AMBA AON APB APB-AP BROM DAP ETM FPU I2C I2S ITM JTAG JTAG-AP JTAG-DP J&M MPU NVIC PCR POR RFIF SWD SoC SPI SRAM TWI UART WDT Description Advanced High-performance Bus (ARM bus standard) DAP AHB Port for debug component access thru AHB bus Advanced Microcontroller Bus Architecture Always-on power domain Advanced Peripheral Bus (ARM bus standard) DAP APB Port for debug component access thru APB bus Boot ROM Debug Access Port ( ARM bus standard) Embedded trace module Floating Point Unit Inter-Integrated Circuit Inter-IC Sound, Integrated Interchip Sound Instrumentation Trace Macrocell Unit Joint Test Access Group (IEEE standard) DAP’s JTAG Access Port to access debug components DAP’s JTAG Debug Port used by external debugger Jun and Marty LLC Memory Protection Unit Nested vector Interrupt Controller Power Clock Reset controller Power on reset, it is active low in this document APB peripheral to interface RF block Serial Wire DAP (ARM bus standard) System on chip Serial Peripheral Interface Static Random Access memory Two-Wire Interface Universal Asynchronous Receiver and Transmitter Watchdog Timer Table 29: Glossary 40 / 45 PHY6212 Product Specification v1.6 9 9.1 Ordering information Chip Marking Example PHY+ PHY6212QA VFFTPPPMM YYWWLLLLLL Figure 18: Chip Marking Example 9.2 Chip Marking Rule Figure 19: Chip Marking Rule Abbreviation Definition and Implemented Codes PHYPLUS MICROELECTRONIC PHY6212 Product Package Type Supply Voltage Flash Size Operating Temperature Product Information Manufacturer Information 2-digital Year Code 2-digital Week Code 6-digital Wafer Lot Code Table 30: Chip Marking Rule 41 / 45 PHY6212 Product Specification v1.6 9.3 Order Code PHY6212QA-W04I Operating Supply Voltage Temp. (°C) QFN32 (5x5) 1.8~3.6V -40~105 PHY6212QA-W04C 512KB Reel Quantity MOQ (PCS/R) (PCS) 5000 5000 QFN32 (5x5) 1.8~3.6V -40~85 512KB Reel 5000 5000 PHY6212MAQA-UC QFN32 (5x5) 1.8~3.6V -40~85 512KB Reel 5000 5000 PHY6212MAQA-PD QFN32 (5x5) 1.8~3.6V -40~85 512KB Reel 5000 5000 PHY6212MAQA QFN32 (5x5) 1.8~3.6V -40~105 512KB Reel 5000 5000 PHY6212MAQB QFN48 (7x7) 1.8~3.6V -40~105 512KB Reel Table 31: Order Code 2500 2500 Part No. Package 42 / 45 Flash Packing PHY6212 Product Specification v1.6 10 10.1 Package dimensions QFN32 package dimensions Figure 20: QFN32 package dimensions Note: dimensions are in mm, angels are in degree. 10.2 QFN48 package dimensions Figure 21: QFN48 package dimensions Note: dimensions are in mm, angels are in degree. 43 / 45 PHY6212 Product Specification v1.6 11 11.1 Sample Application and Layout Guide Sample Application Figure 22: Sample application 11.2 Layout Guide 11.2.1 Placement 1. RF matching/Loop filter leading to antenna should be isolated from any other AC/DC signal as much as possible; 2. Xtal/OSC clock is a noise source to other circuits, keep clock trace as short as possible and away from any important area; 3. LDO’s are sensitive and could be easily contaminated, care should be taken for the environment; 4. Antenna is the main RF radiation point, other important blocks should be shielded or away from this area. RF traces 1. Define RF line width with given dielectric thickness (thickness of PCB dielectric layer to ground plain) to achieve 50ohm impedance; this is mainly for the RF line connecting to matching/loop filter and antenna. 2. Differential traces should be kept in the same length and component should be placed symmetrically; 3. Certain length of RF trace should be treated as part of RF matching. 44 / 45 PHY6212 Product Specification v1.6 11.2.2 Bypass Capacitor 1. Each VDD pin needs a bypass capacitor to release chip internal noise and block noise from power supply. 2. For power traces, bypass capacitors should be placed as close as possible to VDD pins. 3. Use one large and one small capacitor when the pin needs two capacitors. Typically the capacitance of the larger capacitor is about 100 times of that of the smaller one. The smaller capacitor usually has better quality factor than the larger one. Place the larger capacitor closer to the pin. 4. The capacitors of Loop filter need to have larger clearance to prevent EMC/EMI issue. 5. Ground via should be close to the Capacitor GND side, and away from strong signals. 11.2.3 Layer Definition 1. Normally 4 layer PCB is recommended. 2. RF trace must be on the surface layer, i.e. top layer or bottom. 3. The second layer of RF PCB must be “Ground ” layer , for both signal ground and RF reference ground , DO NOT put any other trace or plane on second layer, otherwise “antenna effect” will complicate debug process. 4. Power plane generally is on the 3rd layer. 5. Bottom layer is for “signal ” layer. 6. If two layer PCB is used, quality will degrade in general. More care needs to be taken. Try to maximize ground plane, avoid crossing of signal trace with other noise lines or VDD, shield critical signal line with ground plane, maximize bypass capacitor and number of ground vias. 11.2.4 Reference clock and trace 1. 2. 3. 4. Oscillator signal trace is recommended to be on the 1st layer; DO NOT have any trace around or across the reference clock (oscillator) trace. Isolate the reference clock trace and oscillator by having more GND via around. DO NOT have any other traces under the Oscillator. 11.2.5 Power line or plane 1. Whether to use power plain or power line depend on the required current, noise and layout condition. For RF chip, we generally suggest to use power line to bring power into IC pin. Line has parasitic inductance, which forms a low pass filter to reduce the noise traveling around PCB. 2. Add more conductive via on the current source, it will increase max current limit and reduce inductance of via. 3. Add some capacitor alone the power trace when power line travels a long distance. 4. DO NOT place power line or any plane under RF trace or oscillator and its clock trace , the strong clock or RF signal would travel with power line. 11.2.6 Ground Via 1. Ground Via must be as close to the ground pad of bypass capacitor as possible , too much distance between via and ground pad will reduce the effect of bypass capacitor. 2. Having as many ground via as possible. 3. Place ground via around RF trace, the RF trace should be shielded with via trail. 45 / 45
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