Data Sheet
AS3977
M u l t i - C h a n n e l N a r r o w b a n d F S K Tr a n s m i t t e r
1 General Description
The AS3977 is a low-power fully integrated ETSI, FCC and ARIB
compliant FSK transmitter capable of operating at any ISM
frequency in the range of 300 to 928 MHz. It is based on a sigmadelta controlled fractional-N synthesizer phase locked loop (PLL)
with fully integrated voltage controlled oscillator (VCO). The power
amplifier (PA) output is programmable and can deliver power ranging
from –20dBm up to +10dBm. An on-chip low drop-out (LDO)
regulator is available in case an accurate output power independent
of voltage supply variation is required. The output signal can be
shaped using a programmable Gaussian filter to minimize the
occupied bandwidth and adjacent channel power. The maximum
data rate can be up to 100 kb/s – depending on the required filtering.
The FSK frequency deviation is programmable up to a maximum of
64 kHz.
The crystal oscillator can handle a wide range of frequencies. For
narrow-band applications, a temperature sensor with digital read-out
is included that allows compensation of the crystal frequency drift
due to temperature variation.
The AS3977 is connected to an external microcontroller via a bidirectional digital interface. The device operates at very low current
consumption with a power supply range from 2.0V to 3.6V and can
be powered down when not in use.
Main Characteristics
2.0 – 3.6V power supply
Power down current consumption 100 nA (3V, 25ºC)
Output power up to +10dBm
Occupied bandwidth 6 kHz (4.8 kb/s, FFSK, ARIB)
-40 to 85ºC temperature range
Additional Features
Sigma-Delta controlled fractional-N synthesizer
Resolution of synthesizer < 100Hz
Fully integrated PLL
Fully integrated voltage controlled oscillator (VCO)
4kV ESD protection (1.5kV for the Analog pins)
12 – 20 MHz crystal oscillator
On-chip temperature sensor with digital readout for AFC purposes
Fast frequency hopping with predefined channel selection
The device is fabricated in austriamicroystems advanced 0.35µm
SiGe-BiCMOS technology.
Microcontroller clock output to save addition crystal
2 Key Features
Integrated Manchester coder
Constant output power over battery life time
Digital lock detector
Fully integrated UHF transmitter
Low drop-out regulator
Compliant to ETSI EN 300-220, FCC CFR47 part 15 and ARIB
STD-T67
Bi-directional serial interface
Multi-channel with narrow bandwidth
300 – 928 MHz operating frequency range (ISM)
Filtered FSK
Data rate up to 100 kb/s
FSK deviation programmable up to 64kHz
Extremely low power consumption
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Low Power Down Mode current consumption
3 Applications
The AS3977 is suitable for Remote keyless entry systems, Short
range radio data transmission, Domestic and consumer remote
control units, Cordless alarm systems, Remote metering, and Low
power telemetry.
Revision 3.6
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AS3977
Data Sheet - A p p l i c a t i o n s
Figure 1. AS3977 Block Diagram
VCCPLL
Phase
detector
XTAL IN
ΔΦ
÷4
XTAL OUT
Charge
pump
VCC PA
Loop
filter
÷
P
ΣΔ
÷T
RFchannel
Data
sync.
SDI interface/ Control Interface
DATA I/O
CLOCK
ENABLE
VREGDIG
U
VREGRF
Driving
amplifier
Pre Out
PA Out
RF Band
Synthesizer
RF-power
Temp
RF-power
RF-band
RFchannel
LPR
GND
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Pre
Amplifier
÷N
Deviation
U
VCO
±Q
CLK Gen
Baudrate Gen.
MC CLK
VDD
VSS
GND exposed paddle
Revision 3.6
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AS3977
Data Sheet - C o n t e n t s
Contents
1 General Description ..................................................................................................................................................................
1
2 Key Features.............................................................................................................................................................................
1
3 Applications...............................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
5
4.1 Pin Descriptions....................................................................................................................................................................................
5
5 Absolute Maximum Ratings ......................................................................................................................................................
7
6 Electrical Characteristics...........................................................................................................................................................
8
7 Timing Characteristics ............................................................................................................................................................
15
7.1 Timing Parameters .............................................................................................................................................................................
8 Detailed System Description...................................................................................................................................................
16
17
8.1 Reference Frequency Generator........................................................................................................................................................
17
8.2 Phase Locked Loop............................................................................................................................................................................
17
8.3 Gaussian Filter and Digital Modulator ................................................................................................................................................
17
8.4 Power Amplifier ..................................................................................................................................................................................
17
8.5 Temperature Sensor ...........................................................................................................................................................................
17
8.6 Low Power Reset ...............................................................................................................................................................................
17
8.7 Low Drop Out Regulators ...................................................................................................................................................................
17
8.8 SDI / Control Interface ........................................................................................................................................................................
18
8.9 Baud Rate Generator .........................................................................................................................................................................
18
9 Application Information ...........................................................................................................................................................
19
9.1 Operation Modes ................................................................................................................................................................................
19
9.2 Transmitter Control Interface..............................................................................................................................................................
20
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Configuration Diagram...............................................................................................................................................................
Power On Reset ........................................................................................................................................................................
Writing of Data to Addressable Registers..................................................................................................................................
Reading of Data from Addressable Registers ...........................................................................................................................
Transmitting Data ......................................................................................................................................................................
9.3 Transmitter Control States..................................................................................................................................................................
9.3.1
9.3.2
9.3.3
9.3.4
Power Down State .....................................................................................................................................................................
Active Edge of CLK....................................................................................................................................................................
Active State................................................................................................................................................................................
Transmit State ...........................................................................................................................................................................
21
22
22
23
25
25
25
26
26
26
9.4 ENABLE Signal Functionality .............................................................................................................................................................
27
9.5 Communication and Command Byte Structure ..................................................................................................................................
28
9.6 Transmitter Configuration Register.....................................................................................................................................................
29
9.7 Special Bits.........................................................................................................................................................................................
33
9.7.1
9.7.2
9.7.3
9.7.4
LT (Lock Transmit).....................................................................................................................................................................
LS (Low Power Supply Voltage) ................................................................................................................................................
MCCS, CLKS and PSC .............................................................................................................................................................
SETPD (Set Power Down).........................................................................................................................................................
9.8 Output Frequency Setting...................................................................................................................................................................
33
33
33
33
34
9.8.1 Implementation .......................................................................................................................................................................... 35
9.8.2 Optional Frequency Calculation with Overlapping Fractional Bands by Using the Bit INT.................................................. 36
9.8.3 FSK Deviation Setting and Frequency Trimming....................................................................................................................... 37
9.9 Baud Rate Generator .........................................................................................................................................................................
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Revision 3.6
38
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AS3977
Data Sheet -
9.10 Reference Design PREOUT and PAOUT Connection .....................................................................................................................
38
9.10.1 Matching Circuit and PREOUT and PAOUT Connections to the Supply Voltage ................................................................... 38
10 Measurement Results...........................................................................................................................................................
41
10.0.1 Applicable Radio Standards .................................................................................................................................................... 43
11 Package Drawings and Markings..........................................................................................................................................
44
12 Ordering Information.............................................................................................................................................................
46
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Revision 3.6
4 - 47
AS3977
Data Sheet - P i n A s s i g n m e n t s
4 Pin Assignments
PREOUT
1
PAOUT
2
VREGRF
VCCPA
GND
VSS
Figure 2. Pin Assignments (Top View)
16
15
14
13
AS3977
12
MCCLK
11
DATAIO
VCCPLL
4
9
VREGDIG
5
6
7
8
XTALOUT
VDD
XTALIN
10
CLK
3
ENABLE
GND
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
Pin Number
Type
Description
PREOUT
PREOUT
Open Collector preamplifier output, need a feeding coil
connected to VREGRF or VDD and is the input for the Power
amplifier
1
PAOUT
PAOUT
2
RESERVED
3
VCCPLL
4
Open Collector power amplifier output, need a feeding coil
connected to VREGRF or VDD
PREOUT
Must be connected to GND
Positive Power Pin
Positive supplies of VCO, for optimum performance, add
decoupling capacitors on this Pin.
ENABLE
ENABLE
5
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Digital CMOS level input, internal Pull down resistor > 60k
Revision 3.6
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AS3977
Data Sheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
Pin Number
CLK
6
Type
CLK
SDI clock
VDD
XTALIN
Description
VDD
XTAL oscillator input, DC Level approximately 1 Volt, needs an
DC Blocker in case of external clock
7
VDD
XTALOUT
XTALOUT
XTAL oscillator output, DC Level approximately 1 Volt
8
VDD
VREGDIG
9
VDD
10
DATAIO
11
MCCLK
12
VSS
13
Reserved
14
VCCPA
15
VREGDIG
Voltage regulator2 (VRegDig) output, requires a capacitor with
nominal 100 nF.
Positive Power Pin
16
GND
17
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Digital CMOS level input Pin, SDI data input / output
DATAIO
MCCCLK
Micro controller clock output Digital output with variable driver
strength
Negative supply of digital part
GND Pin
Must be connected to GND
Positive Power Pin
VCCPA
VREGRF
Positive supply of digital part and voltage regulator2 (VRegDig)
VREGRF
GND Power Pin
Positive supply of PA and voltage regulator
Voltage regulator output to feed the RF Amplifier. For optimum
performance a capacitor with nominal 1µF and 100 nF is
recommended.
Negative supply of analogue part (exposed paddle)
Revision 3.6
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AS3977
Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” (see Table 3) is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
Comments
Positive supply voltage (VSUP)
-0.5
5.0
V
Voltage on all supply Pins VCCPA,VCCPLL,VDD
Negative supply voltage (GND, VSS)
0
0
V
Input current (latch-up immunity) (ISCR)
-40
40
mA
Norm: Jedec 17
ESDDHBM
±4
kV
Norm MIL 883 E method 3015
(Human Body Model)
ESDDMM
±200
V
Norm: EIJA IC-121
(Machine Model)
ESDAHBM
±1.5
kV
Norm MIL 883 E method 3015
(Human Body Model)
ESDAMM
±100
V
Norm: EIJA IC-121
(Machine Model)
ESDRFHBM
±1.5
kV
Norm MIL 883 E method 3015
(Human Body Model)
ESDRFMM
±100
V
Norm: EIJA IC-121
(Machine Model)
ESD for Digital Pins
ESD for Analog Pins
ESD for RF Pins
Total power dissipation
(all supplies and outputs)
Storage temperature, (TSTRG)
-55
Package body temperature (TBODY)
Humidity non-condensing
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5
200
mW
125
ºC
260
ºC
85
%
Revision 3.6
Norm: IPC/JEDEC J-STD-020C.
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020C “Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
7 - 47
AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
Table 3. Operating Conditions
Symbol
Parameter
Conditions
Min
VSUP
Positive supply voltage analog
Voltage on all supply
VCCPA,VCCPLL,VDD
GND
Max
Units
2.0
3.6
V
Negative supply voltage analog
0
0
V
VSS
Negative supply voltage digital
0
0
V
A-D
Difference of supplies
-0.1
0.1
V
TAMB
Ambient Temperature
-40
85
ºC
Max
Units
VCC-VDD, GND-VSS
Typ
Table 4. Block Specification
Symbol
Parameter
Conditions
fOUT315
fOUT434
fOUT868
Output Frequency Range
fOUT915
POUT
Output Power
Depends on Power Setting
fFSKdata
FSK Data Rate
Internal Manchester Coding
Min
Typ
300
320
425
450
865
870
902
928
1
100
0.5
50
0
±64
MHz
kbit/s
315MHz Frequency Band Section, FCC part 15 is applicable
ΔFSK1
FSK Deviation
programmable (8bit)
Resolution of FSK Deviation (see Table 5)
PSPE1
Spurious Emissions
(max. –19.6dBm radiated fundamental
1
power)
216-960MHz
at frequencies > 960Mhz
at harmonics
Phase noise @ 50 kHz
Phase noise @ 250 kHz
Phase noise @ 1 MHz
kHz
-49
-41
dBm
-40
-86
Charge pump setting: ICHP=50µA;
VSUP=2.0..3.6V,
TAMB=-40..85ºC
-92
dBc/Hz
-102
434MHz Frequency Band Section, EN 300 220 and/or ARIB STD-T67 are applicable
ΔFSK2
FSK Deviation
Phase noise @ 50 kHz
Phase noise @ 250 kHz
Phase noise @ 1 MHz
PACP2
OBW2
Adjacent Channel Power
Occupied Bandwidth
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Small deviation (ARIB), programmable
(8bit)
Resolution of FSK Deviation (see Table 5)
±1.25
±4
0
±64
-86
Charge pump setting: ICHP=50µA;
VSUP=2.0…3.6V,
TAMB=-40…85ºC
-83
-94
dBc/Hz
-102
ARIB, fREF=4MHz, ICHP=50µA
-40
Channel spacing 12.5 kHz, FSK data rate
4.8 kbit/s (ARIB)
FSK Deviation ±1.8 KHz
8.5
GF Setting (see Gaussian Filter Clock
Setting on page 38)
Channel spacing 25 kHz,
FSK data rate 9.6 kbit/s (ARIB)
FSK Deviation ±3.0 KHz
Revision 3.6
kHz
8.5
16
dBc
kHz
8 - 47
AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Block Specification (Continued)
Symbol
Parameter
Conditions
1
excluding Harmonics
Spurious Emissions
1
and Harmonics
Max
Units
-54
dBm
at other frequencies < 1GHz
at ≥ 1GHz (EN 300 220)
-36
ARIB
-29
With ideal crystal,
VSUP=2.0…3.6V,
TAMB=-40…85ºC
±1
ppm
±64
kHz
-54
dBm
Output Frequency Error
fERROR
Typ
47-74MHz
87.5-118MHz
174-230MHz
470-862MHz (EN 300 220)
Spurious Emissions
PSPE2
Min
-30
dBm
868MHz Frequency Band Section, EN 300 220 is applicable
ΔFSK3
programmable (8bit)
Resolution of FSK Deviation (see Table 5)
FSK Deviation
47-74MHz
87.5-118MHz
174-230MHz
470-862MHz (@-10dBm radiated power)
Spurious Emissions
PSPE3
0
1
excluding Harmonics
Spurious Emissions
-36
at other frequencies < 1GHz
at frequencies ≥ 1GHz
1
and Harmonics
Phase noise @ 50 kHz
-30
-78
Charge pump setting: ICHP=50µA;
VSUP=2.0…3.6V,
TAMB=-40…85ºC
Phase noise @ 250 kHz
Phase noise @ 1 MHz
dBm
-85
dBc/Hz
-89
915MHz Frequency Band Section, FCC part 15 is applicable
ΔFSK4
FSK Deviation
programmable (8bit)
Resolution of FSK Deviation (see Table 5)
PSPE4
Spurious Emissions
(max. –1dBm radiated fundamental
1
power)
216-960MHz
at frequencies > 960MHz and harmonics
0
±64
kHz
-49
-41
dBm
1. These parameters will not be tested.
Table 5. Resolution of FSK Deviation
Symbol
Parameter
Conditions
Equation for Min. Resolution
For detailed information, See FSK
Deviation Setting and Frequency
Trimming on page 37
REF
ΔF = (INT +1). --------16
For detailed information, See FSK
Deviation Setting and Frequency
Trimming on page 37
REF
ΔF = (INT +1). --------15
Units
315MHz and 434MHz Frequency Band Section
ΔFSKres1
Resolution of FSK Deviation
1
f
Hz
2
868MHz and 915MHz Frequency Band Section
ΔFSKres2
Resolution of FSK Deviation
1
f
Hz
2
1. INT refer to Register Settings
Table 6. Reference Frequency Generator and Micro Controller Clock Driver
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Crystal Oscillator
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Revision 3.6
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AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 6. (Continued)Reference Frequency Generator and Micro Controller Clock Driver
Symbol
Parameter
Conditions
fXOSC
Crystal Oscillator Frequency
tXOSC
Crystal Oscillator Start up time
VSUP=2.0…3.6V,
TAMB=-40…85ºC
crystal series resistance ≤ 100Ω
RXOSC
Crystal Oscillator Oscillation Margin
Level
fXOSC=13.56MHz, CL=12pF
Δf/f0
Frequency Stability vs. Temperature
1
Min
Typ
Max
Units
12
16
20
MHz
1.5
ms
Ω
1500
AS3977 Only
±1
ppm
Micro Controller Clock Driver
fMCCLK
Clock output frequency
depending on configuration register
settings and crystal
4
MHz
VMCL
Low level output voltage
VSUP=3V, at nominal high level output
current
0.1*VSUP
V
VMCH
High level output voltage
VSUP=3V, at nominal high level output
current
CLMCC
Capacitive load
20
pF
tRMCC
Rise time
62.5
ns
tFMCC
Fall time
62.5
ns
IMCH
High level output current
1
mA
IMCL
Low level output current
1
mA
0.9*VSUP
V
1. These parameters will not be tested.
Table 7. Phase Locked Loop
Symbol
Parameter
Conditions
Min
Typ
Max
Units
fREF
Comparison Frequency
depending on fXOSC
(reference divider division ratio = 4)
3.0
4.0
5.0
MHz
ΔfO
Output Frequency Resolution
fOUT315 / fOUT434
fOUT868 / fOUT915
46
61
77
92
122
153
tSYNTH
Synthesizer Start up Time
tLOCK
Synthesizer Lock Time
500
Δf=600kHz,
fERROR @ tLOCK=10kHz
Hz
µs
50
200
µs
Typ
Max
Units
Table 8. Loop Filter Bandwidth
Symbol
Parameter
Conditions
Min
Filter Bandwidth at 315 MHz
@ 12.5 µA
fBW
Charge pump setting: @ 25 µA
ICHP
@ 37.5µA
55
Reference Frequency = 4MHz
VSUP = 3.0 V;
TAMB = 25ºC
@ 50 µA
85
115
kHz
170
Filter Bandwidth at 433 MHz
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Revision 3.6
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AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 8. (Continued)Loop Filter Bandwidth
Symbol
Parameter
Conditions
Min
@ 12.5 µA
fBW
Typ
Max
Units
50
Reference Frequency = 4MHz
VSUP = 3.0 V;
TAMB = 25ºC
Charge pump setting: @ 25 µA
ICHP
@ 37.5µA
70
kHz
90
@ 50 µA
120
Filter Bandwidth at 868 MHz
@ 12.5 µA
fBW
50
Reference Frequency = 4MHz
VSUP = 3.0 V;
TAMB = 25ºC
Charge pump setting: @ 25 µA
ICHP
@ 37.5µA
70
kHz
90
@ 50 µA
120
Table 9. Power Amplifier (300 - 320 MHz and 425 - 450 MHz Bands)
Symbol
POUT
POUT
Parameter
Conditions
Min. Output Power @ 50Ω
VSUP=3V, @ 25ºC,
Power depending on power setting with or
without the use of the internal voltage
regulator, external matching network
included
-20
dBm
Max. Output Power @ 50Ω
VSUP=3V, @ 25ºC,
Power depending on power setting with or
without the use of the internal voltage
regulator, external matching network
included
8
dBm
POUT
POUT
POUT
Max
Units
1
-2.5
+2.5
dBm
1
VSUP=3V, @ 25ºC,
Power depending on register setting with
or without the use of the internal voltage
regulator,
external matching network included,
strong AB operation mode
-2.0
+2.0
dBm
VSUP=2.2…3.6V, TAMB=-40…85ºC, With
Output Power Variation vs. VDD and the use of the internal voltage regulator,
Temperature @ 50Ω
external matching network included,
strong AB operation mode
-2.8
1.0
dB
Variation@ 50Ω
(300 – 320MHz)
Output Power
POUT
Typ
VSUP=3V, @ 25ºC,
Power depending on register setting with
or without the use of the internal voltage
regulator,
external matching network included,
strong AB operation mode
Output Power
POUT
Min
Variation@ 50Ω
(425 – 450MHz)
+0.6 /
-1.5
Output Power Variation vs.
Temperature @ 50Ω
VSUP=3V, TAMB=-40..85ºC,
Without the use of the internal voltage
regulator,
external matching network included,
strong AB operation mode
+1.5 /
-2.0
dB
Max Output Power @ 50Ω
VSUP=3.6V, @ 25ºC,
Power depending on power setting
without the use of the internal voltage
regulator,
external matching network included
10
dBm
1. Limits by production test measurement uncertainties
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Revision 3.6
11 - 47
AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 10. Power Amplifier (865 - 870 MHz and 902 - 928 MHz Bands)
Symbol
POUT
POUT
POUT
Parameter
Conditions
Min Output Power
@ 50Ω
VSUP=3V, @ 25ºC,
Power depending on power setting with or
without the use of the internal voltage
regulator,
external matching network included
-20
dBm
Max Output Power
@ 50Ω
VSUP=3V, @ 25ºC,
Power depending on power setting with or
without the use of the internal voltage
regulator, external matching network
included
4
dBm
1
Output Power Variation @ 50Ω
VSUP=3V, @ 25ºC,
Power depending on register setting with
or without the use of the internal voltage
regulator, external matching network
included, strong AB operation mode
POUT
Output Power Variation vs.
Temperature @ 50Ω
Max
+3.5
Units
dBm
2
+2.0 /
-3.0
dB
+2.0 /
-3.0
dB
2
VSUP=3V,
TAMB=-40…85ºC,
Without the use of the internal voltage
regulator, external matching network
included, strong AB operation mode
Typ
-3.5
VSUP=2.2…3.6V,
TAMB= -40…85ºC,
Output Power Variation vs. VDD and With the use of the internal voltage
Temperature @ 50Ω
regulator, external matching network
included, strong AB operation mode
POUT
Min
2
1. Limits by production test measurement uncertainties
2. Power line matching needs to be adjusted to VDD to ensure strong AB operation mode
Table 11. Antenna Tuning Circuit
Symbol
Parameter
Conditions
CAtmin
Minimum Antenna tuning Capacitor
ATCPH = 0000
0.11
pF
Maximum Antenna tuning Capacitor
ATCPH = 1111
1.51
pF
CAtmax
Min
Typ
Max
Units
Table 12. Low Power Reset (Bit LT)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VLPR
Low Power Detection Threshold
Voltage
Decreasing Supply Voltage
1.85
1.95
2.05
V
VLPR
Low Power Release Threshold
Voltage
Rising Supply Voltage
2.05
V
Table 13. Low Supply Voltage Detector (Bit LS)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VLS
Low Supply Detection Threshold
Voltage
Decreasing Supply Voltage
2.0
2.1
2.2
V
VLS
Low Supply Release Threshold
Voltage
Rising Supply Voltage
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Revision 3.6
2.17
12 - 47
AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 14. Temperature Sensor
Symbol
Parameter
Conditions
Min
ERRTS
Absolute Error
TAMB = -40…85ºC
-5
ERRTSL
Absolute Error (limited temperature
range)
TAMB = -20…65ºC
±2
ºC
Conversion Factor
TAMB = -40…85ºC
0.19
ºC/bit
10
bit
ORTS
Output Resolution
CRTS
Conversion Rate
Typ
fTS = fCRYSTAL/12
after startup time of 256 / fTS
Max
Units
+5
ºC
fTS/1354
samples/
s
Max
Units
Table 15. Voltage Regulator for Power Amplifier
Symbol
Parameter
Conditions
Min
Typ
VREGRF
Output Voltage for supply Power
Amplifier
Adjustable, nominal value
1.7
2.0
V
D_VREGR
F
Regulator Tolerance
-0.15
0.1
V
Typ
Max
Units
VSUP=3V @ 25ºC
100
250
VSUP=2.0…3.6V,
TAMB=-40…85ºC
1000
5000
VSUP=3V @ 25ºC,
Cload≤20pF, fCLK=20MHz
1
1.25
VSUP=2.0…3.6V,
TAMB=-40..85ºC, Cload≤20pF,
fCLK=20MHz
1.25
1.6
Table 16. Current Consumption
Symbol
Parameter
IPDWN
Power Down Mode
ICLKEN
Clock Enable Mode
Conditions
Min
nA
mA
ITemp_sens
Temperature sensor Current
VSUP=2.0..3.6V,
TAMB=-40..85ºC
0.25
mA
IPLLEN
PLL Enable Mode
VSUP=2.0…3.6V,
TAMB=-40…85ºC
5.6
mA
VSUP=3V @ 25ºC
Transmit Mode @ 8dBm output
power,
ITX8dBm31 315 MHz band @ 50Ω including
5
matching network, strong AB
operation
VSUP=2.0…3.6V,
TAMB=-40…85ºC
VSUP=3V @ 25ºC
VSUP=2.2…3.6V,
TAMB=-40…85ºC
VSUP=3V @ 25ºC
Transmit Mode @ 8dBm output
power,
ITX8dBm43 433 MHz band @ 50Ω including
3
matching network, strong AB
operation
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VSUP=2.0…3.6V,
TAMB=-40…85ºC
VSUP=3V @ 25ºC
VSUP=2.2…3.6V,
TAMB=-40…85ºC
without the use of
the internal
1
regulator
with the use of the
internal regulator
without the use of
the internal
regulator
with the use of the
internal regulator
Revision 3.6
13.5
16.5
mA
15.5
19
mA
14.0
17.0
mA
16.0
19.5
mA
12.5
15.5
mA
14.5
18
mA
13.0
16.0
mA
15
18.5
mA
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AS3977
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 16. Current Consumption
Symbol
Parameter
Conditions
VSUP=3V @ 25ºC
Transmit Mode @ 4dBm output
power,
ITX4dBm86 868 MHz and 906MHz band @
8
50Ω including matching
network, strong AB operation
VSUP=2.0…3.6V,
TAMB=-40…85ºC
VSUP=3V @ 25ºC
VSUP=2.2…3.6V,
TAMB=-40…85ºC
Min
without the use of
the internal
regulator
with the use of the
internal regulator
Typ
Max
Units
14.5
17.5
mA
16.5
19.0
mA
15.0
18.0
mA
17.0
19.5
mA
Max
Units
1. Power line matching needs to be adjusted to VDD to ensure strong AB operation mode
Table 17. DC/AC Characteristics for Digital Interface
Symbol
Parameter
Conditions
Min
Typ
CMOS Input
VIH
High Level Input Voltage
0.7 *
VSUP
VSUP +
0.1
V
VIL
Low Level Input Voltage
VGND -0.1
0.3 * VSUP
V
IIL
Low Level Input Leakage Current
no internal pull up/down
±1
µA
IIH
High Level Input Leakage Current
no internal pull up/down
±1
µA
IIHPD
High Level Input Leakage Current with
internal pull down
VSUP=3.6V, VIN=3.6V
60
µA
15
CMOS Output
Note: The following specification is valid for the DATAIO standard CMOS output. The MCCLK output can be programmed to different driver
strengths according MCCDS register.
VOH
High level output voltage
VSUP=3V, at nominal high level output
current
VOL
Low level output voltage
VSUP=3V, at nominal low level output
current
CL
tR
VSUP-0.5
V
VSS+0.4
V
Capacitive load
20
pF
Rise time
50
ns
tF
Fall time
50
ns
IOH
High level output current
1
mA
IOL
Low level output current
1
mA
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AS3977
Data Sheet - T i m i n g C h a r a c t e r i s t i c s
7 Timing Characteristics
16
Be aware that the Power Down Mode can be entered by setting ENABLE low for more than 2 XTAL cycles (Power Down Timer).
Figure 3. Write Data
ENABLE
tCS
tCHD
tCH
tEH
tCL
CLK
polarity
CLK
tMS
tMH
tDIS
MCCLK
behavior
DATAI
tDIH
DATAI
DATAI
DATAI
DATAO
Figure 4. Read Data
ENABLE
tCL
tCH
CLK
DATAI
DATAI
DATAI
tDIHZ
DATAO
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tDOS
tDOH
DATAO (D7N)
Revision 3.6
tDOHZ
tDOD
DATAO (D00)
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AS3977
Data Sheet - T i m i n g C h a r a c t e r i s t i c s
7.1 Timing Parameters
Table 18. Timing Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Units
2
Mbps
General
BRSDI
Bit rate
tCH
Clock high time
250
ns
tCL
Clock low time
250
ns
tDIS
Data in setup time
20
ns
tDIH
Data in hold time
10
ns
tEH
Enable hold time
20
ns
Write timing
Read timing
tDIHZ
Data in to high impedance delay
tDOS
Data out setup time
130
ns
tDOH
Data out hold time
135
ns
tDOD
Data out delay
tDOHZ
Data out to high impedance delay
time for the µC to release the DATAIO bus
45
time for the SDI to release the DATAIO
bus
ns
80
ns
80
ns
Timing parameters when leaving the Power Down Mode (for determination of CLK polarity and MCCLK behavior)
tCS
Clock setup time
(CLK polarity)
Setup time of CLK with respect to
ENABLE rising edge
20
ns
tCHD
Clock hold time
(CLK polarity)
Hold time of CLK with respect to ENABLE
rising edge
20
ns
tMS
Data in setup time
(MCCLK behavior)
DATAIO setup time with respect to
ENABLE rising edge
20
ns
tMH
Data in hold time
(MCCLK behavior)
DATAIO hold time with respect to
ENABLE rising edge
20
ns
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AS3977
Data Sheet - D e t a i l e d S y s t e m D e s c r i p t i o n
8 Detailed System Description
The AS3977 is based on a fully integrated sigma-delta controlled fractional-N synthesizer phase locked loop (PLL) and a power amplifier (PA). A
reference frequency generator including a crystal oscillator provides the comparison frequency of the PLL and a high-precision clock output. A
programmable Gaussian filter enables to minimize the occupied bandwidth and adjacent channel power. A temperature sensor with digital readout is included that allows compensation of the crystal frequency drift due to temperature variation. An on-chip low drop out regulator (LDO) is
available in case an accurate output power independent of supply voltage variation is required. A second LDO for the digital supply voltage helps
to minimize interference between the analog and digital part and decreases the current consumption of the digital part. A PROM enables the
compensation of process variation. The AS3977 is controlled by an external microcontroller via a bi-directional serial digital interface (SDI).
8.1 Reference Frequency Generator
The reference frequency generator consists of a crystal oscillator and frequency divider. The crystal oscillator can be driven externally in case an
external clock frequency is supplied.
8.2 Phase Locked Loop
The PLL is of standard charge pump type. The phase frequency detector is designed such that dead zone problems are avoided. The charge
pump current is programmable. All loop filter components are on-chip, the bandwidth is programmable through the charge pump current. The
differential based voltage controlled oscillator (VCO) has integrated inductors and varactors. The VCO operates at a center frequency around
1.8GHz. To cover the specified frequency range over process variation, the sufficiently wide overall tuning range is split into 16 overlapping
frequency bands. At start up of the PLL, an automatic range select circuit (ARS) selects the proper frequency band. The VCO output frequency
is divided by 2, 4, and 6, which enables to cover output frequencies in the range of 850 – 928 MHZ, 425 – 450 MHz and 300 – 320 MHz,
respectively. A lock detector enables to monitor the PLL lock status.
8.3 Gaussian Filter and Digital Modulator
The programmable sigma-delta modulator controls the output frequency of the PLL. The order of the modulator is programmable (MASH2 or
MASH3). In combination with the programmable Gaussian filter for the data signal, the modulator performs the FSK modulation with
programmable deviation, whereby the Gaussian Filter enables to minimize the occupied bandwidth and the adjacent channel power.
8.4 Power Amplifier
The power amplifier is single ended and consists of a preamplifier and an output stage, both with open collector. The necessary external chokes
can be connected to a LDO in case an accurate output power independent of supply voltage variation is required. The output power is
programmable up to 10dBm.
8.5 Temperature Sensor
The AS3977 includes a temperature sensor to measure the absolute temperature inside the chip. The analog value is converted to a digital value
and can then be read out by the microcontroller in order to control the output frequency and/or the transmission power. The value of the chip
temperature in degree can be obtained using following formula:
Temperature = TS < 9…0 > * 0.19 – 50
(EQ 1)
The temperature sensor can be used to compensate the crystal drift over temperature.
Note: AS3977 has the same temperature than the crystal only at start up and the temperature will increase immediately thereafter due to self
heating.
Temperature sensor must be used only in the Clock Enable Mode as a stand alone block. It is mandatory to be used with the PLL and Power
Amplifier switched off.
8.6 Low Power Reset
The low power reset (LPR) disables the power amplifier, if the supply voltage falls below the low power threshold.
8.7 Low Drop Out Regulators
In order to avoid stability issues, external capacitors are required. (see Table 1)
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AS3977
Data Sheet - D e t a i l e d S y s t e m D e s c r i p t i o n
8.8 SDI / Control Interface
This interface enables a serial and synchronous communication between external microcontroller and AS3977. Data can be written to and read
out from AS3977. Additionally, it facilitates the transmission of TX-data. The rising edge on the SDI enable signal (transition to the active state),
while the device is in Power Down Mode has various effects on the circuit:
- It wakes up the crystal oscillator (this takes maximum 1.5 ms with the specified Crystal parameters)
- It sets the transfer and sampling edge of the AS3977 SDI data signal.
- It activates the Micro Controller clock output depending on the register setting and the value of the data signal.
Thus, the wakeup event through the SDI interface determines the basic communication between AS3977 and the microcontroller. In addition it
takes some time to have a stable crystal oscillator clock available. Therefore all functions that require a stable crystal oscillator clock are not
immediately available after the wakeup.
8.9 Baud Rate Generator
This module generates two clocks; one used for the microcontroller (MCCLK) and one as baud rate clock with 50% duty cycle. The baud rate
clock is used by the microcontroller to properly synchronize the provided data during transmission with the internal Manchester coder.
The baud rate generator maintains the behavior of MCCLK and keeps it properly synchronized to the TX data clock. For example, a missing
synchronization can occur when clock settings are changed by an asynchronous event like SDI programming or when a new transmission starts.
The Baud rate generator offers different types of data outputs: one fully asynchronous, one synchronous and one synchronous but Manchester
coded. By means of AS3977 command control Byte, any of the three different output data types can be selected.
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
Figure 5. Functional Description Diagram of Timers and Data Synchronization
Powerdown Timer
Set Powerdown
1
Powerdown
/ 2^16
reset
reset
Baudrate
Generator
ENABLE
Prescalar
/ 1,2,4,8,…
128
XTAL
Postscalar
/ 1,2,4,8
counter
8bit
3
PSC
ASC
Data
Synchronization
MC
2
compare
MCCLK
timer
compare
value
3
to
1
8
Data Generator
3
to
1
INV
2
CLK Source
TXDO
xor
TXDATA
The Prescaler divides the XTAL frequency by fOUT=2
-PSC
*fIN
The Compare timer divides by fOUT=fIN/(TCV+1) and the Postscaler divides the input frequency by fOUT=2
frequency of:
-(PSC+ASC+1)
fOUT=2
-ASC
*fIN which leads into a data
* fIN / (TCV+1)
(EQ 2)
9.1 Operation Modes
All modes are controlled by the SDI interface.
Power Down Mode
The AS3977 is connected to the power supply and can be switched to power down mode. The current consumption is limited by the leakage
current.
Clock Enable Mode
In this mode, only the reference frequency generator is switched on and a clock signal is supplied via the clock output.
PLL Enable Mode
The PLL is switched on and locked at the selected output frequency. The power amplifier is in power down mode. This mode enables OOKASK modulation by switching the PA on and off.
Transmit Mode
The PLL is switched on and locked at the selected output frequency. The power amplifier is in power on mode. This is the FSK mode for
transmitting data.
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 6. Operation Mode Relations
Power ON
ENABLE High
Pulse
16
ENABLE to LOW for 2
XTAL cycles
or
Software Power Down
command via SPI
External
Hardware
Reset
Power Down
Mode
ENABLE is
HIGH
Clock Enable
Mode
SPI
Command
PLL Enable
Mode
SPI
Command
Transmit Mode
9.2 Transmitter Control Interface
The AS3977 is controlled by an external micro controller (µC) via. a bi-directional communication interface (serial digital interface, SDI). The SDI
enables data to be read from and written to internal control registers without the necessity of an internal clock signal. Analog de-bouncing of
clock and data input is implemented in order to improve the overall system reliability.
The SDI-control interface includes a state machine, which expects a command control word as first byte and in reference to this byte, the
interface is configured as write, read, or transmit operation. This method enables an effective and easy control of basic transmitter functions.
Four preset independent output frequencies and two preset independent output power levels and modulation types can be selected using the
control-command byte, thus enabling fast channel hopping and/or fast changes to the output power level and modulation type. The selection of
the active output frequency and/or power level and modulation type is done using the so-called command byte.
As an additional feature, the AS3977 provides a configurable clock signal derived from the crystal frequency. The purpose of this clock signal is
to provide a µC clock and to enable data synchronization.
16
A timer is included to power down (Power Down Mode) the transmitter after a certain time, which is defined as 2 multiplied with the crystal
oscillator- Period.
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.2.1
Configuration Diagram
The interface has one clock signal for the external µC and the SDI input clock. As the MCCLK line can be used to clock the SDI Interface as well
as must have a high impedance pin during the clocking phase of the microcontroller, the Pin must be bi-directional. The pad behavior is selected
by configuration bits and by setting the SDI DATA-IO Line of the SDI interface when leaving PD. Possible configurations between the interface
and the µC are done using 4 wires as shown in Figure 7.
MCCLK is simply connected to the micro controller and can be used to clock a timer or interrupt logic.
Figure 7. Configuration Diagram
MCCLK
ENABLE
µC
CLK
AS3977
DATAIO
A connection using a set of three wires is required to implement the SDI protocol.
ENABLE signal is used to activate the interface and to wake up the whole IC. In addition, the rising edge of the ENABLE after power down
mode is used to set the starting point of the communication protocol.
CLK represents the SDI clock and both edges can be used for data transfer, dependable on the configuration after wake-up.
DATAIO is a bi-directional signal that goes from microcontroller to the Interface during write and transmit-commands, while it is in the other
direction when the interface is sending data read from the micro controller.
The interface supports the following functionality for the micro controller clock output (MCCLK).
MCCLK can be inactive (MCCLK level not defined), always active after start-up (MCCLK is clocking) or clocking only during transmit.
It is possible to configure and to maintain MCCLK settings (even when leaving PD).
Maximum frequency is specified to fXOSC (by using the prescaler output with a division ratio of 1, PSC=0).
Minimum frequency is fXOSC / 65280 (by using the baud rate generator output with prescaler division ratio of 128 and timer counter value of
255).
The rising edge of ENABLE after a Power Down Mode selects the transfer edge of the SDI-CLK by sampling the SDI clock value itself. This
configuration will be valid until the next PD. Each bit must be transferred and sampled according to the configured edges. For example, if at the
first rising edge of SDI enable SDI clock is LOW, then each bit is transferred from the microcontroller on the rising edge of SDI clock and it is
sampled from AS3977 on falling edge of the SDI clock. This is valid for read as well as for write commands.
During the first byte of the WRITE command communication (command and address), the SDI master drives each new data bit on the transfer
active edge and the SDI slave samples it on the next opposite edge. This protocol will be valid until the last data bit has been written to the
external registers. Data’ are transferred to the registers byte by byte after sampling of the last bit.
It is not necessary to enter the PD mode for reset the Interface. The rising edge of SDI-ENABLE signal starts the communication.
When the command is READ, a direction change on the SDI data wire will be done. This change has to be performed synchronously on SDI
master and slave side, however, the master always provide the SDI clock. After sampling the last addressed bit, the SDI slave pin becomes
active on the following SDI clock edge and the first readable bit read is transferred from SDI slave to the master.
In any case, the SDI master has to reset the SDI interface on the last bit of the data in order to stop the communication by applying an Enable
16
LOW pulse (duration: min > 1 SDI CLK cycle, max: < 1/fcrystal * 2 ).
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.2.2
Power On Reset
For stable start up of the AS3977 and to avoid unwanted crystal oscillation, it is strongly recommended to perform a power on reset (Hardware
Reset Method). This can be performed as described in Table 19 and must be carried out every time when the supply voltage is less than the
minimum allowed value (see Operating Conditions on page 8).
Table 19. Power On Reset
9.2.3
Step
Hardware Reset Method
1
Apply Power to the AS3977
2
Apply Enable high pulse (Low-High-Low transition)
3
Power on reset complete after xtal start up + 2 xtal cycles
16
Writing of Data to Addressable Registers
When the Power Down Mode is left, the level of CLK at the rising edge of ENABLE determines the sampling edge of CLK. If CLK is low, when
ENABLE rises, DATAI is sampled at the falling edge of CLK (see Figure 8 and Figure 9), if CLK is high when ENABLE rises, DATAI is sampled at
the rising edge of CLK.
An Enable LOW pulse indicates the end of the WRITE command after register has been written.
Figure 8 illustrates a write command in which the initialization of DATAIO take over condition is done at the falling edge of CLK signal.
Figure 8. Writing of a Single Byte (falling edge sampling)
16
Enable low must be shorter than 2 clock cycles to keep the power
conditions and the data takeover condition
ENABLE
CLK
DATAIO
0
1
A5
In case the ENABLE line has been longer than
16
2 clock cycles low, data take over condition is
determined here
A4
A3
A2
A1
A0
D7
D6
Data D7 is sampled from AS3977
at this edge
D5
D4
Data D4 is transferred from
Microcontroller
D3
D2
D1
D0
Data D7-D0 is
moved to
Address A5A0 here
ENABLE falling edge signals end of write
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 9. Writing of Data with Auto-Incrementing Address
Enable must be high
in order to keep the
power condition
ENABLE
CLK
DATAIO
0 0
A A A A A A D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data D7-D0 is
moved to
Address A5A0 here
9.2.4
Data D7-D0 is
moved to
Address
A5-A0+1 here
Data D7-D0 is
moved to
Address
A5-A0+2
here
Data D7-D0 is
moved to
Address
A5-A0+3 here
Data D7-D0 is
moved to
Address
A5-A0+4 here
Reading of Data from Addressable Registers
By leaving the Power Down Mode through a rising edge of ENABLE, the level of CLK determines the sampling edge of CLK. If CLK is low, DATAI
is sampled at the falling edge of CLK (see Figure 10 and Figure 11), if CLK is high when ENABLE rises, DATAI is sampled at the rising edge of
CLK. Consequently, data to be read from the microcontroller are driven by the slave (AS3977) at the transfer edge and sampled by the master
(µC) at the sampling edge of CLK. An Enable LOW pulse has to be performed after register data has been transferred in order to indicate the
end of the READ command and prepare the Interface to the next command control Byte.
The command control Byte for a read command consists of a command code and an address. The Command code has to be provided from least
significant bit (LSB) to most significant bit (MSB), e.g. for a read it is = “01”. After the command code, the address of register to be read
has to be provided from the MSB to the LSB. Then one or more data bytes can be transferred from the SDI slave to the master, always from the
MSB to the LSB. To transfer bytes from consecutive addresses, SDI master has to keep the SDI enable signal high and the SDI clock has to be
active as long as data need to be read from the slave.
Each bit of the command and address sections of the frame have to be driven by the SDI master on the SDI clock transfer edge and the SDI
slave samples it on the next SDI clock edge. Each bit of the data section of the frame has to be driven by the SDI slave on the SDI clock transfer
edge and the SDI master on the next SDI clock edge samples it. These edges are selected on the first access after PD and they cannot be
changed until next PD.
If the read access is interrupted (by de-asserting the SDI enable signal), data provided to the master is consistent to given address, but it is only
the register content from MSB to LSB. If more SDI clock cycles are provided, data remains consistent and each data byte belongs to given or
incremented address.
In the following figures (Figure 10 and Figure 11), two examples for a read command (without and with address self-increment) are given. The
initialization base for this timing diagram is a “LOW” on the CLK line during Initialization.
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 10. Reading of a Single Byte (falling edge sampling)
16
Enable low must be shorter than 2 clock cycles to keep the power
conditions and the data takeover condition
ENABLE
CLK
DATAIO line driver control changes from
microcontroller to AS3977
DATAI
0
A5
1
A4
A3
A2
A1
A0
DATAO
DATAIO
0
A5
1
16
A4
In case the enable has been longer than 2 clock cycles
low, the power down state is left and data take over condition is determined here
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data D7-D0 at Address A5-A0 is transferred to the Output Register of AS3977
Signals
end of
read
Figure 11. Reading of Data with Auto-Incrementing Address
ENABLE
CLK
DATAI
(µC Driven)
0 1 A A A A A A
5 4 3 2 1 0
DATAO
(AS3977
Driven)
DATAIO
D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 1
A A A A A A D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D D D D D D D
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data D7-D0 at
Address A5-A0 is
transferred here
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Data D7-D0 at
Address A5-A0+1 is
transferred here
Data D7-D0 at
Address A5-A0+2 is
transferred here
Revision 3.6
Data D7-D0 at
Address A5-A0+3 is
transferred here
Data D7-D0 at
Address A5-A0+4 is
transferred here
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.2.5
Transmitting Data
Command code has to be provided from LSB to MSB and for transmit it is = “11”. After the command code, further configuration has to
be provided from the MSB to the LSB. Then a bit-stream, the data to be sent, can be transferred from the SDI master by keeping SDI enable
signal to high. No SDI clock is required for data synchronization or the input bit stream.
Each bit of the command and address sections of the frame have to be driven by the SDI master on the SDI clock transfer edge and the SDI
slave on the next SDI clock edge samples it.
The transmission starts as follows:
After the last configuration bit has been sampled, the micro controller has to provide an additional SDI clock edge to activate the output amplifier.
This allows the SDI state machine to switch to the TX status and to activate MCCLK. Then, together with the first TX data bit, the next SDI clock
sampling edge provided by the master starts the transmission itself and powers on the analog output driver.
In case, the MCCLK output is properly configured, the transmission will be stopped by the microcontroller by setting the clock to a high
impedance state and the MCCLK output of the Transceiver became active and takes over the communication of the Interface.
The power amplifier is switched on (if not already on) at the subsequent sampling edge of CLK after receiving the transmit command byte. This
allows to delay the PAON signal, e.g. to enable locking of the PLL in case a channel hop has to be performed.
The following figure (Figure 12) shows an example (sampling falling edge) of the transmit command with MCCLK active during TX. It is important
to note in this mode the sequence of events labelled 1-4 in the diagram, which lead to transmission. This mode allows the baud clock to be
synchronized to the external data. In such a case, the synchronization (A5=1) bit should be set within the transmitter configuration.
Figure 12. Transmit Command with MCCLK Active During Tx (falling edge sampling)
ENABLE
Tx Configuration and pre-configuration for
MCLK set
2
CLK
Tx configuration parameter ready
DATAIO
1
1
A5
A4
A3
A2
A1
1
4
uController triggers falling edge of CLK after rising edge of MCLK
Power Amplifier is switched on
A0
Power Amplifier is
switched off or data is sent
continuously
Data to be sent
3
MCLK started synchronous to
internal baud clock
MCCLK
9.3 Transmitter Control States
9.3.1
Power Down State
When the Power Down Mode is entered, the crystal oscillator ends running and two very important bits of the registers are set to their inactive
values:
1. Lock transmit: which is set (1) during PD to forbid any transmission.
2. Setpd: it is reset (0) to avoid a locked Power Down Mode.
When the circuit is in Power Down Mode, the crystal oscillator and all the other analog/digital circuits are OFF. The transmitter interface is the
only supplied circuit and it is sensitive to SDI signals. The current consumption is limited by the leakage current. The configuration registers do
not alter as long as the minimum supply requirements are met. The state can only be left by the rising edge of ENABLE. The state can be
16
entered either by setting the set power down bit (SETPD) via. SDI communication or by setting ENABLE low for more than 2 XTAL cycles
(Power Down Timer). When the Power Down Mode is left (by the rising edge of ENABLE), the crystal oscillator is activated.
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Software Power Down Method.
Step
Software Power Down Method
1
Set power Down Bit =1 and put ENABLE to LOW level
2
Power on reset complete with next xtal cycle
Lock Transmit Bit. When the Power Down Mode is left, the lock transmit bit (LT) is set high. The power amplifier can not be switched on as
long as the bit is set to high.
9.3.2
State
ENABLE
LT
Description
Power Down Mode
↑
1
LT is set to High
All other states
↑
LT-1
LT is unchanged except the Supply
voltage drops down below the
threshold level
Active Edge of CLK
When the Power Down Mode is left, the level of CLK at the rising edge of ENABLE determines the active edge of CLK (CLK polarity). Once the
CLK polarity is set, it stays unchanged until the next Power Down Mode is re-entered.
9.3.3
State
ENABLE
CLK
Description
Power Down Mode
↑
0
DATAIO is sampled at the falling edge of CLK
Power Down Mode
↑
1
DATAIO is sampled at the rising edge of CLK
All other states
↑
X
CLK behavior is unchanged
Active State
The Active state is entered at the rising edge of ENABLE, which as well resets the Power Down timer. Possible previous states are Power Down
Mode, Transmit state. DATAIO is set to SDI data input and the Interface expects a command control byte to configure the state-machine. The
16
SDI state can be left by programming another state or by setting ENABLE low for more than 2 XTAL cycles (Power Down timer).
9.3.4
Transmit State
The state is entered upon command. The transmit command byte defines in combination with the configuration registers the transmit
configuration. The power amplifier (PA) will be activated on the subsequent sampling edge of CLK after receiving the command byte only if the
lock transmit bit has been reset (0) by a previous SDI command. Here (only here) the baud rate and data generator counters are reset, i.e. if
Transmit was interrupted by a SDI communication and is re-entered again (with active PA), the baud rate generator is kept synchronized with the
previous transmitted string. DATAIO is set to TX data input. If during transmit a low power reset (LPR) occurs, the lock transmit bit is set high and
hence the power amplifier is switched off.
The state can be left at the falling edge of ENABLE, or increasing the Supply Voltage above the threshold and setting the register bit (LT) to zero.
The control of the power amplifier is determined by the command byte (bit A4 and A5).
Table 20. PA Control Modes
State
LT
A4
A5
ENABLE
Description
All States
1
X
X
X
PAON low
Transmit
0
X
X
1
PAON high on the subsequent sampling edge of CLK after
receiving the command byte
Transmit
0
0
0
↓
PAON low at the falling edge of ENABLE
Transmit
0
0
1
↓
PAON low at the falling edge of ENABLE but synchronized with
baud rate, DATAIO is latched
Transmit
0
1
X
↓
PAON stays high, DATAIO is latched
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.4 ENABLE Signal Functionality
Figure 21 summarizes the function of ENABLE in combination with the SDI state and the logical level of CLK and DATAIO.
Table 21. ENABLE Signal Functionality
State
Power Down Mode
ENABLE
↑
CLK
DATAIO
Description
X
X
resets the SDI and state machine
activates the crystal oscillator (PD is set to low)
sets the lock transmit bit
0
X
indicates data are sampled at the falling edge of CLK
1
X
indicates data are sampled at the rising edge of CLK
X
0
activates MCCLK, fMCCLK=fXOSC/16
X
1
MCCLK configuration is unchanged
All
↑
X
X
resets the Power Down Timer
resets the SDI Interface
(re-)enters the Active state
Active, Transmit
↓
X
X
activates the Power Down Timer; after 2 crystal clock
cycles the IC reaches the Power Down Mode
X
X
Active, Transmit
16
indicates the end of Read/Write
16
(duration: min > 1 SDI CLK cycle, max: < 1/fcrystal * 2 )
All
0
X
X
disables CLK and DATAIO
sets DATAIO to high impedance
Transmit
↓
X
X
switches off the PA (if enabled)
latches DATAIO (if enabled)
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.5 Communication and Command Byte Structure
A frame consists of a command byte including address/configuration and a following bit stream that can either represent an integer number of
bytes or a random sequence of bits when the command is transmit. Command is encoded in the 2 first bits, while address is given on 6 bits. In
case if the command is neither read nor write, these bits are used to configure the transmission and they will be stored until the next
configuration.
The first byte of every SDI sequence is the command byte.
Function Code
C0
C1
Register Address or Transmission Configuration
A5
A4
A3
A2
A1
A0
The function code defines the command to be performed.
C0
C1
Command
0
0
Write data to register at address
0
1
Read data from register at address
1
0
Not defined
1
1
Transmit data. A0…A5 defines the transmit configuration:
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Bit
Function
Frequency
Selection
A2
Power level /
modulation type
selection
A3
Manchester coding
A4
PA mode
A5
Data
Synchronization
Revision 3.6
Value, Description
0 (00): selects frequency setting 1
1 (00): selects frequency setting 2
2 (10): selects frequency setting 3
3 (11): selects frequency setting 4
0: selects power level / modulation type 1
1: selects power level / modulation type 2
0: off
1: on
0: PA off at the falling edge of ENABLE (synchronized
with baud rate if A5 high)
1: DATAIO is latched at the falling edge of ENABLE
(i.e. TX data are kept constant, PA stays on)
0: off
1: on
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.6 Transmitter Configuration Register
All configuration registers are readable and writable. The registers are arranged as addressable bytes. The first byte (A) is addressed by 0,
the consecutive bytes (A, B, etc.) are addressed by 1,2, etc. The configuration register settings (except the registers with default
setting when entering or leaving the Power down mode), do not alter during Power down mode as long as the minimum supply requirements are
met.
Table 22. Configuration Registers
8
7
6
5
4
DIVR
ARSDRS
PLLON
FRAC1
INT1
D
INT2
F
INT3
FRAC3
0
BSEL
FRAC4
reserved
INT3
INT4
M
MCCDS
CLKS
reserved
N
ASC
reserved
LS
LT
MCCS
reserved
O
RPAOV2
FSK1
PREOP1
reserved
TCV
FSK2
PSC
reserved
LD
GFBP
reserved
TSON
PAOP2
PREOP2
PSC
ATCPH
TSRST
RPAOV1
SETPD
K
PAOP1
GFCS
reserved
DF
PREOP1
I
FRAC4
REGEN
G
L
1
FRAC2
FRAC3
J
2
FRAC1
E
H
3
reserved
9
CPSC
reserved
B
C
10
SD3
11
reserved ARSRST
12
PN9INT
A
13
reserved
14
CPSEC
15
TS
Default settings given are recommendations according to application note (not set at power up).
Table 23. Configuration Registers Description
Register
Name
Default Value
Description
Synthesizer section
A
SEL
application dependent
A
ARSRST
0
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Frequency band selection
0 (00): 315MHz frequency band
1 (01): 434 MHz and ARIB frequency band
2 (10): 868MHz frequency band
3 (11): 915MHz frequency band
Automatic range select reset, active high
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Table 23. Configuration Registers Description
Register
Name
Default Value
Description
A
ARSDRS
11
Automatic range select division ratio setting
0 (00): fREF/64
1 (01): fREF/128
2 (10): fREF/256
3 (11): fREF/512
A
DIVR
010
Reference divider division ratio setting must be set to
Binary 010
A
CPSEC
0
Charge pump sections setting
0: One section active
1: Two sections active
application dependent
Charge pump current setting
0 (00): 12.5 µA/Section
1 (01): 25.0 µA/Section
2 (10): 37.5 µA/Section
3 (11): 50.0 µA/Section
A
CPCS
00000
A
B
B
SD3
B
B
PN9INT
B
B
reserved Bits: set to Binary 00000 for normal mode of
operation
0
0: normal mode of operation
1: reserved for test purposes only
1
ΣΔ order selection
0: MASH2
1: MASH3
0
0: reserved Bit; set to zero
0
0: normal mode
1: reserved for test purposes only
0
0: normal mode
1: reserved for test purposes only
C
FRAC1
application dependent
Synthesizer fractional setting 1
C
INT1
application dependent
Synthesizer integer setting 1
C
PLLON
1
D
FRAC2
application dependent
Synthesizer fractional setting 2
E
INT2
application dependent
Synthesizer integer setting 2
E
FRAC3
application dependent
Synthesizer fractional setting 3
INT3
application dependent
Synthesizer integer setting 3
H
FRAC4
application dependent
Synthesizer fractional setting 4
H
INT4
application dependent
Synthesizer integer setting 4
F
F
G
G
H
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00
Revision 3.6
0: Phase locked loop off
1: Phase locked loop on
reserved Bits: set to Binary 00 for normal mode of
operation
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Table 23. Configuration Registers Description
Register
Name
Default Value
Description
Modulation and Power Amplifier section
I
GFCS
application dependent
Gaussian filter clock setting
I
DF
application dependent
FSK deviation setting
J
GFBP
0
Gaussian filter bypass
0: not bypassed
1: bypassed
J
REGEN
1
0: Turn off the VDD RF Regulator
1: Turn on the VDD RF Regulator
J
-
0000
J
reserved
0
J
ATCPH
J
RPAOV1
J
PAOP1
0000
11
reserved Bits: set to Binary 0000 for normal mode of
operation
reserved Bit should be set to 0
Antenna tuning circuit phase shift setting
0 (0000): minimum capacitor
:
:
15 (1111): maximum capacitor
PA voltage regulator setting 1
0 (00): VREG=1.7V
1 (01): VREG=1.8V
2 (10): VREG=1.9V
3 (11): VREG=2.0V
application dependent
Power amplifier power level setting 1
0 (00): maximum power
:
3 (11): minimum power
K
PREOP1
application dependent
Preamplifier power level setting 1
0 (00000): power off
1 (00001): minimum power
:
31 (11111): maximum power
K
FSK1
0
Modulation type selection 1
0: FSK
1: reserved for test purposes only
K
LT
0
Lock transmit, active=high
K
LS
0
Low power supply indicator, active=high
11
PA voltage regulator setting 2
0 (00): VREG=1.7V
1 (01): VREG=1.8V
2 (10): VREG=1.9V
3 (11): VREG=2.0V
J
K
K
RPAOV2
PAOP2
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application dependent
Revision 3.6
Power amplifier power level setting 2
0 (00): maximum power
:
3 (11): minimum power
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Table 23. Configuration Registers Description
Register
K
L
L
Name
Default Value
Description
application dependent
Preamplifier power level setting 2
0 (00000): power off
0 (00001): minimum power
:
31 (11111): maximum power
FSK2
0
Modulation type selection 2
0: FSK
1: reserved for test purposes only
-
0000000
PREOP2
reserved Bits: set to Binary 0000000 for normal mode
of operation
Baud Rate Generator, Data Generator and Digital Test Multiplexer section
L
MCCS
L
MCCDS
11
Micro controller clock output
0 (00): reserved
1 (01): reserved
2 (10): Micro controller clock is on during transmit
(MCCLK is output)
3 (11): Micro controller clock is always on (MCCLK is
output)
application dependent
Clock output driver driving strength setting
0 (000): 4mA (maximum) driving strength
…
7 (111): 1mA (minimum) driving strength
CLKS
application dependent
MCCLK source selection
0 (00): MCCLK connected to pre scaler output
1 (01): MCCLK connected to baud rate generator
output
2 (10): MCCLK connected to baud rate generator
output but inverted
3 (11): not used
PSC
application dependent
M
TCV
application dependent
M
ASC
application dependent
M
reserved
0010
N
TSON
0
0: Temperature sensor off
1: Temperature sensor on
N
TSNRST
1
Reset of temperature sensor, active=low
N
-
0000000
reserved Bits: set to Binary 0000000 for normal mode
of operation
0
Set power down, active=high (see Power On Reset on
page 22)
L
L
M
Micro controller clock pre scaler division ratio
-PSC
fOUT=2
*fIN
Baud rate generator counter value
Baud rate generator after scaler division ratio
-ASC
fOUT=2
*fIN
reserved Bits: set to Binary 0010 for normal mode of
operation
Temperature Sensor section
Power Down Control (see Power On Reset on page 22)
N
SETPD
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Table 23. Configuration Registers Description
Register
Name
Default Value
Description
N
-
0000000
reserved Bits: set to Binary 0000000 for normal mode
of operation
Temperature Sensor and Lock Detector Output (read only)
O
TS
-
Temperature sensor output
O
LD
-
Lock detector output
O
-
-
reserved
9.7 Special Bits
The following paragraphs provide a brief description of special bits used for Transmitter Interface functionality.
9.7.1
LT (Lock Transmit)
The Lock Transmit bit will be set each time the circuit goes in Power Down Mode. When the bit is set, the power amplifier of the AS3977 cannot
be activated. TX commands will be anyway accepted but without any “external” and visible effect.
A low has to be written before starting any RF-Transmission. The first write command can be responsible for a wake up event of the circuit and
to release Power Down Mode, which will lead to the inactive state. This signal will be activated whenever the power supply is dramatically under
the threshold for safe workings of analog circuits during transmit operations. If the supply voltage is under the threshold during transmit, the read
back value is “1” and this can indicate a non finished transmission.
9.7.2
LS (Low Power Supply Voltage)
Low power Supply voltage (LS) is a read/write bit, which indicates that the power amplifier supply voltage level (VCCPA) is below a certain
threshold voltage (see Table 13). After an increase of the power supply voltage above the threshold level (plus a hysteresis), this bit has to be
reset to zero via SPI. The bit condition has no influence on the operation of the IC. LS and LT monitor the VCCPA supply (they are only working
if Voltage is applied to VCCPA). As they are working with the same VREF generator that will be supplied from VCCPA, an overlap of the
threshold levels will never occur. LS is an indicator whereby LT switches off the PA hard coded.
9.7.3
MCCS, CLKS and PSC
These bits are used to set the micro controller clock functionality and to control the associated MCCLK bi-directional and multi-functional pad.
MCCS stands for Micro Controller Clock output Selection and it declares how the MCCLK pad will be used. Depending on the level of DATAIO by
leaving the Power Down Mode, this setting can be left unchanged from the last written value (DATAIO=1) or it can be set to the default value
(DATAIO=0). Default MCCS value is “11” then the MCCLK pad is used as output and the clock is always active.
CLKS stands for Clock Selection and it is used to select as MCCLK pre-scaler or baud rate output. Default value is the pre-scaler output.
PSC stands for Pre-scaler and it is the two’s exponent for first crystal oscillator division ratio. Default value is “100” that means a division ratio of
4
2 = 16.
By leaving the Power Down Mode and if DATAIO is sampled LOW, these bits are set to their default values and then as soon as the crystal
oscillator is on, the MCCLK will be active and with a frequency that is 1/16 of the crystal oscillator working frequency.
9.7.4
SETPD (Set Power Down)
This bit is used to force the circuit to go in Power Down Mode (see Software Power Down Method on page 26). When the circuit is in Power
Down Mode, this bit is reset to ZERO to avoid a dead lock condition. The Power Down Mode can be reached by writing a ONE to this bit
whenever a fast transition to the Power Down Mode is needed.
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.8 Output Frequency Setting
The output frequency fRF is given by:
f RF = P ⋅ f REF ⋅ ( M ⋅ N + AC + FRAC )
(EQ 3)
Where:
P
is the Predivider division ratio
fREF is the Reference frequency
M
is the Prescaler modulus
N
is the N-counter division ratio
AC is the A-counter offset, AC determines together with FRAC the actual A-counter setting
FRAC is the Fractional part
Predivider Division Ratio P and Pre Scaler Modulus M. The frequency band selection determines the value of the predivider division
ratio P and the setting of the pre scaler modulus M. The setting of these values for the different frequency bands is given in Table 24.
Table 24. P and M Values for Frequency Bands
Frequency Band
P
M
BSEL
Note
315 MHz
1
4
0 (00)
300 – 320 MHz
433 MHz
1
5
1 (01)
425 – 450 MHz
868 MHz
2
5
2 (10)
865 – 870 MHz
915 MHz
2
5
3 (11)
902 – 928 MHz
The reference frequency should be in the range of 3 to 5, 75 MHz and can be calculated by:
f XTAL
f REF = -----------------divider
(EQ 4)
f RF
- = DR INT + DR FRAC
DR = ----------------P ⋅ f REF
(EQ 5)
The recommended setting of the divider is 4.
The next step is to calculate the Division ratio:
This division ration can be split into a part before the comma, called integer part and a part after the comma, also called fractional part DRFRAC
The N-counter value of the Fractional N Synthesizer can be calculated with the formula:
( DR
– 3)
INT
N = whole numbered part of -----------------------------
M
(EQ 6)
The A-Counter is the rest of this Division and can be calculated by:
AC = ( DR INT – 3 ) – N × M
(EQ 7)
In case, the Value of the A-counter is zero, the value of the A-counter has to be increased by M and the value of N has to be decreased by one
AC = M
N=N-1
(EQ 8)
In case, the N-counter is in the range from 10 to 25 and the value of the A-counter is less than N-counter-7:
INT < 3 : 0 > = N - 10
INT < 7 : 4 > = AC - 1
(EQ 9)
Note: In case, no solution can be found for the wanted center frequency, it may help to modify the reference frequency or INT
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
9.8.1
Implementation
Starting from the equation,
f RF = P ⋅ f REF ⋅ ( M ⋅ N + AC + FRAC )
(EQ 10)
The equation now rewritten by taking configuration registers and implementation details into account:
(EQ 11)
f RF = P
⎛
⎛
⎜ (INT< 9 > +4 )(INT< 3:0 > + INT⋅6 +10 )+ INT< 7:4 > +1+ (INT +1)⎜ 3 +
DIVR < 2:0 > +2⎝
⎝
f XTAL
⎞⎞
⎟⎟
⎠⎠
FRAC < 15 : 0 >
16
2
Reference frequency fREF (DIVR)
The reference frequency fREF is determined by the crystal frequency fXTAL and the reference divider division ratio setting DIVR and can be
calculated with the help of:
(EQ 12)
f REF =
f XTAL
DIVR < 2 : 0 > +2
The value of fREF should be in the range of 3 MHz to 5, 75 MHz to achieve an optimum on noise performance and current consumption
f
f REF
9.8.1.1
XTAL
DIVR < 2:0 > = ------------ – 2
(EQ 13)
M = (INT < 9 > +4)
(EQ 14)
N = (INT < 3:0 > +INT < 8 > .6+10)
(EQ 15)
M-counter and Value of INT
The value of the M-counter is given by:
The Bit INT can be calculated as,
INT < 9 > = M - 4
9.8.1.2
N-counter and Value of INT
Taken the default value of INT=0 into account, the value of the INT3 can be calculated by:
INT < 3:0 > = N-10
9.8.1.3
A- Counter and Value of INT
AC = INT < 7:4 > +1 +(INT +1) x 3
(EQ 16)
Taken the default value of INT=0 into account, the value of the INT can be calculated by:
INT < 7:4 > = AC-1
9.8.1.4
Fractional Part and Values of FRAC
(EQ 17)
DRFRAC =
(INT +1 ) ⎜⎛ FRAC ⎟⎞
⎝
⎠
2
16
Taken the default value of INT=0 into account, multiplying the Fractional part with 2 gives the register values for the Fractional and
synthesizer value and can be calculated by:
16
FRAC < 15:0 >= DRFRAC x 2
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Example:
Wanted frequency 425 MHz by 16 MHz crystal frequency.
The values of P and M can be taken from table
P=1→ Defined with the BSEL Bit’s BSEL= Hex “2”
M=5 → INT= 5-4 = 1
The Setting of DIVR = 2 results in a reference frequency divider of 4.
The Division ratio will now be:
f RF
433, 92
- = --------------------R = 108, 48 = DR INT + DR FRAC
DR = ----------------P ⋅ f REF
1.4
(EQ 18)
And can be split into the values:
( DR
– 3)
( 108 – 3 )
5
INT
N = whole numbered part of ----------------------------- = ---------------------- = 21
M
(EQ 19)
As the Rest is zero, we have to set AC=M and N to decrease by one.
N=20
INT < 3:0 >= N-10 = 20-10=10 = Hex „A“
AC=5
INT < 7:4 >= AC-1= 5-1=4 Hex „4“
16
FRAC < 15:0 >= DRFRAC x 2 = 0,48 x 65536 = 31457 =Hex “7AE1”
9.8.2
Optional Frequency Calculation with Overlapping Fractional Bands by Using the Bit INT
Bit INT. The bit INT is a multiplier to the output of the ΣΔ-modulator. Set this Bit to high stretches the fractional-N region by two and
results in overlapping frequency bands with a bandwidth of 2*fREF and an overlap ratio of 50% in order to allow frequency modulation and/or
frequency trimming independently on the required output frequency and selected crystal. Note that setting INT high increases the PLL inband noise by approximately 3dB. Therefore it is recommended to use this option only if the required frequency band did not fit to the crystal
reference.
INT=N-2
INT=N
INT=N-1
INT=N+1
Frequency Band
INT8=1
FRAC
FRAC
INT8=0
FRAC
FRAC
FRAC
FRAC
FRAC
FRAC
FRAC
FRAC
FRAC
FRAC
Modulation on the Integer border with
INT = 0 not possible
Modulation on the Integer border with
INT = 1 not possible
Steps for INT=1
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Calculate the Division ratio
f RF
- = DR INT + DR FRAC
DR = ----------------P ⋅ f REF
(EQ 20)
1. If the fractional part is larger than 0.5
FRAC = DR FRAC ⋅ 2
( DR
15
– 6)
INT
N= whole numbered part of -----------------------------
(EQ 21)
M
The A-Counter is the rest of the Division and can be calculated by:
AC = ( DR INT – 6 ) – N × M
(EQ 22)
2. If the fractional part is less than 0.5
FRAC = ( DR FRAC + 1 ) ⋅ 2
15
–7
DR
INT
N = whole numbered part of ------------------------
(EQ 23)
M
The A-Counter is the rest of the Division and can be calculated by:
AC = (DRINT - 7) - N x M
(EQ 24)
In case, the value of the A-counter is zero, the value of the A-counter has to be increased by M and the value of N has to be decreased by one
AC = AC + M
N=N-1
(EQ 25)
In case, the N-counter is in the range from 16 to 31 and the value of the A-counter is less than N-counter-14:
INT = N - 16
INT = AC - 1
(EQ 26)
Note: In case, no solution can be found for the wanted center frequency, it may help to modify the reference frequency or INT.
9.8.3
FSK Deviation Setting and Frequency Trimming
The frequency resolution Δf is determined by the reference frequency fREF, the selected frequency band and the setting of INT and can be
calculated with following equation:
f REF
Δf = P ⋅ ( INT + 1 ) ⋅ --------16
(EQ 27)
2
9.8.3.1
FSK Deviation Setting
The FSK deviation DF is given by the frequency resolution Δf and the setting of DF and can be calculated with the help of:
DF = Δf ⋅ DF . DM
(EQ 28)
The deviation multiplier DM is determined by the setting of DF according to the following table:
DF
DM
0 (00)
1
1 (01)
2
2 (10)
4
3 (11)
16
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Frequency Trimming. Frequency trimming (e.g. in case a characterized crystal is used) can be done with the help of the (nominal) frequency
resolution Δf and without recalculating all the frequency settings. If the crystal error is known, the resulting error ε RF in the output frequency is
ε
Δf
ε
Δf
RF
RF
also known. The ratio ----------- can then be used to correct the error. In case the crystal error is positive, ----------- has to be subtracted from, in case
the crystal error is negative it has to be added to FRAC.
A similar procedure can be performed to calibrate for initial frequency errors. Note that in both cases the resulting value for FRAC has to
fulfil the conditions FRAC - DF ≥ 0Η and FRAC + DF ≤ FFFFH.
9.8.3.2
Gaussian Filter Clock Setting
The setting of GFCS determines the clock frequency fGF of the Gaussian filter according to
(EQ 29)
fGF =
f REF
GFCS< 7 : 0 > +1
Ideally, fGF should be set to be 30*fMod (fMod …modulation frequency).
9.9 Baud Rate Generator
The main functionality of the module is to generate clocks with programmed periods. The first action is to change the parameters followed by
starting a transmission.
Changing PSC, TCV, ASC and CLKS parameters
As soon as the crystal oscillator clock is active, pre scaler and after scaler timer configuration parameters are continuously updated from the
SDI registers. To avoid spurious emissions, these synchronized values cannot be immediately used for new clock generation because the
circuit has to take care about current and new clock phase difference. Then, as soon as the phase difference between them is zero, an
enable signal is generated and new values are stored to the final registers that will be used for the normal functionality of the circuit. At this
point the new clock will start without spurious periods.
Starting a transmission
A typical situation is as follows – After start up and configuration, the circuit goes in Power Down Mode. Then a wake up event occurs on the
SDI interface and the internal crystal oscillator starts running (after a setup time). The wake up event is typically a rising edge on the SDI
enable input that samples the SDI data e.g. to the LOW value and this resets the MCCLK frequency to be 1/16 of the oscillator frequency
and makes the clock always active. At this point the micro-controller starts its activity and it can decide to reprogram MCCLK frequency to
the desired value and to the desired behavior. The decision between current and new value will be done synchronously to eliminate any
possible spurious period on MCCLK (mainly if it is used). In any case it can be maintained the new setting between different Power Down
Modes or it can be reset to the default value on the first access to the SDI interface when the circuit is in Power Down Mode.
9.10 Reference Design PREOUT and PAOUT Connection
For all RF Specification, refer to the Reference Design. The PAOUT pin is Power Line matched to 50Ω load wherein a power of
8dBm@315MHz/433MHz and 4dBm@868MHz/915MHz is spent typically.
9.10.1 Matching Circuit and PREOUT and PAOUT Connections to the Supply Voltage
Figure 13 shows the Power Line Matching and Transformation Network used on the Reference Design. Table 25 gives the values for several
settings, varying the operation frequency and the Supply Voltage source. Supply blocking capacitors are not shown in the schematic (see Figure
13).
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 13. Schematic
n.m.
L2
Supply
Voltage
AS3977
C3
2
PREOUT
1
C1
C2
PAOUT
Π Matching Network
to 50Ω
L1
SMA
Connector
Into 50Ω
L4
Table 25. Part List of the Reference Design Components
Supply voltage 2V regulated
Source is VREGRF (pin 16)
315 MHz
Supply voltage 3V
Source is Power Supply
315 MHz
Compone
nt
Value
Murata-LQW18AN47NG00
L4
43 nH
Murata-LQW18AN43NG00
62 nH
Murata-LQW18AN62NG00
L2
62 nH
Murata-LQW18AN62NG00
C3
10 pF
Murata-GRM1885C1H100JA01
C3
100 pF
Murata-GRM1885C1H101JA01
C2
2.7 pF
Murata-GRM1885C1H2R7CZ01
C2
3.3 pF
Murata-GRM1885C1H3R3CZ01
L1
56 nH
Murata-LQW18AN56NG00
L1
82 nH
Murata-LQW18AN82NG00
C1
0.5 pF
Murata-GRM1885C1HR50CZ01
C1
4.7 pF
Murata-GRM1885C1H4R7CZ01
Component
Value
L4
47 nH
L2
Type
433 MHz
Type
433 MHz
L4
24 nH
Murata-LQW18AN24NG00
L4
24 nH
Murata-LQW18AN24NG00
L2
33 nH
Murata-LQW18AN33NG00
L2
33 nH
Murata-LQW18AN33NG00
C3
10 pF
Murata-GRM1885C1H100JA01
C3
100 pF
Murata-GRM1885C1H101JA01
C2
2.2 pF
Murata-GRM1885C1H2R2CZ01
C2
3.9 pF
Murata-GRM1885C1H3R9CZ01
L1
43 nH
Murata-LQW18AN43NG00
L1
43 nH
Murata-LQW18AN43NG00
C1
2.7 pF
Murata-GRM1885C1H2R7CZ01
C1
6.8 pF
Murata-GRM1885C1H6R8CZ01
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AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Table 25. Part List of the Reference Design Components
Supply voltage 2V regulated
Source is VREGRF (pin 16)
868/915 MHz
Supply voltage 3V
Source is Power Supply
868/915 MHz
L4
8.2 nH
Toko-LL1608-FS
L4
8.2 nH
Toko-LL1608-FS
L2
8.2 nH
Toko-LL1608-FS
L2
8.2 nH
Toko-LL1608-FS
C3
10 pF
Murata-GRM1885C1H100JA01
C3
10 pF
Murata-GRM1885C1H100JA01
C2
1.0 pF
Murata-GRM1885C1H1R0CZ01
C2
1.0 pF
Murata-GRM1885C1H1R0CZ01
L1
10 nH
Murata-LQW18AN10NG00
L1
10 nH
Murata-LQW18AN10NG00
C1
2.2 pF
Murata-GRM1885C1H2R2CZ01
C1
2.2 pF
Murata-GRM1885C1H2R2CZ01
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AS3977
Data Sheet - M e a s u r e m e n t R e s u l t s
10 Measurement Results
Figure 14. Output spectrum with 7.5MHz span, Frequency=433.92MHz, POUT=8dBm (0.3dBm added due to cable attenuation),
Span=7.5MHz
Figure 15. Phase-noise: - 88.5dBc, POUT=8dBm
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AS3977
Data Sheet - M e a s u r e m e n t R e s u l t s
Figure 16. Modulated signal with bypass gaussian filter, Freq Mod: 5kHz, Deviation: 10kHz
Figure 17. Modulated signal with gaussian filter, Freq Mod: 5kHz, Deviation: 10kHz
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AS3977
Data Sheet - M e a s u r e m e n t R e s u l t s
Figure 18. Occupied bandwidth with bypass gaussian filter, Occupied bandwidth: 49.7kHz, Freq Mod: 5kHz, Deviation: 10kHz
Figure 19. Occupied bandwidth with gaussian filter, Occupied bandwidth: 30kHz, Freq Mod: 5kHz, Deviation: 10kHz
10.0.1 Applicable Radio Standards
ARIB STD-T67 (Telemeter, Telecontrol and Data-Transmission Radio Equipment)
ETSI EN 300 220
FCC CFR 47 Part 15
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AS3977
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
11 Package Drawings and Markings
The device is available in a 16-Lead QFN (4x4mm) package.
Figure 20. Package Drawings
Top View
Bottom View
2,30
2,50
PIN 1 in dicator
PIN 1 in dicator
4,0
14
13
15
16
12
QFN
QFN16
16
(44 xX 44 mm)
mm
4,0
2,30
2,50
Top View
1
2
11
0,65
BSC
3
10
4
9
8
7
6
5
0,25
0,35
0,40
0,60
Side View
0,75
0,95
Land pattern recommendation for JEDEC MO-220 VGGC
V1
C1
X2
16
15
14
16
13
15
14
13
E
12
1
11
2
3
10
3
10
4
9
4
9
1
Y2
C
2
C2 Y2
Exposed paddle
5
6
X1
7
12
11
Exposed paddle
5
8
6
7
V2
8
Y1
Table 26. Package Dimensions
Symbol
mm
Pitch E
0.65
Pad X1
0.35
Pad Y1
0.9
Pad Space C1
3.9
Pad space C2
3.9
Tab pad X2
2.4
Tab pad Y2
2.4
Courtyard V1
5.3
Courtyard V2
5.3
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AS3977
Data Sheet - R e v i s i o n H i s t o r y
Revision History
Revision
Date
3.4
Apr 01, 2008
3.5
Dec 15, 2008
3.6
Apr 16, 2010
Owner
kfr/tjs
Description
Added block diagram Operation Mode Relations (page 20)
Updated Ordering Information (page 46)
Updated Ordering Information (page 46)
Note: Typos may not be explicitly mentioned under revision history.
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AS3977
Data Sheet - O r d e r i n g I n f o r m a t i o n
12 Ordering Information
The devices are available as the standard products shown in Table 27.
Table 27. Ordering Information
Device ID
AS3977-TPD
Part Number
Description
1
Delivery Form
Package
AS3977B-BQFS
Tray
QFN16 4x4
AS3977B-BQFT
Tape and Reel
QFN16 4x4
1. Dry Pack sensitivity Level =3 according IPC/JEDEC J-STD-033A.
Where:
T=Temperature range:
B=-40…85 degree
P=Package Type:
QF=QFN
D=Delivery Form
S=Tray in DryPack
T=Tape and Reel
Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS3977
Data Sheet - C o p y r i g h t s
Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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