74LVC2T45GT-Q100X

74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Rev. 3 — 28 January 2019 Product data sheet 1. General description The 74LVC2T45-Q100; 74LVCH2T45-Q100 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two 2-bits input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH2T45-Q100 holds unused or floating data inputs at a valid logic level. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range: • VCC(A): 1.2 V to 5.5 V • VCC(B): 1.2 V to 5.5 V High noise immunity Complies with JEDEC standards: • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) ESD protection: • MIL-STD-883, method 3015 Class 3A exceeds 4000 V • HBM JESD22-A114F Class 3A exceeds 4000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Maximum data rates: • 420 Mbps (3.3 V to 5.0 V translation) • 210 Mbps (translate to 3.3 V)) • 140 Mbps (translate to 2.5 V) • 75 Mbps (translate to 1.8 V) • 60 Mbps (translate to 1.5 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II ±24 mA output drive (VCC = 3.0 V) Inputs accept voltages up to 5.5 V Low power consumption: 16 μA maximum ICC Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state • IOFF circuitry provides partial Power-down mode operation 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC2T45GT-Q100 -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74LVC2T45GS-Q100 -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 74LVC2T45DC-Q100 74LVCH2T45DC-Q100 4. Marking Table 2. Marking Type number Marking code [1] 74LVC2T45DC-Q100 V45 74LVCH2T45DC-Q100 X45 74LVC2T45GT-Q100 V45 74LVC2T45GS-Q100 V5 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram DIR 1A 5 DIR 2 1A 7 2A 1B 1B 3 2A 6 VCC(A) 2B 2B VCC(B) VCC(A) 001aag577 Fig. 1. Logic symbol 74LVC_LVCH2T45_Q100 Product data sheet VCC(B) 001aag578 Fig. 2. Logic diagram All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 2 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 6. Pinning information 6.1. Pinning 74LVC2T45 74LVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 74LVC2T45 74LVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 2A 3 6 2B GND 4 5 DIR 001aai905 Transparent top view 001aai904 Fig. 3. Pin configuration SOT765-1 (VSSOP8) Fig. 4. Pin configuration SOT833-1 and SOT1203 (XSON8) 6.2. Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage A (port A and DIR) 1A 2 data input or output 2A 3 data input or output GND 4 ground (0 V) DIR 5 direction control 2B 6 data input or output 1B 7 data input or output VCC(B) 8 supply voltage B (port B) 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input Input/output [1] VCC(A), VCC(B) DIR nA nB 1.2 V to 5.5 V L nA = nB input 1.2 V to 5.5 V H input nB = nA GND [2] X Z Z [1] [2] The input circuit of the data I/O is always active. When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 3 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC(A) supply voltage A -0.5 +6.5 V VCC(B) supply voltage B -0.5 +6.5 V IIK input clamping current VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode VI < 0 V [1] -50 - -0.5 +6.5 -50 - [1][2][3] -0.5 Suspend or 3-state mode [1] -0.5 [2] mA V mA VCCO + 0.5 V +6.5 V - ±50 mA - 100 mA IO output current VO = 0 V to VCCO ICC supply current ICC(A) or ICC(B) IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] [3] [4] Tamb = -40 °C to +125 °C [4] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 6.5 V. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC(A) supply voltage A 1.2 5.5 V VCC(B) supply voltage B 1.2 5.5 V VI input voltage 0 5.5 V VO output voltage 0 VCCO V 0 5.5 V -40 +125 °C - 20 ns/V VCCI = 1.4 V to 1.95 V - 20 ns/V VCCI = 2.3 V to 2.7 V - 20 ns/V VCCI = 3 V to 3.6 V - 10 ns/V VCCI = 4.5 V to 5.5 V - 5 ns/V Active mode [1] Suspend or 3-state mode Tamb ambient temperature Δt/ΔV input transition rise and fall rate [1] [2] VCCI = 1.2 V [2] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 4 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 10. Static characteristics Table 7. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max VOH HIGH-level output voltage VI = VIH or VIL; IO = -3 mA; VCCO = 1.2 V VOL LOW-level output voltage II Unit [1] - 1.09 - V VI = VIH or VIL; IO = 3 mA; VCCO = 1.2 V [1] - 0.07 - V input leakage current DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V [2] - - ±1 μA IBHL bus hold LOW current A or B port; VI = 0.42 V; VCCI = 1.2 V [2] - 19 - μA IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCCI = 1.2 V [2] - -19 - μA IBHLO bus hold LOW overdrive current A or B port; VCCI = 1.2 V [2][3] - 19 - μA IBHHO bus hold HIGH overdrive current A or B port; VCCI = 1.2 V [2][3] - -19 - μA IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [1] - - ±1 μA IOFF power-off leakage current A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V - - ±1 μA B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - - ±1 μA CI input capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V - 2.2 - pF CI/O input/output capacitance A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V - 6.0 - pF [1] [2] [3] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH. Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VIH data input HIGH-level input voltage -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCCI = 1.2 V 0.8VCCI - 0.8VCCI - V VCCI = 1.4 V to 1.95 V 0.65VCCI - 0.65VCCI - V VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V VCCI = 4.5 V to 5.5 V 0.7VCCI - 0.7VCCI - V VCCI = 1.2 V 0.8VCC(A) - 0.8VCC(A) - V VCCI = 1.4 V to 1.95 V 0.65VCC(A) - 0.65VCC(A) - V VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V VCCI = 4.5 V to 5.5 V 0.7VCC(A) - 0.7VCC(A) - V [1] DIR input 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 5 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Symbol Parameter Conditions -40 °C to +85 °C Min VIL LOW-level input data input voltage VCCI = 1.2 V -40 °C to +125 °C Max Min Unit Max [1] - 0.2VCCI - 0.2VCCI V VCCI = 1.4 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCI = 4.5 V to 5.5 V - 0.3VCCI - 0.3VCCI V VCCI = 1.2 V - 0.2VCC(A) - 0.2VCC(A) V VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V VCCI = 4.5 V to 5.5 V - 0.3VCC(A) - - VCCO - 0.1 - V DIR input VOH VOL HIGH-level output voltage LOW-level output voltage IO = -100 μA; VCCO = 1.2 V to 4.5 V [2] VCCO - 0.1 IO = -6 mA; VCCO = 1.4 V 1.0 - 1.0 - V IO = -8 mA; VCCO = 1.65 V 1.2 - 1.2 - V IO = -12 mA; VCCO = 2.3 V 1.9 - 1.9 - V IO = -24 mA; VCCO = 3.0 V 2.4 - 2.4 - V IO = -32 mA; VCCO = 4.5 V 3.8 - 3.8 - V IO = 100 μA; VCCO = 1.2 V to 4.5 V - 0.1 - 0.1 V IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V - ±2 - ±10 μA VI = 0.49 V; VCCI = 1.4 V 15 - 10 - μA VI = 0.58 V; VCCI = 1.65 V 25 - 20 - μA VI = 0.70 V; VCCI = 2.3 V 45 - 45 - μA VI = 0.80 V; VCCI = 3.0 V 100 - 80 - μA 100 - 100 - μA VI = 0.91 V; VCCI = 1.4 V -15 - -10 - μA VI = 1.07 V; VCCI = 1.65 V -25 - -20 - μA VI = 1.60 V; VCCI = 2.3 V -45 - -45 - μA VI = 2.00 V; VCCI = 3.0 V -100 - -80 - μA VI = 3.15 V; VCCI = 4.5 V -100 - -100 - μA VI = VIL [2] II input leakage current DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V IBHL bus hold LOW current A or B port [1] VI = 1.35 V; VCCI = 4.5 V IBHH bus hold HIGH current 74LVC_LVCH2T45_Q100 Product data sheet 0.3VCC(A) V VI = VIH A or B port [1] All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 6 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Symbol Parameter IBHLO IBHHO bus hold LOW overdrive current bus hold HIGH overdrive current Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCCI = 1.6 V 125 - 125 - μA VCCI = 1.95 V 200 - 200 - μA VCCI = 2.7 V 300 - 300 - μA VCCI = 3.6 V 500 - 500 - μA VCCI = 5.5 V 900 - 900 - μA VCCI = 1.6 V -125 - -125 - μA VCCI = 1.95 V -200 - -200 - μA VCCI = 2.7 V -300 - -300 - μA VCCI = 3.6 V -500 - -500 - μA -900 - -900 - μA - ±2 - ±10 μA A or B port [1][3] A or B port [1][3] VCCI = 5.5 V IOZ OFF-state output current IOFF A port; VI or VO = 0 V to 5.5 V; power-off leakage current VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V - ±2 - ±10 μA B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V - ±2 - ±10 μA VCC(A), VCC(B) = 1.2 V to 5.5 V - 8 - 8 μA VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 μA VCC(A) = 5.5 V; VCC(B) = 0 V - 2 - 2 μA VCC(A) = 0 V; VCC(B) = 5.5 V -2 - -2 - μA - 8 - 8 μA VCC(A), VCC(B) = 1.65 V to 5.5 V - 3 - 3 μA VCC(B) = 0 V; VCC(A) = 5.5 V -2 - -2 - μA VCC(B) = 5.5 V; VCC(A) = 0 V - 2 - 2 μA VCC(A), VCC(B) = 1.2 V to 5.5 V - 16 - 16 μA VCC(A), VCC(B) = 1.65 V to 5.5 V - 4 - 4 μA - 50 - 75 μA - 50 - 75 μA - 50 - 75 μA ICC supply current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V A port; VI = 0 V or VCCI; IO = 0 A [2] [1] B port; VI = 0 V or VCCI; IO = 0 A VCC(A), VCC(B) = 1.2 V to 5.5 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI ΔICC additional supply current per input; VCC(A), VCC(B) = 3.0 V to 5.5 V A port; A port at VCC(A) - 0.6 V; DIR at VCC(A); B port = open [4] DIR input; DIR at VCC(A) - 0.6 V; A port at VCC(A) or GND; B port = open B port; B port at VCC(B) - 0.6 V; DIR at GND; A port = open [1] [2] [3] [4] [4] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH. For non bus hold parts only (74LVC2T45-Q100). 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 7 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 11. Dynamic characteristics Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. Symbol Parameter Conditions VCC(B) Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V tPLH LOW to HIGH propagation delay A to B 10.6 8.1 7.0 5.8 5.3 5.1 ns B to A 10.6 9.5 9.0 8.5 8.3 8.2 ns tPHL HIGH to LOW propagation delay A to B 10.1 7.1 6.0 5.3 5.2 5.4 ns B to A 10.1 8.6 8.1 7.8 7.6 7.6 ns HIGH to OFF-state propagation delay DIR to A 9.4 9.4 9.4 9.4 9.4 9.4 ns DIR to B 12.0 9.4 9.0 7.8 8.4 7.9 ns LOW to OFF-state propagation delay DIR to A 7.1 7.1 7.1 7.1 7.1 7.1 ns DIR to B 9.5 7.8 7.7 6.9 7.6 7.0 ns OFF-state to HIGH propagation delay DIR to A [1] 20.1 17.3 16.7 15.4 15.9 15.2 ns DIR to B [1] 17.7 15.2 14.1 12.9 12.4 12.2 ns OFF-state to LOW propagation delay DIR to A [1] 22.1 18.0 17.1 15.6 16.0 15.5 ns DIR to B [1] 19.5 16.5 15.4 14.7 14.6 14.8 ns tPHZ tPLZ tPZH tPZL [1] tPZH and tPZL are calculated values using the formula shown in Section 13.4. Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. Symbol Parameter Conditions VCC(A) Unit 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V LOW to HIGH propagation delay A to B 10.6 9.5 9.0 8.5 8.3 8.2 ns B to A 10.6 8.1 7.0 5.8 5.3 5.1 ns tPHL HIGH to LOW propagation delay A to B 10.1 8.6 8.1 7.8 7.6 7.6 ns B to A 10.1 7.1 6.0 5.3 5.2 5.4 ns tPHZ HIGH to OFF-state propagation delay DIR to A 9.4 6.5 5.7 4.1 4.1 3.0 ns DIR to B 12.0 6.1 5.4 4.6 4.3 4.0 ns LOW to OFF-state propagation delay DIR to A 7.1 4.9 4.5 3.2 3.4 2.5 ns DIR to B 9.5 7.3 6.6 5.9 5.7 5.6 ns OFF-state to HIGH propagation delay DIR to A [1] 20.1 15.4 13.6 11.7 11.0 10.7 ns DIR to B [1] 17.7 14.4 13.5 11.7 11.7 10.7 ns OFF-state to LOW propagation delay DIR to A [1] 22.1 13.2 11.4 9.9 9.5 9.4 ns DIR to B [1] 19.5 15.1 13.8 11.9 11.7 10.6 ns tPLH tPLZ tPZH tPZL [1] tPZH and tPZL are calculated values using the formula shown in Section 13.4. 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 8 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 1.8 V 2.5 V 3.3 V 5.0 V CPD A port: (direction A to B); B port: (direction B to A) 2 3 3 4 pF A port: (direction A to B); B port: (direction B to A) 15 16 16 18 pF [1] [2] power dissipation capacitance[1] [2] VCC(A) and VCC(B) Unit CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.4 V to 1.6 V tPLH LOW to HIGH propagation delay A to B 2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns B to A 2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns tPHL HIGH to LOW propagation delay A to B 2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns B to A 2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 ns HIGH to OFF-state propagation delay DIR to A 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns DIR to B 3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns LOW to OFF-state propagation delay DIR to A 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns DIR to B 2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 9.4 OFF-state to HIGH propagation delay DIR to A [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns DIR to B [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns OFF-state to LOW propagation delay DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns DIR to B [1] - 38.0 - 34.0 - 30.5 - 29.6 - 29.5 ns tPHZ tPLZ tPZH tPZL 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © ns Nexperia B.V. 2019. All rights reserved 9 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.65 V to 1.95 V LOW to HIGH propagation delay A to B 2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 B to A 2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns HIGH to LOW propagation delay A to B 2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 B to A 2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns HIGH to OFF-state propagation delay DIR to A 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 ns DIR to B 3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5 8.2 LOW to OFF-state propagation delay DIR to A 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 ns DIR to B 2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 7.1 tPZH OFF-state to HIGH propagation delay DIR to A [1] - 35.2 - 33.7 - 25.2 - 23.9 - 22.2 ns DIR to B [1] - 29.6 - 28.2 - 19.8 - 17.7 - 17.3 ns tPZL OFF-state to LOW propagation delay DIR to A [1] - 39.4 - 36.2 - 24.4 - 22.9 - 20.4 ns DIR to B [1] - 34.4 - 31.4 - 25.6 - 24.2 - 24.1 ns 16.0 1.5 8.5 1.3 6.2 1.1 4.8 ns tPLH tPHL tPHZ tPLZ ns ns ns ns VCC(A) = 2.3 V to 2.7 V tPLH LOW to HIGH propagation delay A to B 2.3 17.9 2.3 B to A 2.0 13.5 2.2 9.3 1.5 8.5 1.4 8.0 1.0 7.5 ns tPHL HIGH to LOW propagation delay A to B 2.3 15.8 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 ns B to A 1.8 11.8 1.9 8.5 1.4 7.5 1.3 7.0 0.9 6.2 ns HIGH to OFF-state propagation delay DIR to A 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 ns DIR to B 3.0 22.5 3.0 21.4 2.5 11.0 2.8 9.3 2.3 6.9 ns LOW to OFF-state propagation delay DIR to A 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 ns DIR to B 2.3 14.6 2.5 13.2 2.0 9.0 2.5 8.4 1.8 5.8 ns OFF-state to HIGH propagation delay DIR to A [1] - 28.1 - 22.5 - 17.5 - 16.4 - 13.3 ns DIR to B [1] - 23.7 - 21.8 - 14.3 - 12.0 - 10.6 ns OFF-state to LOW propagation delay DIR to A [1] - 34.3 - 29.9 - 18.5 - 16.3 - 13.1 ns DIR to B [1] - 23.9 - 21.0 - 15.6 - 13.5 - 12.7 ns tPHZ tPLZ tPZH tPZL VCC(A) = 3.0 V to 3.6 V LOW to HIGH propagation delay A to B 2.3 17.1 2.1 15.5 1.4 8.0 0.8 5.6 0.7 4.4 ns B to A 1.7 11.8 1.7 7.2 1.3 6.2 0.7 5.6 0.6 5.4 ns tPHL HIGH to LOW propagation delay A to B 2.2 15.6 2.0 12.6 1.3 7.0 0.8 5.0 0.7 4.0 ns B to A 1.7 10.9 1.8 7.1 1.3 5.4 0.8 5.0 0.7 4.5 ns tPHZ HIGH to OFF-state propagation delay DIR to A 2.3 7.3 2.3 7.3 2.3 7.3 2.3 7.3 2.7 7.3 ns DIR to B 2.9 18.0 2.9 16.5 2.3 10.1 2.7 8.6 2.2 6.3 ns LOW to OFF-state propagation delay DIR to A 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 ns DIR to B 2.3 13.6 2.4 12.5 1.9 7.8 2.3 7.1 1.7 4.9 ns OFF-state to HIGH propagation delay DIR to A [1] - 25.4 - 19.7 - 14.0 - 12.7 - 10.3 ns DIR to B [1] - 22.7 - 21.1 - 13.6 - 11.2 - 10.0 ns OFF-state to LOW propagation delay DIR to A [1] - 28.9 - 23.6 - 15.5 - 13.6 - 10.8 ns DIR to B [1] - 22.9 - 19.9 - 14.3 - 12.3 - 11.3 ns tPLH tPLZ tPZH tPZL 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 10 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 4.5 V to 5.5 V LOW to HIGH propagation delay A to B 2.2 16.6 1.9 15.1 1.0 7.5 0.7 5.4 0.5 3.9 ns B to A 1.6 10.5 1.4 6.8 1.0 4.8 0.7 4.4 0.5 3.9 ns HIGH to LOW propagation delay A to B 2.3 15.3 1.8 12.2 1.0 6.2 0.7 4.5 0.5 3.5 ns B to A 1.7 10.8 1.7 7.0 0.9 4.6 0.7 4.0 0.5 3.5 ns HIGH to OFF-state propagation delay DIR to A 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 ns DIR to B 2.9 17.3 2.9 16.1 2.3 9.7 2.7 8.0 2.5 5.7 ns LOW to OFF-state propagation delay DIR to A 1.4 3.7 1.4 3.7 1.3 3.7 1.0 3.7 0.9 3.7 ns DIR to B 2.3 13.1 2.4 12.1 1.9 7.4 2.3 7.0 1.8 4.5 ns tPZH OFF-state to HIGH propagation delay DIR to A [1] - 23.6 - 18.9 - 12.2 - 11.4 - 8.4 ns DIR to B [1] - 20.3 - 18.8 - 11.2 - 9.1 - 7.6 ns tPZL OFF-state to LOW propagation delay DIR to A [1] - 28.1 - 23.1 - 14.3 - 12.0 - 9.2 ns DIR to B [1] - 20.7 - 17.6 - 11.6 - 9.9 - 8.9 ns tPLH tPHL tPHZ tPLZ [1] tPZH and tPZL are calculated values using the formula shown in Section 13.4. Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6. Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.4 V to 1.6 V LOW to HIGH propagation delay A to B 2.5 23.5 2.1 19.4 1.8 14.9 1.5 13.0 1.4 11.6 ns B to A 2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns tPHL HIGH to LOW propagation delay A to B 2.3 21.3 1.9 16.9 1.6 13.0 1.5 12.0 1.5 11.9 ns B to A 2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns tPHZ HIGH to OFF-state propagation delay DIR to A 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 ns DIR to B 3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 ns LOW to OFF-state propagation delay DIR to A 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 ns DIR to B 2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns OFF-state to HIGH propagation delay DIR to A [1] - 43.7 - 40.1 - 26.8 - 24.9 - 23.6 ns DIR to B [1] - 36.1 - 32.0 - 27.5 - 25.6 - 24.2 ns OFF-state to LOW propagation delay DIR to A [1] - 48.6 - 45.1 - 26.7 - 25.0 - 23.5 ns DIR to B [1] - 41.9 - 37.5 - 33.6 - 32.6 - 32.5 ns tPLH tPLZ tPZH tPZL 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 11 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.65 V to 1.95 V LOW to HIGH propagation delay A to B 2.3 21.1 1.9 19.5 1.9 10.3 1.5 8.0 1.2 7.5 B to A 2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns HIGH to LOW propagation delay A to B 2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 B to A 1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns HIGH to OFF-state propagation delay DIR to A 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 ns DIR to B 2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2 9.1 LOW to OFF-state propagation delay DIR to A 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 ns DIR to B 2.2 19.4 2.3 17.6 1.9 10.2 2.4 9.3 2.1 7.9 tPZH OFF-state to HIGH propagation delay DIR to A [1] - 38.8 - 37.1 - 27.8 - 26.4 - 24.6 ns DIR to B [1] - 32.7 - 31.1 - 21.9 - 19.6 - 19.1 ns tPZL OFF-state to LOW propagation delay DIR to A [1] - 43.5 - 39.9 - 26.9 - 25.3 - 22.6 ns DIR to B [1] - 38.0 - 34.7 - 28.3 - 26.8 - 26.6 ns tPLH tPHL tPHZ tPLZ ns ns ns ns VCC(A) = 2.3 V to 2.7 V tPLH LOW to HIGH propagation delay A to B 2.0 19.7 2.0 17.6 1.3 9.4 1.1 6.9 0.9 5.3 ns B to A 1.8 14.9 1.9 10.3 1.3 9.4 1.2 8.8 0.9 8.3 ns tPHL HIGH to LOW propagation delay A to B 2.0 17.4 1.8 14.2 1.2 8.3 1.1 6.0 0.8 5.1 ns B to A 1.6 13.0 1.7 9.4 1.2 8.3 1.1 7.7 0.8 6.9 ns HIGH to OFF-state propagation delay DIR to A 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 ns DIR to B 2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0 7.6 ns LOW to OFF-state propagation delay DIR to A 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 ns DIR to B 2.0 16.1 2.2 14.6 1.8 9.9 2.2 9.3 1.6 6.4 ns OFF-state to HIGH propagation delay DIR to A [1] - 31.0 - 24.9 - 19.3 - 18.1 - 14.7 ns DIR to B [1] - 26.1 - 24.0 - 15.8 - 13.3 - 11.7 ns OFF-state to LOW propagation delay DIR to A [1] - 37.8 - 33.0 - 20.4 - 18.0 - 14.5 ns DIR to B [1] - 26.4 - 23.2 - 17.3 - 15.0 - 14.1 ns tPHZ tPLZ tPZH tPZL VCC(A) = 3.0 V to 3.6 V LOW to HIGH propagation delay A to B 2.0 18.9 1.8 17.1 1.2 8.8 0.7 6.2 0.6 4.9 ns B to A 1.5 13.0 1.5 8.0 1.1 6.9 0.6 6.2 0.5 6.0 ns tPHL HIGH to LOW propagation delay A to B 1.9 17.2 1.8 13.9 1.1 7.7 0.7 5.5 0.6 4.4 ns B to A 1.5 12.0 1.6 7.9 1.1 6.0 0.7 5.5 0.6 5.0 ns tPHZ HIGH to OFF-state propagation delay DIR to A 2.0 8.1 2.0 8.1 2.0 8.1 2.0 8.1 2.4 8.1 ns DIR to B 2.6 19.8 2.6 18.2 2.0 11.2 2.4 9.5 1.9 7.0 ns LOW to OFF-state propagation delay DIR to A 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 ns DIR to B 2.0 15.0 2.1 13.8 1.7 8.6 2.0 7.9 1.5 5.4 ns OFF-state to HIGH propagation delay DIR to A [1] - 28.0 - 21.8 - 15.5 - 14.1 - 11.4 ns DIR to B [1] - 25.1 - 23.3 - 15.0 - 12.4 - 11.1 ns OFF-state to LOW propagation delay DIR to A [1] - 31.8 - 26.1 - 17.2 - 15.0 - 12.0 ns DIR to B [1] - 25.3 - 22.0 - 15.8 - 13.6 - 12.5 ns tPLH tPLZ tPZH tPZL 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 12 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state Symbol Parameter Conditions VCC(B) Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Min Max Min Max Min Max Min Max Min Max VCC(A) = 4.5 V to 5.5 V LOW to HIGH propagation delay A to B 1.9 18.3 1.7 16.7 0.9 8.3 0.6 6.0 0.4 4.3 ns B to A 1.4 11.6 1.2 7.5 0.9 5.3 0.6 4.9 0.4 4.3 ns HIGH to LOW propagation delay A to B 2.0 16.9 1.6 13.5 0.9 6.9 0.6 5.0 0.4 3.9 ns B to A 1.5 11.9 1.5 7.7 0.8 5.1 0.6 4.4 0.4 3.9 ns HIGH to OFF-state propagation delay DIR to A 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 ns DIR to B 2.6 19.1 2.6 17.8 2.0 10.7 2.4 8.8 2.2 6.3 ns LOW to OFF-state propagation delay DIR to A 1.2 4.1 1.2 4.1 1.1 4.1 0.9 4.1 0.8 4.1 ns DIR to B 2.0 14.5 2.1 13.4 1.7 8.2 2.0 7.7 1.6 5.0 ns tPZH OFF-state to HIGH propagation delay DIR to A [1] - 26.1 - 20.9 - 13.5 - 12.6 - 9.3 ns DIR to B [1] - 22.4 - 20.8 - 12.4 - 10.1 - 8.4 ns tPZL OFF-state to LOW propagation delay DIR to A [1] - 31.0 - 25.5 - 15.8 - 13.2 - 10.2 ns DIR to B [1] - 22.9 - 19.5 - 12.9 - 11.0 - 9.9 tPLH tPHL tPHZ tPLZ [1] ns tPZH and tPZL are calculated values using the formula shown in Section 13.4. 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 13 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 11.1. Waveforms and test circuit VI VM nA, nB input GND tPHL tPLH VOH nB, nA output VM 001aaj644 VOL Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. The data input (A, B) to output (B, A) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH t PZH VY VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Enable and disable times Table 14. Measurement points Supply voltage Input [1] Output [2] VCC(A), VCC(B) VM VM VX VY 1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V 3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 14 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 15. Test data Supply voltage Input VCC(A), VCC(B) VI [1] Δt/ΔV [2] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ [3] 1.2 V to 5.5 V VCCI ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2VCCO [1] [2] [3] Load VEXT VCCI is the supply voltage associated with the data input port. dV/dt ≥ 1.0 V/ns. VCCO is the supply voltage associated with the output port. 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 15 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics 001aai907 14 tPHL (ns) 12 (1) 10 001aai908 14 tPLH (ns) 12 (1) 10 (2) 8 (2) 8 (3) 6 (3) (4) (5) (6) 6 (4) (5) (6) 4 4 2 2 0 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai909 14 tPHL (ns) 12 (1) 0 10 8 (4) (5) (6) 8 6 6 4 4 2 2 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 10 15 20 25 30 35 CL (pF) 001aai910 14 tPLH (ns) 12 (2) (3) 0 5 b. LOW to HIGH propagation delay (A to B) 10 0 0 0 (1) (2) (3) (4) (5) (6) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 8. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.2 V 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 16 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 001aai911 14 tPHL (ns) 12 001aai912 14 tPLH (ns) 12 (1) 10 10 (1) 8 8 (2) (2) 6 (3) 6 (3) (4) (5) (6) (4) 4 4 (5) 2 0 2 (6) 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai913 14 tPHL (ns) 12 10 0 0 5 10 15 20 25 30 35 CL (pF) b. LOW to HIGH propagation delay (A to B) 001aai914 14 tPLH (ns) 12 10 (1) 8 (1) 8 6 (2) (3) (4) 6 (2) (3) (4) (5) (5) (6) 4 2 0 (6) 4 2 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 9. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.5 V 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 17 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 001aai915 14 tPHL (ns) 12 10 (1) 10 (1) 8 8 (2) 6 (3) (4) 4 (5) (6) 2 0 001aai916 14 tPLH (ns) 12 0 5 10 15 20 25 6 (3) 4 (4) (5) (6) 2 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai917 14 tPHL (ns) 12 (2) 10 0 0 5 10 15 20 25 b. LOW to HIGH propagation delay (A to B) 001aai918 14 tPLH (ns) 12 10 8 8 (1) (1) 6 (2) (3) (4) (5) (6) 6 (2) (3) (4) (5) (6) 4 4 2 0 30 35 CL (pF) 2 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.8 V 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 18 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 001aai919 14 tPHL (ns) 12 10 001aai920 14 tPLH (ns) 12 (1) 10 (1) 8 8 (2) (2) 6 6 (3) (3) 4 2 0 0 5 10 15 20 25 2 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai921 14 tPHL (ns) 12 0 8 8 0 (2) (3) (4) (5) (6) 0 5 10 15 20 25 10 15 20 25 (1) (2) (3) (4) (5) (6) 4 2 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 30 35 CL (pF) 001aai922 6 (1) 2 5 14 tPLH (ns) 12 10 4 0 b. LOW to HIGH propagation delay (A to B) 10 6 (4) (5) (6) 4 (4) (5) (6) 0 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 11. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 2.5 V 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 19 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 001aai923 14 tPHL (ns) 12 10 001aai924 14 tPLH (ns) 12 10 (1) (1) 8 8 (2) 6 (2) 6 (3) (3) 4 2 0 4 (4) (5) (6) 0 5 10 15 20 25 2 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai925 14 tPHL (ns) 12 0 8 8 (2) (3) (4) (5) (6) 4 2 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 5 10 15 20 25 30 35 CL (pF) 001aai926 14 tPLH (ns) 12 10 (1) 0 b. LOW to HIGH propagation delay (A to B) 10 6 (4) (5) (6) 6 (1) 4 (2) (3) 2 (4) (5) (6) 0 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 12. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 3.3 V 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 20 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 001aai927 14 tPHL (ns) 12 10 001aai928 14 tPLH (ns) 12 10 (1) (1) 8 8 (2) 6 (2) 6 (3) (3) 4 2 0 4 (4) (5) (6) 0 5 10 15 20 25 2 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 001aai929 14 tPHL (ns) 12 (4) (5) (6) 0 0 5 10 15 20 25 30 35 CL (pF) b. LOW to HIGH propagation delay (A to B) 001aai930 14 tPLH (ns) 12 10 10 8 8 6 (1) 6 4 (2) (3) 4 (2) (3) 2 (4) (5) (6) 2 (4) (5) (6) 0 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) 0 (1) 0 5 10 15 20 25 30 35 CL (pF) d. LOW to HIGH propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. Fig. 13. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 5.0 V 74LVC_LVCH2T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 21 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 13. Application information 13.1. Unidirectional logic level-shifting application The circuit given in Fig. 14 is an example of the 74LVC2T45-Q100; 74LVCH2T45-Q100 being used in a unidirectional logic level-shifting application. VCC1 VCC2 VCC(A) VCC1 1A 1 8 VCC(B) VCC2 1B 74LVC2T45-Q100 7 2A 2B 3 74LVCH2T45-Q100 6 GND VCC1 2 4 5 DIR system-1 VCC2 system-2 aaa-006263 Fig. 14. Unidirectional logic level-shifting application Table 16. Description of unidirectional logic level-shifting application Pin Name Function Description 74LVC_LVCH2T45_Q100 Product data sheet 1 VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V) 2 1A OUT output level depends on VCC1 voltage 3 2A OUT output level depends on VCC1 voltage 4 GND GND device GND 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 2B IN input threshold value depends on VCC2 voltage 7 1B IN input threshold value depends on VCC2 voltage 8 VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V) All information provided in this document is subject to legal disclaimers. Rev. 3 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 22 / 30 Nexperia 74LVC2T45-Q100; 74LVCH2T45-Q100 Dual supply translating transceiver; 3-state 13.2. Bidirectional logic level-shifting application Fig. 15 shows the 74LVC2T45-Q100; 74LVCH2T45-Q100 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 I/O-1 VCC1 VCC2 VCC(A) PULL-UP/DOWN 1A 2A GND 1 8 VCC2 VCC(B) PULL-UP/DOWN I/O-2 1B 2 74LVC2T45-Q100 7 2B 74LVCH2T45-Q100 3 6 4 5 DIR DIR CTRL DIR CTRL system-1 system-2 aaa-006264 Pull-up or pull-down only needed for 74LVC2T45-Q100. Fig. 15. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 17. Description of bidirectional logic level-shifting application H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold 4 L input output system-2 data to system-1 13.3. Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. Typicaltotal supply current (ICC(A) + ICC(B)) VCC(A) VCC(B) 74LVC_LVCH2T45_Q100 Product data sheet Unit 0V 1.8 V 2.5 V 3.3 V 5.0 V 0V 0