74AUP1G08GW-Q100H

74AUP1G08-Q100 Low-power 2-input AND gate Rev. 2 — 28 January 2019 Product data sheet 1. General description The 74AUP1G08-Q100 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) ESD protection: • MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V • HBM JESD22-A114F Class 3A. Exceeds 5000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G08GW-Q100 -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G08GM-Q100 -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1G08GW-Q100 pE 74AUP1G08GM-Q100 pE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 B 2 A Y 1 4 4 2 Y B mna114 mna113 Fig. 1. A & Logic symbol Fig. 2. IEC logic symbol mna221 Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G08 74AUP1G08 B 1 A 2 GND 3 5 VCC 4 Y B 1 6 VCC A 2 5 n.c. GND 3 4 Y 001aaf026 Transparent top view 001aaf025 Fig. 4. Pin configuration SOT353-1 (TSSOP5) Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 2 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input Output A B Y L L L L H L H L L H H H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Min Max Unit -0.5 +4.6 V IIK input clamping current -50 - VI input voltage -0.5 +4.6 IOK output clamping current VO < 0 V -50 - VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC -0.5 +4.6 V - ±20 mA ICC supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] Conditions VI < 0 V [1] Tamb = -40 °C to +125 °C [1] [2] mA V mA The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V -40 +125 °C 0 200 ns/V Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74AUP1G08_Q100 Product data sheet VCC = 0.8 V to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 3 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V VCC - 0.1 - - V IO = -1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 1.11 - - V IO = -1.9 mA; VCC = 1.65 V 1.32 - - V IO = -2.3 mA; VCC = 2.3 V 2.05 - - V IO = -3.1 mA; VCC = 2.3 V 1.9 - - V IO = -2.7 mA; VCC = 3.0 V 2.72 - - V IO = -4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V Tamb = 25 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -20 μA; VCC = 0.8 V to 3.6 V VOL II LOW-level output voltage VI = VIH or VIL input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 μA additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 μA supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 μA additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1] - - 40 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF IOFF ΔIOFF ICC ΔICC 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 4 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.1 - - V IO = -1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 1.03 - - V IO = -1.9 mA; VCC = 1.65 V 1.30 - - V IO = -2.3 mA; VCC = 2.3 V 1.97 - - V IO = -3.1 mA; VCC = 2.3 V 1.85 - - V IO = -2.7 mA; VCC = 3.0 V 2.67 - - V IO = -4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V Tamb = -40 °C to +85 °C VIH VIL VOH VOL II IOFF ΔIOFF ICC ΔICC HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 μA power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 μA additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 μA supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 μA additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1] - - 50 μA VCC = 0.8 V 0.75 × VCC - - V VCC = 0.9 V to 1.95 V 0.70 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25 × VCC V VCC = 0.9 V to 1.95 V - - 0.30 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V Tamb = -40 °C to +125 °C VIH VIL HIGH-level input voltage LOW-level input voltage 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 5 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate Symbol Parameter VOH VOL II IOFF ΔIOFF ICC ΔICC [1] HIGH-level output voltage LOW-level output voltage Conditions Min Typ Max Unit IO = -20 μA; VCC = 0.8 V to 3.6 V VCC - 0.11 - - V IO = -1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = -1.7 mA; VCC = 1.4 V 0.93 - - V IO = -1.9 mA; VCC = 1.65 V 1.17 - - V IO = -2.3 mA; VCC = 2.3 V 1.77 - - V IO = -3.1 mA; VCC = 2.3 V 1.67 - - V IO = -2.7 mA; VCC = 3.0 V 2.40 - - V IO = -4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V VI = VIH or VIL VI = VIH or VIL - - 0.50 V input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 μA additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 μA supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 μA additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1] - - 75 μA One input at VCC - 0.6 V, other input at VCC or GND. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7 Symbol Parameter Conditions Min Typ [1] Max Unit - 17.0 - ns VCC = 1.1 V to 1.3 V 2.6 5.1 10.8 ns VCC = 1.4 V to 1.6 V 1.6 3.7 6.5 ns VCC = 1.65 V to 1.95 V 1.3 3.0 5.2 ns VCC = 2.3 V to 2.7 V 1.1 2.4 4.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.5 ns Tamb = 25 °C; CL = 5 pF tpd propagation delay A, B to Y; see Fig. 6 [2] VCC = 0.8 V 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 6 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = 25 °C; CL = 10 pF tpd propagation delay A, B to Y; see Fig. 6 [2] VCC = 0.8 V - 20.6 - ns VCC = 1.1 V to 1.3 V 2.4 6.0 12.5 ns VCC = 1.4 V to 1.6 V 2.0 4.3 7.6 ns VCC = 1.65 V to 1.95 V 1.7 3.6 6.1 ns VCC = 2.3 V to 2.7 V 1.4 2.9 4.8 ns VCC = 3.0 V to 3.6 V 1.3 2.7 4.2 ns - 24.1 - ns VCC = 1.1 V to 1.3 V 3.4 6.8 14.2 ns VCC = 1.4 V to 1.6 V 2.3 4.9 8.6 ns VCC = 1.65 V to 1.95 V 1.9 4.0 6.9 ns VCC = 2.3 V to 2.7 V 1.7 3.4 5.5 ns VCC = 3.0 V to 3.6 V 1.5 3.1 4.8 ns - 34.4 - ns VCC = 1.1 V to 1.3 V 4.6 9.1 19.4 ns VCC = 1.4 V to 1.6 V 3.4 6.4 11.5 ns VCC = 1.65 V to 1.95 V 2.6 5.3 9.1 ns VCC = 2.3 V to 2.7 V 2.3 4.5 7.2 ns VCC = 3.0 V to 3.6 V 2.2 4.2 6.2 ns VCC = 0.8 V - 2.5 - pF VCC = 1.1 V to 1.3 V - 2.7 - pF VCC = 1.4 V to 1.6 V - 2.8 - pF VCC = 1.65 V to 1.95 V - 2.9 - pF VCC = 2.3 V to 2.7 V - 3.5 - pF VCC = 3.0 V to 3.6 V - 4.0 - pF Tamb = 25 °C; CL = 15 pF tpd propagation delay A, B to Y; see Fig. 6 [2] VCC = 0.8 V Tamb = 25 °C; CL = 30 pF tpd propagation delay A, B to Y; see Fig. 6 [2] VCC = 0.8 V Tamb = 25 °C power dissipation capacitance f = 1 MHz; VI = GND to VCC CPD [1] [2] [3] [3] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of the outputs. 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 7 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7 Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max VCC = 1.1 V to 1.3 V 2.1 11.7 2.1 12.9 ns VCC = 1.4 V to 1.6 V 1.5 7.5 1.5 8.3 ns VCC = 1.65 V to 1.95 V 1.3 6.1 1.3 6.7 ns VCC = 2.3 V to 2.7 V 1.0 4.8 1.0 5.3 ns VCC = 3.0 V to 3.6 V 0.9 4.3 0.9 4.8 ns VCC = 1.1 V to 1.3 V 2.2 13.6 2.2 15.0 ns VCC = 1.4 V to 1.6 V 1.8 8.9 1.8 9.8 ns VCC = 1.65 V to 1.95 V 1.6 7.2 1.6 7.9 ns VCC = 2.3 V to 2.7 V 1.3 5.7 1.3 6.3 ns VCC = 3.0 V to 3.6 V 1.2 4.7 1.2 5.2 ns VCC = 1.1 V to 1.3 V 3.1 15.7 3.1 17.3 ns VCC = 1.4 V to 1.6 V 2.1 10.1 2.1 11.2 ns VCC = 1.65 V to 1.95 V 1.8 8.2 1.8 9.0 ns VCC = 2.3 V to 2.7 V 1.6 6.5 1.6 7.2 ns VCC = 3.0 V to 3.6 V 1.5 5.9 1.5 6.5 ns VCC = 1.1 V to 1.3 V 4.1 21.8 4.1 24.0 ns VCC = 1.4 V to 1.6 V 2.9 13.6 2.9 15.0 ns VCC = 1.65 V to 1.95 V 2.4 10.9 2.4 12.1 ns VCC = 2.3 V to 2.7 V 2.2 8.6 2.2 9.5 ns VCC = 3.0 V to 3.6 V 2.1 7.5 2.1 8.3 ns CL = 5 pF tpd propagation delay A, B to Y; see Fig. 6 [1] CL = 10 pF tpd propagation delay A, B to Y; see Fig. 6 [1] CL = 15 pF tpd propagation delay A, B to Y; see Fig. 6 [1] CL = 30 pF tpd [1] propagation delay A, B to Y; see Fig. 6 [1] tpd is the same as tPLH and tPHL. 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 8 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate 11.1. Waveforms and test circuit VI VM A, B input GND t PHL t PLH VOH VM Y output mna614 VOL Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. The data input (A or B) to output (Y) propagation delays Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 x VCC 0.5 x VCC VCC ≤ 3.0 ns VCC G VI DUT VEXT 5 kΩ VO RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 11. Test data Supply voltage Load VCC CL RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2 x VCC [1] VEXT For measuring enable and disable times RL = 5 kΩ. For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 9 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate 12. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm D E SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 e e1 L w M bp detail X 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 Fig. 8. REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Package outline SOT353-1 (TSSOP5) 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 10 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 Fig. 9. sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Package outline SOT886 (XSON6) 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 11 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate 13. Abbreviations Table 12. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G08_Q100 v.2 20190128 Product data sheet - 74AUP1G08_Q100 v.1 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74AUP1G08GM-Q100 (SOT886) added. 74AUP1G08_Q100 v.1 20130131 74AUP1G08_Q100 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 - © Nexperia B.V. 2019. All rights reserved 12 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. 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Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 13 / 14 74AUP1G08-Q100 Nexperia Low-power 2-input AND gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 3 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 9 12. Package outline........................................................ 10 13. Abbreviations............................................................ 12 14. Revision history........................................................12 15. Legal information......................................................13 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 28 January 2019 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 January 2019 © Nexperia B.V. 2019. All rights reserved 14 / 14