74AUP2G57
Low-power dual PCB configurable multiple function gate
Rev. 2 — 2 December 2015
Product data sheet
1. General description
The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs.
Each gate within the device can be configured as any of the following logic functions AND,
OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be
connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10% of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP2G57DP
40 C to +125 C
TSSOP10
plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
74AUP2G57GU
40 C to +125 C
XQFN10
plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40 1.80 0.50 mm
SOT1160-1
74AUP2G57GF
40 C to +125 C
XSON10
plastic extremely thin small outline package; no leads; SOT1081-2
10 terminals; body 1.0 1.7 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP2G57DP
aC
74AUP2G57GU
aC
74AUP2G57GF
aC
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Q$
Q<
Q%
Q&
DDD
Fig 1.
Logic symbol (one gate)
74AUP2G57
Product data sheet
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Rev. 2 — 2 December 2015
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Nexperia B.V. 2017. All rights reserved
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74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
6. Pinning information
6.1 Pinning
$83*
$
9&&
%
<
&
&
<
%
*1'
$
DDD
Fig 2.
Pin configuration SOT552-1 (TSSOP10)
$83*
$
9&&
<
WHUPLQDO
LQGH[DUHD
$83*
&
&
%
$
*1'
<
9&&
%
<
&
&
<
%
*1'
$
%
$
7UDQVSDUHQWWRSYLHZ
7UDQVSDUHQWWRSYLHZ
DDD
Fig 3.
DDD
Pin configuration SOT1160-1 (XQFN10)
74AUP2G57
Product data sheet
Fig 4.
Pin configuration SOT1081-2 (XSON10)
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Rev. 2 — 2 December 2015
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74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SOT552-1 and SOT1081-2 SOT1160-1
1A, 2A
1, 6
10, 5
data input
1B, 2B
2, 7
1, 6
data input
1C, 2C
3, 8
2, 7
data input
1Y, 2Y
9, 4
8, 3
data output
GND
5
4
ground (0 V)
VCC
10
9
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
nC
nB
nA
nY
L
L
L
H
L
L
H
L
L
H
L
H
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
H
H
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input AND
see Figure 5
2-input AND with both inputs inverted
see Figure 8
2-input NAND with inverted input
see Figure 6 and Figure 7
2-input OR with inverted input
see Figure 6 and Figure 7
2-input NOR
see Figure 8
2-input NOR with both inputs inverted
see Figure 5
2-input XNOR
see Figure 9
Inverter
see Figure 10
Buffer
see Figure 11
74AUP2G57
Product data sheet
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Rev. 2 — 2 December 2015
©
Nexperia B.V. 2017. All rights reserved
4 of 21
74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
9&&
Q%
Q&
Q<
Q%
Q%
Q&
Q<
9&&
Q%
Q&
Q&
Q<
Q%
Q<
Q%
Q&
Q<
Q<
DDD
DDD
Pin numbers are not valid for SOT1160-1 package
Fig 5.
Q&
Pin numbers are not valid for SOT1160-1 package
2-input AND gate or 2-input NOR gate with
both inputs inverted
Fig 6.
2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
9&&
9&&
Q$
Q&
Q<
Q$
Q&
Q$
Q<
Q$
Q&
Q&
Q<
Q$
Q&
Q<
Q<
Q$
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Fig 8.
2-input NOR gate or 2-input AND gate with
both inputs inverted
9&&
9&&
Q%
Q%
Q&
Q<
Q&
Q$
Q<
Q<
Q$
Q<
DDD
DDD
Pin numbers are not valid for SOT1160-1 package
Fig 9.
Q<
DDD
DDD
Fig 7.
Q&
Pin numbers are not valid for SOT1160-1 package
2-input XNOR gate
Fig 10. Inverter
9&&
Q%
Q%
Q<
Q<
DDD
Pin numbers are not valid for SOT1160-1 package
Fig 11. Buffer
74AUP2G57
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
©
Nexperia B.V. 2017. All rights reserved
5 of 21
74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
-
20
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
[1]
[2]
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP10 package: above 125C the value of Ptot derates linearly with 8.33 mW/K.
For XQFN10 (SOT1160-1) package: above 128 C the value of Ptot derates linearly with 11.5 mW/K.
For XSON10 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
Conditions
Product data sheet
Max
Unit
0.8
3.6
V
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
ambient temperature
74AUP2G57
Min
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Rev. 2 — 2 December 2015
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Nexperia B.V. 2017. All rights reserved
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74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.75 VCC -
-
V
IO = 1.7 mA; VCC = 1.4 V
1.11
-
-
V
Tamb = 25 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
IO = 1.9 mA; VCC = 1.65 V
1.32
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3 VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
VI = VT+ or VT
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
IOFF
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
40
A
CI
input capacitance
VI = GND or VCC; VCC = 0 V to 3.6 V
-
1.1
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.7
-
pF
74AUP2G57
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
©
Nexperia B.V. 2017. All rights reserved
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74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.7 VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.03
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.30
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3 VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
VI = VT+ or VT
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
-
-
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
VCC = 0 V to 0.2 V
-
-
0.6
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
50
A
74AUP2G57
Product data sheet
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Rev. 2 — 2 December 2015
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Nexperia B.V. 2017. All rights reserved
8 of 21
74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC 0.11 -
-
V
IO = 1.1 mA; VCC = 1.1 V
0.6 VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
0.93
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.17
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33 VCC V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
VI = VT+ or VT
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
75
A
74AUP2G57
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
©
Nexperia B.V. 2017. All rights reserved
9 of 21
74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Min
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
-
22.6
-
-
-
-
Unit
CL = 5 pF
tpd
propagation
delay
nA, nB and nC to nY; see Figure 12
[2]
VCC = 0.8 V
ns
VCC = 1.1 V to 1.3 V
2.8
6.5
12.6
2.5
13.0
13.2
ns
VCC = 1.4 V to 1.6 V
2.2
4.6
7.6
2.5
8.2
8.6
ns
VCC = 1.65 V to 1.95 V
2.1
3.9
6.2
2.0
6.8
7.2
ns
VCC = 2.3 V to 2.7 V
2.0
3.1
4.5
1.8
5.1
5.3
ns
VCC = 3.0 V to 3.6 V
1.8
2.8
3.9
1.5
4.1
4.3
ns
-
26.1
-
-
-
-
ns
CL = 10 pF
tpd
propagation
delay
nA, nB and nC to nY; see Figure 12
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
3.2
7.3
14.4
2.8
14.9
15.2
ns
VCC = 1.4 V to 1.6 V
2.6
5.2
8.7
2.8
9.3
9.8
ns
VCC = 1.65 V to 1.95 V
2.5
4.5
7.0
2.2
7.8
8.2
ns
VCC = 2.3 V to 2.7 V
2.4
3.7
5.2
2.1
5.9
6.2
ns
VCC = 3.0 V to 3.6 V
2.3
3.4
4.6
1.9
4.9
5.1
ns
-
31.6
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
3.4
8.0
15.7
3.1
16.7
17.0
ns
VCC = 1.4 V to 1.6 V
2.8
5.7
9.4
3.1
10.4
10.9
ns
VCC = 1.65 V to 1.95 V
2.6
4.9
7.7
2.5
8.7
9.2
ns
VCC = 2.3 V to 2.7 V
2.6
4.1
5.7
2.4
6.5
6.9
ns
VCC = 3.0 V to 3.6 V
2.5
3.8
5.0
2.2
5.5
5.7
ns
-
37.8
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.6
10.4
20.9
3.9
21.8
22.3
ns
VCC = 1.4 V to 1.6 V
3.6
7.4
12.2
3.8
13.4
14.1
ns
VCC = 1.65 V to 1.95 V
3.5
6.2
9.9
3.1
11.1
11.8
ns
VCC = 2.3 V to 2.7 V
3.4
5.2
7.4
3.1
8.3
8.8
ns
VCC = 3.0 V to 3.6 V
3.2
4.9
6.6
2.8
7.0
7.4
ns
CL = 15 pF
tpd
propagation
delay
nA, nB and nC to nY; see Figure 12
[2]
VCC = 0.8 V
CL = 30 pF
tpd
propagation
delay
74AUP2G57
Product data sheet
nA, nB and nC to nY; see Figure 12
VCC = 0.8 V
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
©
Nexperia B.V. 2017. All rights reserved
10 of 21
74AUP2G57
Nexperia
Low-power dual PCB configurable multiple function gate
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
VCC = 0.8 V
-
2.6
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.8
-
-
-
-
pF
VCC = 1.4 V to 1.6 V
-
2.9
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
3.1
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.7
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.3
-
-
-
-
pF
CL = 5 pF, 10 pF, 15 pF and 30 pF
power
dissipation
capacitance
CPD
[3]
fi = 1 MHz; VI = GND to VCC
[4]
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
All specified values are the average typical values over all stated loads.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
12. Waveforms
9,
Q$Q%Q&LQSXW
90
90
*1'
W3+/
W3/+
92+
90
Q
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