74LVC1G08GV-Q100,1

74LVC1G08-Q100 Single 2-input AND gate Rev. 3 — 25 January 2019 Product data sheet 1. General description The 74LVC1G08-Q100 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance ≤ 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74LVC1G08GW-Q100 -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1 body width 1.25 mm Version 74LVC1G08GV-Q100 -40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G08GM-Q100 -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74LVC1G08-Q100 Nexperia Single 2-input AND gate 4. Marking Table 2. Marking Type number Marking code [1] 74LVC1G08GW-Q100 VE 74LVC1G08GV-Q100 V08 74LVC1G08GM-Q100 VE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 B 2 A Y 1 4 4 2 Y B mna114 mna113 Fig. 1. A & Logic symbol Fig. 2. IEC logic symbol mna221 Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G08 74LVC1G08 B 1 A 2 GND 3 5 4 B 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC Y 001aab639 001aab638 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) Transparent top view Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5, SC-74A XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 2 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate 7. Functional description Table 4. Function table [1] Input Output A B Y L L L L H L H L L H H H [1] H = HIGH voltage level; L = LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode [1] -0.5 VCC + 0.5 V Power-down mode; VCC = 0 V [1] -0.5 +6.5 V - ±50 mA VI < 0 V [1] IO output current ICC supply current - 100 mA IGND ground current -100 - mA Ptot total power dissipation - 250 mW Tstg storage temperature -65 +150 °C [1] [2] VO = 0 V to VCC mA Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature Δt/ΔV input transition rise and fall rate Active mode Power-down mode; VCC = 0 V 74LVC1G08_Q100 Product data sheet 0 - 5.5 V -40 - +125 °C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 3 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C HIGH-level input VCC = 1.65 V to 1.95 V voltage VCC = 2.3 V to 2.7 V VIH VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage -40 °C to +125 °C Unit Min Typ [1] Max Min Max 0.65VCC - - 0.65VCC - V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - VCC = 2.7 V to 3.6 V - - 0.8 VCC = 4.5 V to 5.5 V - - 0.3VCC VCC - 0.1 - IO = -4 mA; VCC = 1.65 V 1.2 IO = -8 mA; VCC = 2.3 V 1.9 IO = -12 mA; VCC = 2.7 V 0.35VCC V 0.7 V - 0.8 V - 0.3VCC V - VCC - 0.1 - V - - 0.95 - V - - 1.7 - V 2.2 - - 1.9 - V IO = -24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = -32 mA; VCC = 4.5 V 3.8 - - 3.4 - V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 - ±1 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - ±0.1 ±2 - ±2 μA ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 μA ΔICC additional supply per pin; VCC = 2.3 V to 5.5 V; current VI = VCC - 0.6 V; IO = 0 A - 5 500 - 500 μA CI input capacitance - 5 - - - pF [1] VCC = 3.3 V; VI = GND to VCC All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 4 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7. Symbol Parameter tpd propagation delay CPD [1] [2] [3] Conditions power dissipation capacitance -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.4 8.0 1.0 10.5 ns VCC = 2.3 V to 2.7 V 0.5 2.2 5.5 0.5 7.0 ns VCC = 2.7 V 0.5 2.5 5.5 0.5 7.0 ns VCC = 3.0 V to 3.6 V 0.5 2.1 4.5 0.5 6.0 ns VCC = 4.5 V to 5.5 V 0.5 1.7 4.0 0.5 5.5 ns - 16 - - - pF A, B to Y; see Fig. 6 [2] VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLZ and tPZL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 11.1. Waveforms and test circuit VI VM A, B input GND t PHL t PLH VOH VM Y output mna614 VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. The input A, B to output Y propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 5 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC1G08_Q100 Product data sheet VEXT Load All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 6 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate 12. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm D E SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 e e1 L w M bp detail X 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 Fig. 8. REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Package outline SOT353-1 (TSSOP5) 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 7 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate Plastic surface-mounted package; 5 leads SOT753 D B E y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 Fig. 9. JEITA EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 SC-74A Package outline SOT753 (SC-74A) 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 8 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig. 10. Package outline SOT886 (XSON6) 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 9 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G08_Q100 v.3 20190125 Product data sheet - Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVC1G08GM-Q100 (SOT886) added. 74LVC1G08_Q100 v.2 20161207 Modifications: • 74LVC1G08_Q100 v.1 20120709 74LVC1G08_Q100 Product data sheet 74LVC1G08_Q100 v.2 Product data sheet - 74LVC1G08_Q100 v.1 Table 7: The maximum limits for leakage current and supply current have changed. Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 - © Nexperia B.V. 2019. All rights reserved 10 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. 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Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 11 / 12 74LVC1G08-Q100 Nexperia Single 2-input AND gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 3 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................5 11.1. Waveforms and test circuit........................................ 5 12. Package outline.......................................................... 7 13. Abbreviations............................................................ 10 14. Revision history........................................................10 15. Legal information......................................................11 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 January 2019 74LVC1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 25 January 2019 © Nexperia B.V. 2019. All rights reserved 12 / 12 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74LVC1G08GV-Q100,1 74LVC1G08GW-Q100,1 74LVC1G08GM-Q100X