74LVC2G86DP-Q100H

74LVC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate Rev. 2 — 14 December 2016 Product data sheet 1. General description The 74LVC2G86-Q100 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant inputs for interfacing with 5 V logic  High noise immunity  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V)  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  24 mA output drive (VCC = 3.0 V)  CMOS low-power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V 74LVC2G86-Q100 Nexperia Dual 2-input EXCLUSIVE-OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G86DP-Q100 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G86DC-Q100 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G86DP-Q100 V86 74LVC2G86DC-Q100 V86 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram  $ % < $ % <  DDK Fig 1. DDK Logic symbol Fig 2. IEC logic symbol % < $ Fig 3. PQD Logic diagram (one driver) 74LVC2G86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 December 2016 © Nexperia B.V. 2017. All rights reserved 2 of 14 74LVC2G86-Q100 Nexperia Dual 2-input EXCLUSIVE-OR gate 6. Pinning information 6.1 Pinning /9&*4 $   9&& %   < <   % *1'   $ DDD Fig 4. Pin configuration SOT505-2 and SOT765-1 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nA nB nY L L L L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level 74LVC2G86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 December 2016 © Nexperia B.V. 2017. All rights reserved 3 of 14 74LVC2G86-Q100 Nexperia Dual 2-input EXCLUSIVE-OR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - 0.5 +6.5 V mA - 50 Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - 100 mA 100 - mA - 300 mW 65 +150 C VO > VCC or VO < 0 V VO = 0 to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] mA For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate 74LVC2G86_Q100 Product data sheet Conditions Min Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V VCC = 0 V; Power-down mode 0 5.5 V 40 +125 C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 December 2016 © Nexperia B.V. 2017. All rights reserved 4 of 14 74LVC2G86-Q100 Nexperia Dual 2-input EXCLUSIVE-OR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit Tamb = 40 C to +85 C VIH VIL VOL VOH HIGH-level input voltage LOW-level input voltage LOW-level output voltage 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.65 V to 1.95 V 0.35  VCC V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V IO = 8 mA; VCC = 2.3 V - 0.12 0.3 V 0.3  VCC V VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - 0.17 0.4 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V IO = 32 mA; VCC = 4.5 V - 0.39 0.55 V HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 1.54 - V IO = 8 mA; VCC = 2.3 V 1.9 2.15 - V IO = 12 mA; VCC = 2.7 V 2.2 2.50 - V IO = 24 mA; VCC = 3.0 V 2.3 2.62 - V IO = 32 mA; VCC = 4.5 V 3.8 4.11 - V - 0.1 1 A II input leakage current IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 A ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 2.5 - pF 74LVC2G86_Q100 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 December 2016 © Nexperia B.V. 2017. All rights reserved 5 of 14 74LVC2G86-Q100 Nexperia Dual 2-input EXCLUSIVE-OR gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ[1] Max 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.65 V to 1.95 V - - Conditions Unit Tamb = 40 C to +125 C HIGH-level input voltage VIH LOW-level input voltage VIL LOW-level output voltage VOL VOH VCC = 1.65 V to 1.95 V 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3  VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V VCC  0.1 - - V HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V - - 1 A II input leakage current IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 A ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 500 A [1] VI = 5.5 V or GND; VCC = 0 V to 5.5 V All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 74LVC2G86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 14 December 2016 © Nexperia B.V. 2017. All rights reserved 6 of 14 74LVC2G86-Q100 Nexperia Dual 2-input EXCLUSIVE-OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 6. Symbol Parameter 40 C to +85 C Conditions power dissipation capacitance CPD Min Max Min Max VCC = 1.65 V to 1.95 V 1.4 3.8 9.9 1.4 12.4 ns VCC = 2.3 V to 2.7 V 0.8 2.5 5.7 0.8 7.2 ns VCC = 2.7 V 0.8 3.0 5.7 0.8 7.2 ns VCC = 3.0 V to 3.6 V 0.8 2.3 4.7 0.8 5.9 ns VCC = 4.5 V to 5.5 V 0.6 1.9 3.6 0.6 4.5 ns - 15.8 - - - pF [3] per gate; VI = GND to VCC; VCC = 3.3 V output enabled [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL [3] Unit [2] propagation delay nA, nB to nY; see Figure 5 tpd 40 C to +125 C Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. Waveforms 9, 90 Q$Q%LQSXW *1' W 3+/ W 3/+ 92+ Q