NV6115-RA

NV6115 650 V GaNFast™ Power IC 2. Description QFN 5 x 6 mm The NV6115 is a 650 V GaNFast™ power IC, optimized for high frequency, soft-switching topologies. Monolithic integration of FET, drive and logic creates an easy-to-use ‘digital-in, power-out’ high-performance powertrain building block, enabling designers to create the fastest, smallest, most efficient integrated powertrain in the world. The highest dV/dt immunity, high-speed integrated drive and industry-standard low-profile, low-inductance, 5 x 6 mm SMT QFN package allow designers to exploit Navitas GaN technology with simple, quick, dependable solutions for breakthrough power density and efficiency. Navitas’ GaNFast™ power ICs extend the capabilities of traditional topologies such as flyback, half-bridge, resonant, etc. to MHz+ and enable the commercial introduction of breakthrough designs. Simplified schematic 1. Features GaNFast™ Power IC • Monolithically-integrated gate drive • Wide logic input range with hysteresis • 5 V / 15 V input-compatible • Wide VCC range (10 to 30 V) • Programmable turn-on dV/dt • 200 V/ns dV/dt immunity • 650 V eMode GaN FET 3. Topologies / Applications • • • • • • • • • Low 170 mΩ resistance • Zero reverse recovery charge • 2 MHz operation Small, low-profile SMT QFN • 5 x 6 mm footprint, 0.85 mm profile • Minimized package inductance AC-DC, DC-DC, DC-AC Buck, boost, half bridge, full bridge Active Clamp Flyback, LLC resonant, Class D Mobile fast-chargers, adapters Notebook adaptors LED lighting, solar micro-inverters TV / monitor, wireless power Server, telecom & networking SMPS Environmental • RoHS, Pb-free, REACH-compliant 4. Typical Application Circuits DCIN(+) DCOUT(+) DCIN(+) D VCC PWM D 10V to 24V PWM Half Bridge Driver IC REG VDD DZ REG VDD VCC dV/dt DZ dV/dt NV6115 S D VCC PWM REG VDD NV6115 DZ S dV/dt 10V to 24V NV6115 S DCIN(-) DCIN(-) DCOUT(-) Half-bridge Boost Final Datasheet PGND 1 Rev 5-15-2018 NV6115 5. Table of Contents 1. Features ...................................................................1 8. Functional Description ........................................ 11 2. Description ..............................................................1 8.1. Start Up ............................................................ 11 3. Topologies / Applications ......................................1 8.2. Normal Operating Mode ................................... 12 4. Typical Application Circuits ..................................1 8.3. Standby Mode .................................................. 12 6. Specifications .........................................................3 8.4. Programmable Turn-on dV/dt Control .............. 12 6.1. Absolute Maximum Ratings ................................3 8.5. Current Sensing ............................................... 13 6.2. Recommended Operating Conditions .................3 8.6. Paralleling Devices ........................................... 13 6.3. ESD Ratings........................................................4 8.7. 3.3V PWM Input Circuit .................................... 14 6.4. Thermal Resistance ............................................4 8.8. PCB Layout Guidelines .................................... 14 6.5. Electrical Characteristics .....................................5 8.9. Recommended Component Values ................. 15 6.6. Switching Waveforms .........................................6 9. Recommended PCB Land Pattern ..................... 16 6.7. Characteristic Graphs .........................................7 10. PCB Layout Guidelines ..................................... 17 7. Internal Schematic, Pin Configurations and Functions ...................................................................10 12. QFN Package Outline ........................................ 19 13. Tape and Reel Dimensions ............................... 20 14. Ordering Information ......................................... 21 Final Datasheet 2 Rev 5-15-2018 NV6115 6. Specifications 6.1. Absolute Maximum Ratings (with respect to Source (pad) unless noted) SYMBOL VDS PARAMETER Drain-to-Source Voltage VTDS Transient Drain-to-Source Voltage VCC Supply Voltage (1) MAX UNITS -7 to +650 V 750 V 30 V VPWM PWM Input Pin Voltage -3 to +30 V VDZ VDD Setting Pin Voltage 6.6 V VDD Drive Supply Voltage 7.2 V ID Continuous Drain Current (@ TC = 100ºC) 8 A ID PULSE Pulsed Drain Current (10 µs @ TJ = 25°C) 16 A ID PULSE Pulsed Drain Current (10 µs @ TJ = 125°C) 12 A Slew Rate on Drain-to-Source 200 V/ns Operating Junction Temperature -55 to 150 ºC Storage Temperature -55 to 150 ºC dV/dt TJ TSTOR (1) < 1 µS. VTDS is intended for surge rating during non-repetitive events (for example start-up, line interruption) (2) Absolute maximum ratings are stress ratings; devices subjected to stresses beyond absolute maximum ratings may cause permanent damage. 6.2. Recommended Operating Conditions SYMBOL PARAMETER MIN VDZ Drive Supply Set Zener Voltage 5.8 VDD Drive Supply Voltage 5.5 IDD_EXT Regulator External Load Current VPWM PWM Input Pin Voltage VDS Drain-to-Source Voltage VCC Supply Voltage Operating Junction Temperature TJ TYP (3) 6.2 MAX UNITS 6.6 V 7.0 V 3.0 mA Min. of (VCC or 20) V 520 V 10 24 V -40 125 °C 0 5 (3) Use of zener diode other than 6.2 V is not recommended. See Table I for recommended part numbers of 6.2 V zener diodes. (4) Exposure to conditions beyond maximum recommended operating conditions for extended periods of time may affect device reliability. Final Datasheet 3 Rev 5-15-2018 NV6115 6.3. ESD Ratings SYMBOL PARAMETER MAX UNITS HBM Human Body Model (per JS-001-2014) 1,000 V CDM Charged Device Model (per JS-002-2014) 1,000 V TYP UNITS 6.4. Thermal Resistance SYMBOL PARAMETER RɵJC (5) Junction-to-Case 2.2 ºC/W RɵJA (5) Junction-to-Ambient 50 ºC/W (5) Rɵ measured on DUT mounted on 1 square inch 2 oz Cu (FR4 PCB) Final Datasheet 4 Rev 5-15-2018 NV6115 6.5. Electrical Characteristics Typical conditions: VDS = 400 V, VCC = 15 V, VDZ = 6.2 V, FSW = 1 MHz, TAMB = 25 ºC, ID = 4 A (unless otherwise specified) SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS VCC Supply Characteristics IQCC VCC Quiescent Current 0.85 IQCC-SW VCC Operating Current 2.3 VPWMH Input Logic High Threshold (rising edge) VPWML Input Logic Low Threshold (falling edge) VI-HYS Input Logic Hysteresis 0.5 V TON Turn-on Propagation Delay 11 ns Fig.1, Fig.2 TOFF 1.5 mA VPWM = 0 V mA FSW = 1 MHz, VDS = Open Low-Side Logic Input Characteristics 4 1 V V Turn-off Propagation Delay 9 ns Fig.1, Fig.2 TR Drain rise time 6 ns Fig.1, Fig.2 TF Drain fall time 3 ns Fig.1, Fig.2 Switching Characteristics FSW Switching Frequency tPW Pulse width 0.02 2 MHz 1000 µs GaN FET Characteristics IDSS Drain-Source Leakage Current 0.2 IDSS Drain-Source Leakage Current 7 25 µA VDS = 650 V, VPWM = 0 V µA VDS = 650 V, VPWM = 0 V, TC = 125 ºC Drain-Source Resistance 170 238 mΩ VPWM = 6 V, ID = 4 A VSD Source-Drain Reverse Voltage 3.2 5 V VPWM = 0 V, ISD = 4 A QOSS Output Charge 16 nC QRR Reverse Recovery Charge 0 nC COSS Output Capacitance 18 pF VDS = 400 V, VPWM = 0 V 24 pF VDS = 400 V, VPWM = 0 V 40 pF VDS = 400 V, VPWM = 0 V RDS(ON) CO(er)(1) CO(tr)(2) Effective Output Capacitance, Energy Related Effective Output Capacitance, Time Related VDS = 400 V, VPWM = 0 V (1) CO(er) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 400 V (2) CO(tr) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 400 V Final Datasheet 5 Rev 5-15-2018 NV6115 6.6. Switching Waveforms (TC = 25 ºC unless otherwise specified) VPWM 50% VDS t VDS 90% 10% TOFF TON TF Fig.1. Inductive switching circuit Final Datasheet TR t Fig.2. Propagation delay and rise/fall time definitions 6 Rev 5-15-2018 NV6115 6.7. Characteristic Graphs (GaN FET, TC = 25 ºC unless otherwise specified) Fig.3. Pulsed Drain current (ID PULSE) vs. Fig.4. Pulsed Drain current (ID PULSE) vs. drain-to-source voltage (VDS) at T = 25 °C drain-to-source voltage (VDS) at T = 125 °C Fig.5. Source-to-drain reverse conduction voltage Fig.6. Drain-to-source leakage current (IDSS) vs. drain-to-source voltage (VDS) Fig.7. VPWMH and VPWML vs. junction temperature(TJ) Fig.8. Normalized on-resistance (RDS(ON)) vs. junction temperature (TJ) Final Datasheet 7 Rev 5-15-2018 NV6115 Characteristic Graphs (Cont.) Fig.9. Output capacitance (COSS) vs. drain-to-source voltage (VDS) Fig.10. Energy stored in output capacitance (EOSS) vs. drain-to-source voltage (VDS) Fig.11. Charge stored in output capacitance (QOSS) vs. drain-to-source voltage (VDS) Fig.12. VCC operating current (IQCC-SW ) vs. operating frequency (FSW) Fig.13. VCC quiescent current (IQCC) vs. Fig.14. Propagation delay (TON and TOFF) vs. junction temperature(TJ) supply voltage (VCC) Final Datasheet 8 Rev 5-15-2018 NV6115 Characteristic Graphs (Cont.) Fig.16. Power dissipation (PTOT) vs. case temperature (TC) Fig.15. Slew rate (dV/dt) vs. gate drive turn-on current set resistance (RDD) at T = 25 °C Fig.17. Max. thermal transient impedance (ZthJC) vs. pulse width (tP) Final Datasheet 9 Rev 5-15-2018 NV6115 7. Internal Schematic, Pin Configurations and Functions 1 4 3 VCC D DZ REG VDD 8 7 6 5 dV/dt 2 PWM S PAD Package Top View Pin I/O(1) Description Number Symbol 1 VCC P Supply voltage (10V to 24V) 2 PWM I PWM input 3 VDD I Gate drive supply voltage. Gate drive turn-on current set pin (using RDD). 4 DZ I Gate drive supply voltage set pin (6.2 V zener to GND). 5,6,7,8 D P Drain of power FET PAD S O, G Source of power FET & GaN IC supply ground. Metal pad on bottom of package. (1) I = Input, O = Output, P = Power, G = GaN IC Ground Final Datasheet 10 Rev 5-15-2018 NV6115 8. Functional Description The following functional description contains additional information regarding the IC operating modes and pin functionality. NV6115 10V to 24V VCC 1 PWM 8.1. Start Up D VDD DZ When the VCC supply is first applied to the NV6115, care should be taken such that the VDD and DZ pins are up at their correct voltage levels before the PWM input signal starts. The VDD pin ramp up time is determined by the internal regulator current at this pin and the external CVDD capacitor. Also, since the DZ pin voltage sets the VDD voltage level, the VDD pin will ramp up together with the DZ pin (Fig.18). 10nF 6.2V S Fig.18. Quick start-up circuit For half-bridge configurations, it is important that the VCC supply, the DZ pin, and the VDD supply of the high-side NV6115 are all charged up to their proper levels before the first high-side PWM pulses start. For LLC applications, a long on-time PWM pulse to the low-side (> 10 µs) is typically provided by the LLC controller to allow the supply pins of the high-side NV6115 to charge up (through the external bootstrap diode) to their correct levels before the first high-side PWM pulses start (Fig.19). For active clamp flyback (ACF) applications, the halfbridge must be ready very quickly due to the soft-start mode of the ACF controller. When the first few PWM pulses are generated by the ACF controller, the highside supply pins of the NV6115 will require a few lowside pulses to charge up (through the external bootstrap diode) before the high-side starts to switch (Fig.20). Fig.19. LLC half-bridge start-up timing diagram Fig.20. ACF half-bridge start-up timing diagram Final Datasheet 11 Rev 5-15-2018 NV6115 8.2. Normal Operating Mode NV6115 During Normal Operating Mode, all of the internal circuit blocks are active. VCC is operating within the recommended range of 10 V to 24 V, the VDD pin is at the voltage set by the zener diode at the DZ pin (6.2 V), and the internal gate drive and power FET are both enabled. The external PWM signal at the PWM pin determines the frequency and duty-cycle of the internal gate of the power FET. As the PWM voltage toggles above and below the rising and falling input thresholds (4 V and 1 V), the internal gate of the power FET toggles on and off between VDD and 0 V (Fig.21). The drain of the power FET then toggles between the source voltage (typically power ground) and a higher voltage level (650 V max), depending on the external power conversion circuit topology. 1 D VDD DZ SI1330EDL ENABLE S Fig.22. Standby mode VCC cut-off circuit 8.4. Programmable Turn-on dV/dt Control During first start-up pulses or during hard-switching conditions, it is desirable to limit the slew rate (dV/dt) of the drain of the power FET during turn-on. This is necessary to reduce EMI or reduce circuit switching noise. To program the turn-on dV/dt rate of the internal power FET, a resistor (RDD) is placed in between the VDD capacitor and the VDD pin. This resistor (RDD) sets the turn-on current of the internal gate driver and therefore sets the turn-on falling edge dV/dt rate of the drain of the power FET (Fig.23). A typical turn-on slew-rate change with respect to RDD is shown in Fig.15. t VDS VBUS TON VCC PWM 100K VPWM TOFF BSS84A 10V to 24V t TPERIOD VPWM Fig.21. Normal operating mode timing diagram 8.3. Standby Mode TOFF VDS For applications where a low standby power is required, an external series cut-off circuit (Fig.22) can be used to disconnect VCC of the NV6115 from the main VCC supply of the power supply. This will reduce VCC current consumption when the converter is in burst mode during light-load or open load conditions. The VCC cut-off circuit consists of a series PMOS FET that is turned on and off with a pull-down NMOS FET. The gate of the NMOS is controlled by an external ENABLE signal that should be provided by the main controller of the power supply. The capacitor value at the VCC pin should then be selected according to the desired start-up speed of the NV6115 each time the ENABLE signal toggles high. A 22 nF capacitor at VCC, for example, will give a typical start-up time of approximately 2 μs. Final Datasheet t TON VBUS Drain turn-on Falling edge Increase RDD to Decrease dv/dt t Fig.23. Turn-on dV/dt slew rate control 12 Rev 5-15-2018 NV6115 8.5. Current Sensing 8.6. Paralleling Devices For many applications it is necessary to sense the cycleby-cycle current flowing through the power FET. To sense the current flowing through the NV6115, a standard current-sensing resistor can be placed in between the source and power ground (Fig.24). In this configuration, all of the components around the NV6115 (CVCC, CVDD, DZ, etc.) should be grounded with a single connection at the source. Also, an additional RC filter can be inserted between the PWM signal and the PWM pin (100 Ω, 100 pF typical). This filter is necessary to prevent false triggering due to high-frequency voltage spikes occurring at the source node due to external parasitic inductance from the source PCB trace or the current-sensing resistor itself. For some applications it is desirable to parallel ICs in order to reduce conduction losses and temperatures. A maximum of two NV6115 ICs can be connected in parallel in a PFC boost application working in boundaryconduction mode (BCM) only. The parallel configuration for two NV6115 ICs is shown in Fig.25. The paired pins that are connected together include the drain pins (D), the source pins (S), the VCC pins, the PWM pins, and the DZ. A single DZ diode can be shared by both ICs. The VDD pins are not connected together and require separate VDD supply capacitors (CVDD1, CVDD2) and separate turn-on current set resistors (RDD1, RDD2). Each IC should have its own local VCC supply filter capacitor (CVCC1, CVCC2). The PWM pins can have a single filter resistor (RPWM) but separate filter capacitors (CPWM1, CPWM2) should be placed at the PWM pin of each IC. NV6115 10V to 24V VCC When designing the PCB layout for the two paralleled ICs, the drain and source connections should be made as symmetrical as possible two avoid any parasitic inductance or capacitance mismatch. A proper PCB layout example for paralleling is shown in Section 11. 1 PWM 100R 100pF D VDD DZ DCIN(+) DCOUT(+) S NV6115 NV6115 D D S S RCS RDD1 RPWM CVDD1 CVCC2 VDD VCC DZ VDD VCC PWM CVCC1 10V to 24V Fig.24. Current sensing circuit DZ PWM 1 1 PGND DZ CS RDD2 CVDD2 CPWM2 CPWM1 CS RCS DCIN(-) DCOUT(-) Fig.25. Boost schematic using two parallel ICs Final Datasheet 13 Rev 5-15-2018 NV6115 The following rules should be followed carefully during the design of the PCB layout: 8.7. 3.3V PWM Input Circuit 1) Place all IC filter and programming components directly next to the IC. These components include (CVCC, CVDD, RPWM, CPWM, For some applications where a 3.3 V PWM signal is required (DSP, MCU, etc.) an additional buffer can be placed before the PWM input pin (Fig.26) with the buffer supply voltage connected to the VDD capacitor. RDD and DZ). 2) Keep ground trace of IC filter and programming components separate from power GND trace. Do not run power GND currents through ground trace of filter components! 10V to 24V 3) For best thermal management, place thermal vias in the source pad area to conduct the heat out through the bottom of the package and through the PCB board to other layers (see Sections 10 and 11 for correct layout examples). 4) Use large PCB thermal planes (connected with thermal vias to the source pad) and additional PCB layers to reduce IC temperatures as much as possible (see Sections 10 and 11 for correct layout examples). Fig.26. 3.3 V PWM input buffer circuit 5) For half-bridge layouts, do not extend copper planes from one IC across the components or pads of the other IC! 8.8. PCB Layout Guidelines The design of the PCB layout is critical for good noise immunity, sufficient thermal management, and proper operation of the IC. Typical PCB layout examples for without current sensing resistor, with current sensing resistor, and paralleling, are all shown in Sections 10 and 11. Final Datasheet 6) For high density designs use additional PCB layers to route signal connections. This allows layout to maintain large thermal copper planes. 14 Rev 5-15-2018 NV6115 8.9. Recommended Component Values The following table (Table I) shows the recommended component values (typical only) for the external filter capacitors and zener diode connected to the pins of the NV6115. These components should be placed as close as possible to the IC. Please see PCB Layout guidelines for more information. The zener diode at the DZ pin should be a low-current type with a flat zener. SYM DESCRIPTION PART NO. SUPPLIER TYP UNITS CVCC Maximum VCC supply capacitor 0.1 µF CVDD VDD supply capacitor 0.01 µF RDD Gate drive turn-on current set resistor 25 (range 0 to 200) Ω DZ VDD set zener diode (DZ pin) 6.2 V BZT52B6V2 RHG MM3Z6V2ST1G Taiwan Semiconductor Corporation ON-Semiconductor RPWM PWM filter resistor 100 Ω CPWM PWM filter capacitor 100 pF Table I. Recommended component values (typical only). 1. Zener Selection The zener voltage is a critical parameter that sets the internal reference for gate drive voltage and other circuitry. The zener diode needs to be selected such that the voltage on the D Z pin is within recommended operating conditions (5.8 V to 6.6 V) across operating temperature (-40°C to 125°C) and bias current (10 µA to 1 mA). To ensure effective operation, the current vs. voltage characteristics of the zener diode should be measured down to 10µA to ensure flat characteristics across the current operating range (10 µA to 1 mA). The recommended part numbers meet these requirements. If the zener selected by user does not ensure that the voltage on the zener pin is always within the recommended operating range, the functionality and reliability of the NV6115 can be impacted. An external resistor (~47 kΩ) between VCC and DZ can improve zener voltage stability by adding bias current to the zener pin to ensure the voltage on the DZ pin is always within the recommended operating range (Fig.27). This will add ~200µA of quiescent current. 10V to 24V Fig.27. Increasing Zener Bias Current for Stable Zener Voltage Final Datasheet 15 Rev 5-15-2018 NV6115 9. Recommended PCB Land Pattern All dimensions are in mm Final Datasheet 16 Rev 5-15-2018 NV6115 10. PCB Layout Guidelines Final Datasheet 17 Rev 5-15-2018 NV6115 11. PCB Layout Guidelines (cont.) PCB Via Top Layer Paralleling 2 ICs (Boost PFC, BCM Mode only) Bottom Layer Component Landing Pad (Top Layer) Drain Switching Node NV6115 NV6115 D D S S RDD1 CVDD1 CVCC2 CVDD2 RDD2 CPWM2 CPWM1 RPWM DZ PWM VCC DZ VDD PWM VCC CVCC1 10V to 24V DZ VDD 1 1 CS RCS PWR GND Drain Switching Node PCB Bottom Layer Thermal Copper Area (adjust size as necessary) NV6115 NV6115 D D S 1 S 1 4 CVCC1 DZ CPWM1 4 CVCC2 CPWM2 RDD1 Thermal Vias (dia = 0.65mm, hole = 0.33mm, pitch = 0.925mm, via wall thickness = 1mil) RDD2 CVDD1 CVDD2 RPWM PWM Input VCC Supply CS Signal RCS PWR GND Current Sensing Resistors (RCS) (Top View) Final Datasheet 18 Rev 5-15-2018 NV6115 12. QFN Package Outline Final Datasheet 19 Rev 5-15-2018 NV6115 13. Tape and Reel Dimensions Final Datasheet 20 Rev 5-15-2018 NV6115 14. Ordering Information Part Number Operating Temperature Grade Storage Temperature Range Package MSL Rating Packing (Tape & Reel) NV6115 -40 °C to +125 °C TCASE -55 °C to +150 °C TCASE 5 x 6 mm QFN 3 1,000 : 7” Reel 5,000 : 13” Reel Additional Information DISCLAIMER Navitas Semiconductor Inc. (Navitas) reserves the right to modify the products and/or specifications described herein at any time and at Navitas’ sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied. This document is presented only as a guide and does not convey any license under intellectual property rights of Navitas or any third parties. Navitas’ products are not intended for use in applications involving extreme environmental conditions or in life support systems. Products supplied under Navitas Terms and Conditions. Navitas Semiconductor, Navitas, GaNFast and associated logos are registered trademarks of Navitas. Copyright ©2018 Navitas Semiconductor Inc. All rights reserved Navitas Semiconductor Inc., 2101 E El Segundo Blvd, Suite 201, El Segundo, California 90245, USA. Final Datasheet 21 Contact info@navitassemi.com Rev 5-15-2018