IS31FL3246
36-CHANNEL LED DRIVER
October 2021
GENERAL DESCRIPTION
FEATURES
IS31FL3246 is comprised of 36 constant current
channels, each channel can be pulse width modulated
(PWM) by total 8 bits+10 bits (261890 steps) for
smooth LED brightness control or color mixing control,
8 bits PWM (LFP) operate at 127Hz (can be disabled),
10 bits (HFP) operate at 32kHz, to minimize the
audible noise. The output current of each channel can
be set at up to 25mA (Max.), all channels are grouped
as G group(OUT1, OUT4, OUT7...), R group (OUT2,
OUT5, OUT8...) , B group (OUT3, OUT6, OUT9...) and
each group has a 8 bits output current control register
which allows fine tuning the current for rich global RGB
color mixing.
Proprietary programmable technology is used to
minimize audible noise caused by MLCC decoupling
capacitors. All registers can be programmed via a high
speed I2C bus interface (1MHz).
The chip can be turned off by pulling the SDB pin low
or by using the software shutdown feature to reduce
power consumption. The rising edge of the SDB pin will
reset the I2C bus module.
IS31FL3246 is available in QFN-44 (5mm×5mm) and
eTQFP-48. It operates from 2.7V to 5.5V over the
temperature range -40°C to +125°C.
2.7V to 5.5V supply
Pin to Pin with IS31FL3236A/IS31FL3237
(QFN-44, 5mm×5mm)
I2C with register address automatic increment
Four selectable I2C addresses
SDB rising edge reset I2C module
Resistor sets operating current of 25mA (Max.)
Accurate color rendition
- Three 8-bit global DC current adjust
- 8-bit DC current adjust for all green channels
- 8-bit DC current adjust for all red channels
- 8-bit DC current adjust for all blue channels
- Each channel total 8-bit+10-bit PWM (261890
steps)
- 8-bit PWM at 127Hz/254Hz/508Hz (LFP)
-10-bit/8-bit PWM at 32kHz (8-bit mode can be
at 64kHz or 128kHz, HFP)
Group dimming to reduce RGB coding
EMI reduction technology
- Selectable 6 phase delay
- Selectable 180 degree clock phase
-40°C to +125°C extended industrial temperature
range
APPLICATIONS
Lumissil Microsystems – www.lumissil.com
Rev. C, 10/08/2021
Hand-held devices for LED display
LED in home appliances
1
IS31FL3246
TYPICAL APPLICATION CIRCUIT
*Note 1
*Note 1
VCC = VBattery
VLED+ = VBattery
VCC
1μF
OUT1_G1
AD
0.1μF
OUT2_R1
*Note 2
OUT3_B1
VBUS
2kΩ
2kΩ
SDA
Micro
Controller
SCL
IS31FL3246
SDB
100kΩ 0.1μF
OUT34_G12
ISET
RISET
3.3kΩ
GND
Figure 1
OUT35_R12
OUT36_B12
Typical Application Circuit (VCC=VBattery)
*Note 1
*Note 3
VCC = 5V
VCC
1μF
0.1μF
AD
VLED+ = 5V
OUT1_G1
91Ω
OUT2_R1
*Note 2
33Ω
VBUS
2kΩ
33Ω
*Note 1
OUT3_B1
2kΩ
SDA
Micro
Controller
SCL
IS31FL3246
SDB
100kΩ 0.1μF
33Ω
OUT34_G12
91Ω
ISET
RISET
3.3kΩ
OUT35_R12
33Ω
GND
Figure 2
OUT36_B12
Typical Application Circuit (VCC=5V)
Note 1: VLED+ can be the same or less than VCC voltage.
Note 2: VBUS is the pull up voltage for the IS31FL3246 I2C interface, which is usually the same as the micro controller's VCC. If the IS31FL3246
VCC= 5V and VBUS is lower than 2.8V, recommend using an I2C level shift circuit to avoid a high shut down current (ISD). For example with VBUS=
1.8V, if the IS31FL3246 VCC= 4V the ISD= 43µA (Typ.) or if VCC= 5V the ISD=111µA (Typ.).
Note 3: These optional resistors are for offloading the thermal dissipation (P= I2R) away from the IS31FL3246(values are for VLED+= 5V).
Note 4: The output current is set up to 23mA when RISET= 3.3kΩ. The maximum global output current can be set by external resistor, RISET.
Please refer to the detail application information in RISET section.
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Rev. C, 10/08/2021
2
IS31FL3246
PIN CONFIGURATION
OUT3_B1 1
33 OUT34_G12
OUT4_G2 2
32 OUT33_B11
OUT5_R2 3
31 OUT32_R11
OUT6_B2 4
30 OUT31_G11
OUT7_G3 5
29 OUT30_B10
OUT8_R3 6
28 OUT29_R10
OUT9_B3 7
27 OUT28_G10
37 OUT35_R12
38 OUT36_B12
39 SDB
23 OUT24_B8
40 AD
OUT13_G5 11
41 VCC
24 OUT25_G9
42 GND
OUT12_B4 10
43 GND
25 OUT26_R9
44 ISET
OUT11_R4 9
45 SDA
26 OUT27_B9
46 SCL
OUT10_G4 8
48 OUT2_R1
QFN-44
Pin Configuration (Top View)
47 OUT1_G1
Package
OUT3_B1 1
36 OUT34_G12
OUT4_G2 2
35 OUT33_B11
OUT5_R2 3
34 OUT32_R11
GND 4
OUT6_B2 5
32 OUT31_G11
OUT7_G3 6
31 OUT30_B10
OUT8_R3 7
30 OUT29_R10
OUT9_B3 8
29 OUT28_G10
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Rev. C, 10/08/2021
OUT23_R8 24
OUT21_B7 22
OUT22_G8 23
OUT20_R7 21
GND 19
25 OUT24_B8
OUT19_G7 20
OUT13_G5 12
GND 18
26 OUT25_G9
OUT18_B6 17
OUT12_B4 11
OUT17_R6 16
27 OUT26_R9
OUT15_B5 14
28 OUT27_B9
OUT11_R4 10
OUT16_G6 15
OUT10_G4 9
OUT14_R5 13
eTQFP-48
33 GND
3
IS31FL3246
PIN DESCRIPTION
No.
Pin
Description
1~3,5~17
OUT3 ~ OUT18
Output channel 3~18 for LEDs.
17,39
4,18,19,
33,42,43
GND
Ground.
18~35
20~32,
34~38
OUT19 ~ OUT36
Output channel 19~36 for LEDs.
36
39
SDB
Shutdown the chip when pulled low.
37
40
AD
I2C address setting.
38
41
VCC
Power supply.
40
44
ISET
Input terminal used to connect an external
resistor. This regulates the global output
current.
41
45
SDA
I2C serial data.
42
46
SCL
I2C serial clock.
43,44
47,48
OUT1, OUT2
Output channel 1, 2 for LEDs.
Thermal Pad
Connect to GND.
QFN
eTQFP
1~16
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Rev. C, 10/08/2021
4
IS31FL3246
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY
IS31FL3246-QFLS4-TR
IS31FL3246-TQLS4-TR
IS31FL3246-TQLS4
QFN-44, Lead-free
eTQFP-48, Lead-free
eTQFP-48, Lead-free
2500/Reel
2500/Reel
250/Tray
Copyright © 2021 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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Rev. C, 10/08/2021
5
IS31FL3246
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at SCL, SDA, SDB, OUT1 to OUT36
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4-layer standard test PCB
based on JESD 51-2A), θJA
ESD (HBM)
ESD (CDM)
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~ +150°C
-40°C ~ +125°C
33.1°C/W (QFN)
38.8°C/W (eTQFP)
± 8kV
± 750V
Note 5: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Typical values are TA = 25°C, VCC = 5V.
Symbol
VCC
Parameter
Condition
Supply voltage
VOUT= 0.8V, RISET= 3kΩ, GCCX= 0xFF,
FMS= “10” (Note 6)
Output current
VOUT= 0.8V, RISET= 3.3kΩ,
GCCX= 0xFF, FMS= “10”
ΔIMAT
Output current error
between bits (Note 7)
RISET= 3.3kΩ, GCCx= 0xFF, FMS= “10”,
HFP_L= 0x00, VCC=5V, IOUT= 23mA
ΔIACC
Output current error
between devices (Note
8)
RISET= 3.3kΩ, GCCx= 0xFF, FMS= “10”,
HFP_L= 0x00, VCC=5V, IOUT= 23mA
VHR
Headroom voltage
RISET= 3.3kΩ, GCCx= 0xFF, FMS= “10”,
HFP_L= 0x00, VCC=5V, IOUT= 23mA
ICC
RISET= 3.3kΩ, GCCx= 0xFF, FMS= “11”,
Quiescent power supply VCC=3.6V,PMS= “0”, HFP=32kHz
current
RISET= 3.3kΩ, GCCx= 0xFF, FMS= “11”,
VCC=5V,PMS= “0”, HFP=32kHz
ISD
Shutdown current
Typ.
2.7
Maximum output current
IOUT
Min.
Max.
Unit
5.5
V
25.3
21.16
23
mA
24.84
mA
-7
7
%
-3
3
%
0.3
0.5
V
2.8
4
mA
3.3
4.5
mA
RISET= 3.3kΩ, VSDB= 0V or software
shutdown, VCC= 3.6V
0.9
1.6
μA
RISET= 3.3kΩ, VSDB= 0V or software
shutdown, VCC= 5V
2
3
μA
fOUT_H
PWM high frequency
PMS= “1”
30.5
32.5
34.5
kHz
fOUT_L
PWM low frequency
PMS= “1”
119.2
126.9
134.7
Hz
TSD
Thermal shutdown
(Note 9)
165
°C
TSD_HY
Thermal shutdown
hysteresis
(Note 9)
20
°C
Logic Electrical Characteristics (SDA, SCL, SDB, AD)
VIL
Logic “0” input voltage
VCC= 2.7V~5.5V
VIH
Logic “1” input voltage
VCC= 2.7V~5.5V
IIL
Logic “0” input current
VINPUT= 0V (Note 9)
5
nA
IIH
Logic “1” input current
VINPUT= VCC (Note 9)
5
nA
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Rev. C, 10/08/2021
0.4
1.4
V
V
6
IS31FL3246
DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 9)
Symbol
Parameter
Fast Mode
Min.
fSCL
Serial-clock frequency
-
tBUF
Bus free time between a STOP and a START
1.3
condition
Typ.
Fast Mode Plus
Max. Min.
Typ.
Max.
Units
400
-
1000
kHz
-
0.5
-
μs
tHD, STA Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT Data hold time
-
-
-
-
μs
tSU, DAT Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals, receiving
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals, receiving
-
300
-
120
ns
Note 6: The recommended minimum value of RISET is 3kΩ.
Note 7: IOUT mismatch (bit to bit) △IMAT is calculated:
I MAT
I OUTn (n 1 ~ 36)
1 100%
I OUT 1 I OUT 2 ... I OUT 36
36
Note 8: IOUT accuracy (device to device) △IACC is calculated:
I ACC
I OUT1 I OUT 3 ... I OUT 36
I OUT ( IDEAL) )
(
36
100%
I OUT ( IDEAL)
Where IOUT(IDEAL)= 23mA when RISET= 3.3kΩ.
Note 9: Guaranteed by design.
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Rev. C, 10/08/2021
7
IS31FL3246
FUNCTIONAL BLOCK DIAGRAM
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Rev. C, 10/08/2021
8
IS31FL3246
DETAILED DESCRIPTION
I2C INTERFACE
The IS31FL3246 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3246 has a 7-bit slave
address (A7:A1), followed by the R/W bit, A0. Set A0 to
“0” for a write command and set A0 to “1” for a read
command. The value of bits A1 and A2 are decided by
the connection of the AD pin. The complete slave
address is:
Table 1 Slave Address (Write Only):
Bit
A7:A3
A2:A1
A0
Value
0110 0
AD
0
AD connected to GND, AD = 00;
AD connected to VCC, AD = 11;
AD connected to SCL, AD = 01;
AD connected to SDA, AD = 10;
The SCL line is uni-directional. The SDA line is
bi-directional (open-drain) with a pull-up resistor
(typically 2kΩ). The maximum clock frequency specified
by the I2C standard is 1MHz. In this discussion, the
master is the microcontroller and the slave is the
IS31FL3246.
The timing diagram for the I2C is shown in Figure 3.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the master
checks for the IS31FL3246’s acknowledge. The master
releases the SDA line high (through a pull-up resistor).
Then the master sends an SCL pulse. If the
IS31FL3246 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the SDA
line is not low, then the master should send a “STOP”
signal (discussed later) and abort the transfer.
Following acknowledge of IS31FL3246, the register
address byte is sent, most significant bit first.
IS31FL3246 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3246 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
ADDRESS AUTO INCREMENT
To write multiple bytes of data into IS31FL3246, load
the address of the data register that the first data byte
is intended for. During the IS31FL3246 acknowledge of
receiving the data byte, the internal address pointer will
increment by one. The next data byte sent to
IS31FL3246 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS31FL3246
(Figure 6).
READING OPERATION
Most of the registers can be read.
To read the register, after I2C start condition, the bus
master must send the IS31FL3246 device address with
____
the R/W bit set to “0”, followed by the register address
which determines which register is accessed. Then
restart I2C, the bus master should send the
____
IS31FL3246 device address with the R/W bit set to “1”.
Data from the register defined by the command byte is
then sent from the IS31FL3246 to the master (Figure
7).
Figure 3 Interface Timing
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Rev. C, 10/08/2021
9
IS31FL3246
Figure 4 Bit Transfer
Figure 5 Writing to IS31FL3246 (Typical)
Figure 6 Writing to IS31FL3246 (Automatic Address Increment)
Figure 7 Reading from IS31FL3246
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Rev. C, 10/08/2021
10
IS31FL3246
REGISTER DEFINITIONS
Table 2 Register Function
Address
Name
00h
Function
R/W
Table Default
Control Register
Power control register
R/W
3
01h~48h
High Frequency PWM(HFP) Duty
Register
OUT [36:1] high frequency PWM
register bytes
R/W
5
49h~6Ch
Low Frequency PWM(LFP) Duty
Register
OUT [36:1] low frequency PWM
register byte
R/W
6
6Dh
Update Register
Update the HFP & LFP data
W
-
6Eh
Global Current Control Register_G Global current of all green channels
R/W
9
6Fh
Global Current Control Register_R
Global current of all red channels
R/W
10
70h
Global Current Control Register_B
Global current of all blue channels
R/W
11
71h
Phase Delay and Clock Phase
Register
Phase Delay and Clock Phase
R/W
12
7Fh
Reset Register
Reset all registers
W
-
Table 3 00h Control Register
Bit
D7
Name
-
Default
0
D6
D5:D4 D3:D2
RGBM HFPS
0
00
D1
D0
-
PMS
SSD
00
0
0
The Control Register sets software shutdown mode,
pulse width modulated (PWM) high/low frequency and
PWM resolution.
LFP : 8-bit
127 Hz or 254 Hz or 508 Hz
High=OFF
Low=ON
Low=ON
High=OF F
High=OF F
Low =ON
High=OFF
Low =ON
0000
0000
OUT4~6...OUT34~36) control by same PWM register.
PWM map in 12 RGB as show in Table 8.
When PMS = “1”, no matter how HFPS is set, HFP
(high frequency PWM) is 32kHz, LFP(low frequency
PWM) is 127Hz.
When PMS = “0” (8-bit mode), HFPS will decide the
internal oscillator clock frequency and the PWM output
PWM frequency. Table 4 lists the options of PWM
frequency.
SSD
0
1
Software Shutdown Enable
Software shutdown mode
Normal operation
PMS
0
1
High PWM freqyency Resolution
8bit mode
10bit mode
HFPS
00
01
1x
High Frequency PWM Select
32kHz
64kHz
128kHz
RGBM
0
RGB Register Mode Select
36 Channel Mode (registers are controlled
as table 7)
12 RGB Mode (registers are controlled as
table 8)
High=OF F
Low =ON
HFP : 8-bit o r 10-bit
32kHz/64kHz/128 kHz
If HFP set to 10-bit, it only supports HFP=32kHz, LFP=127Hz
If HFP set to 8-bit, it supports
HFP=32kHz, LFP=127Hz
HFP=64kHz, LFP=254Hz
HFP=128kHz, LFP=508Hz
Each 1/256 of LFP contains 0/1024~1024/1024 of HFP
Figure 8 PWM Timing Diagram
Each channel can be (PWM) by total 8bits+10bits
(261890 steps) for smooth LED brightness control or
color mixing control, 8 bits PWM(LFP) operate at
127Hz(can be disabled), 10 bits(HFP) operate at
32kHz.
When RGBM = “0”, each of the 36 channels are
controlled by it’s own PWM register. PWM map in 36
channels as show in Table 7. When RGBM = “1”, 36
channels compose into 12 RGB combinations, all 3
channels in one RGB combinations (OUT1~3,
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Rev. C, 10/08/2021
1
11
IS31FL3246
Table 4 PWM Frequency
OSC
PMS
HFPS
(MHz)
(“1”) 10-bit
xx
(“0”) 8-bit
32
LFP (Hz)
HFP (kHz)
127
32
00
8
127
32
01
16
254
64
1x
32
508
128
GCCR ( 6 Fh )
D7:D4
D3:D2
Name
-
FMS
Default
0000
00
FMS
00
01
10
11
D1:D0
GCCB ( 70 h )
HFP_L
0000 0000
PWM Frequency Mode Select
HFP + LFP
Only HFP, LFP=256
DC Mode, no PWM, output always on
Channel Shutdown mode
HFP_H High Frequency PWM High Byte Duty Value
(0x00~0x03)
HFP_L High Frequency PWM Low Byte Duty Value
(0x00~0xFF)
Each output has 8 bits (N=256)/10 bits (N=1024) to
modulate the PWM duty in 256/1024 steps. If using 8
bit PWM resolution, PMS= “0” and only HFP_L bits
need to be set.
IOUT and the value of the HFP and LFP Registers
decide the average current of each LED noted ILED.
IOUT is computed by Formula (1):
I OUTx I OUT ( MAX )
GCCx
256
(1)
Where x = R, G or B, IOUT(MAX) is the maximum output
current decided by RISET (Check RISET section for more
information), GCCx if the GCCG (6Eh), RCCR (6Fh)
and GCCB (70h)(6Eh is for G-group channels (OUT1,
OUT4…OUT34). 6Fh is for R-group channels (OUT2,
OUT5…OUT35). 70h is for B-group channels (OUT3,
OUT6…OUT36)). Please refer to the detail information
in Table 7.
GCCG ( 6 Eh )
7
D[ n ] 2
n
n
(3)
7
D[ n ] 2
n
(4)
n0
ILED computed by Formula (5):
HFP LFP
I OUT (5)
N
256
I LED
HFP
9
D[ n ] 2
n
(6)
n
(7)
n 0
LFP
7
D[ n ] 2
n0
D7:D0
HFP_H
(only enable in
10-bit mode)
00
D[ n ] 2
n0
Table 5 01h~48h High Frequency PWM Duty
Register
01h (03h,
Reg
02h (04h, 06h…)
05h…)
Bit
7
Where HFP is the high frequency PWM Duty of each
output (01h~48h), and LFP is the low frequency PWM
Duty of each output (4Ah~6Ch), N=256/1024 (8/10 bit
PWM resolution), If using 8 bit PWM resolution (PMS=
“0”), only HFP_L bits need to be set and HFP_H need
to be set to ‘00’.
For example: RISET=3.3kΩ, GCCG=0xFF, GCCR=0x80,
GCCB=0x40, LFP=0xFF, PMS= “1” (10-bit PWM
resolution), HFP_H=0x03, HFP_L=0xFF, IOUT(MAX)=
23.18mA
255
(1)
23 mA
256
128
I OUT ( MAX )
11 .5 mA (1)
256
64
I OUT ( MAX )
5 . 76 mA (1)
256
I OUTG I OUT ( MAX )
I OUTR
I OUTB
HFP
9
D[ n ] 2
n
1023
(6)
n
255
(7)
n 0
LFP
7
D[ n ] 2
n0
N= 1024
1023 255
23 mA 23 mA
1024 256
1023 255
11 . 5 mA 11 .5 mA
1024 256
I LEDG
I LEDR
I LEDB
1023 255
5 . 76 mA 5 .76 mA
1024 256
(5)
If
RISET=3.3kΩ,
GCCG=0xFF,
GCCR=0x80,
GCCB=0x40, LFP=0xFF, PMS= “0” (8-bit PWM
resolution), HFP_H=0x03, HFP_L=0xFF, IOUT(MAX)=
23.18mA
(2)
n0
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Rev. C, 10/08/2021
12
IS31FL3246
255
(1)
23 mA
256
128
I OUT ( MAX )
11 .5 mA (1)
256
64
I OUT ( MAX )
5 . 76 mA (1)
256
I OUTG I OUT ( MAX )
I OUTR
I OUTB
HFP
7
D[ n ] 2
n
255
(6)
n0
LFP
7
D [ n ] 2 n 255
(7)
n0
N= 256
255 255
23 mA 23 mA
256 256
255 255
I LEDR
11 .5 mA 11 . 5 mA
256 256
255 255
I LEDB
5 .76 mA 5 . 76 mA (5)
256 256
I LEDG
Lumissil Microsystems – www.lumissil.com
Rev. C, 10/08/2021
Table 6
Register
49h~6Ch
Low Frequency PWM Duty
Bit
D7:D0
Name
LFP
Default
0000 0000
Each output modulated by the 8bits low frequency
PWM duty in 256 steps.
IOUT is computed by Formula (1):
I OUTx I OUT ( MAX )
I LED
GCCx
256
HFP LFP
I OUTx
N
256
(1)
(5)
Where x = R, G or B, IOUT(MAX) is the maximum output
current decided by RISET (Check RISET section for more
information), GCCx if the GCCG (6Eh), RCCR (6Fh)
and GCCB (70h) (6Eh is for G-group channels (OUT1,
OUT4…OUT34). 6Fh is for R-group channels (OUT2,
OUT5…OUT35). 70h is for B-group channels (OUT3,
OUT6…OUT36)).
13
IS31FL3246
Table 7 PWM & GCCx Register Map - 36 Channel
Mode (RGBM = “0”)
OUT
HFP_H
HFP_L
LFP
GCCx
1
02h
01h
49h
6Eh
2
04h
03h
4Ah
6Fh
3
06h
05h
4Bh
70h
4
08h
07h
4Ch
6Eh
5
0Ah
09h
4Dh
6Fh
6
0Ch
0Bh
4Eh
70h
7
0Eh
0Dh
4Fh
6Eh
8
10h
0Fh
50h
6Fh
9
12h
11h
51h
70h
10
14h
13h
52h
6Eh
11
16h
15h
53h
6Fh
12
18h
17h
54h
70h
13
1Ah
19h
55h
6Eh
14
1Ch
1Bh
56h
6Fh
15
1Eh
1Dh
57h
70h
16
20h
1Fh
58h
6Eh
17
22h
21h
59h
6Fh
18
24h
23h
5Ah
70h
19
26h
25h
5Bh
6Eh
20
28h
27h
5Ch
6Fh
21
2Ah
29h
5Dh
70h
22
2Ch
2Bh
5Eh
6Eh
23
2Eh
2Dh
5Fh
6Fh
24
30h
2Fh
60h
70h
25
32h
31h
61h
6Eh
26
34h
33h
62h
6Fh
27
36h
35h
63h
70h
28
38h
37h
64h
6Eh
29
3Ah
39h
65h
6Fh
30
3Ch
3Bh
66h
70h
31
3Eh
3Dh
67h
6Eh
32
40h
3Fh
68h
6Fh
33
42h
41h
69h
70h
34
44h
43h
6Ah
6Eh
35
46h
45h
6Bh
6Fh
36
48h
47h
6Ch
70h
Lumissil Microsystems – www.lumissil.com
Rev. C, 10/08/2021
Table 8 PWM & GCCx Register Map - 12 RGB
Mode (RGBM = “1”)
RBG
OUT
HFP_H HFP_L LFP GCCx
Group
1
RGB
Group 1
RGB
Group 2
RGB
Group 3
RGB
Group 4
RGB
Group 5
RGB
Group 6
RGB
Group 7
RGB
Group 8
RGB
Group 9
RGB
Group 10
RGB
Group 11
RGB
Group 12
49h
6Eh
4Ah
6Fh
3
4Bh
70h
4
4Ch
6Eh
4Dh
6Fh
6
4Eh
70h
7
4Fh
6Eh
50h
6Fh
9
51h
70h
10
52h
6Eh
53h
6Fh
12
54h
70h
13
55h
6Eh
56h
6Fh
15
57h
70h
16
58h
6Eh
59h
6Fh
18
5Ah
70h
19
5Bh
6Eh
5Ch
6Fh
21
5Dh
70h
22
5Eh
6Eh
5Fh
6Fh
24
60h
70h
25
61h
6Eh
62h
6Fh
27
63h
70h
28
64h
6Eh
65h
6Fh
30
66h
70h
31
67h
6Eh
68h
6Fh
33
69h
70h
34
6Ah
6Eh
6Bh
6Fh
6Ch
70h
2
5
8
11
14
17
20
23
26
29
32
35
36
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
01h
03h
05h
07h
09h
0Bh
0Dh
0Fh
11h
13h
15h
17h
14
IS31FL3246
6Dh Update Register
When SDB= “H” and SSD= “1”, a write of “0000 0000”
to 6Dh is to update the PWM Register (01h~6Ch)
values.
Table 12 71h Phase Delay and Clock Phase
Register
Bit
Name
Default
Table 9 6Eh Global Current Control Register-G
D7:D0
Name
GCCG
Default
0000 0000
Table 10 6Fh Global Current Control Register-R
D7:D0
Name
GCCR
Default
0000 0000
Table 11 70h Global Current Control Register-B
Bit
D7:D0
Name
GCCB
Default
0000 0000
The Global Current Control Register modulates all
channels DC current which is noted as IOUT in 256
steps.
6Eh (GCCG) is for G-group channels (OUT1,
OUT4…OUT34). 6Fh (GCCR) is for R-group channels
(OUT2, OUT5…OUT35). 70h (GCCB) is for B-group
channels (OUT3, OUT6…OUT36).
GCCx control the IOUT as shown in Formula (1).
D[ n ] 2 n
(5)
n0
If GCCx=0xFF,
I OUTx I OUT ( MAX )
255
256
If GCCx=0x01,
I OUTx I OUT ( MAX )
HLS
0
1
Bit
7
D6 D5
D4
D3
D2
D1
D0
PDE HLS PS6 PS5 PS4 PS3 PS2 PS1
0
0
0
0
0
0
0
0
IS31FL3246 features a 6 phase delay function, when
this bit is set, the phase delay function is enabled.
Bit
GCCx
D7
1
256
Where x = R, G or B, IOUT(MAX) is the maximum output
current decided by RISET (Check RISET section for more
information).
Group Phase Delay Select
6 Group Phase Delay operate at low
frequency PWM (LFP)
6 Group Phase Delay operate at high
frequency PWM (HFP)
PDE
0
1
Phase Delay Enable
Phase delay disable
Phase delay enable
PS[n]
0
1
Clock Phase Select
Clock Phase Select disable
Clock Phase Select enable
Phase Delay separates 36 outputs as 6 groups,
OUT1~OUT6 as group 1, OUT7~OUT12 as group
2…OUT31~OUT36 as group 6. When Phase Delay is
enabled, group 2 has a 1/(6×fOUT) time delay than
group 1, group 3 also has a 1/(6×fOUT) time delay than
group 2, group 4 also has a 1/(6×fOUT) time delay than
group 3, and so on.
For each group of 6 outputs there is a Clock Phase
option PS[n] (n=1~6), when PSn is set to “1”,
OUT[1+(n-1)×6], OUT[3+(n-1)×6], OUT[5+(n-1)×6]
keep the phase, phase 1, the turning on edge of the
PWM pulse is fixed from starting of PWM cycle, but
OUT[2+(n-1)×6], OUT[4+(n-1)×6], OUT[6+(n-1)×6]
change to phase 2, the turning off edge of the PWM
pulse is fixed from ending of PWM cycle as fiure 13,
the rising and falling edges will cancel the power ripple.
IS31FL3742 operates both at PWM frequency at
127Hz~504Hz (LFP) and 32kHz~128kHz, HLS bit can
select the Group Phase Delay function operating
frequency. When HLS= “0”, 6 Group Phase Delay
operate at low frequency PWM (LFP), When HLS= “1”,
6 Group Phase Delay operate at high frequency PWM
(HFP).
Phase Delay feature and Clock Phase options can
work together to minimize the voltage ripple of LED
power supply. Check Phase Delay and Clock Phase
section for more information
7Fh Reset Register
A write of “0000 0000” to 7Fh will reset all registers to
their default values.
Lumissil Microsystems – www.lumissil.com
Rev. C, 10/08/2021
15
IS31FL3246
APPLICATION INFORMATION
RISET
The maximum output current IOUT(MAX) of OUT1~OUT36
can be adjusted by the external resistor, RISET, as
described in Formula (8).
I OUT ( MAX ) x
V ISET
R ISET
(8)
x = 78.25, VISET = 0.97V.
The recommended minimum value of RISET is 3kΩ.
When RISET=3.3kΩ, IOUT(MAX)=23mA
When RISET=3kΩ, IOUT(MAX)=25.3mA
CURRENT SETTING
The maximum output current is set by the external
resistor RISET. The Global Current Control register
GCCX can be used to set a lower current than set by
RISET.
The IS31FL3246 provides independent gradation
control for each of the red, green and blue colors. The
Global Current Control Register modulates all channels
DC current which is noted as IOUT in 256 steps.
6Eh is for G-group channels (OUT1, OUT4…OUT34).
6Fh is for R-group channels (OUT2, OUT5…OUT35).
70h is for B-group channels (OUT3, OUT6…OUT36).
PWM CONTROL
Each channel can be (PWM) by total 8bits+10bits
(261890 steps) for smooth LED brightness control or
color mixing control, 8 bits PWM (LFP) operate at
127Hz (can be disabled), 10 bits (HFP) operate at
32kHz.
LFP : 8-bit
127 Hz or 254 Hz or 508 Hz
High=OFF
Low=ON
Low=ON
High=OF F
Low =ON
High=OFF
High=OF F
Low =ON
High=OF F
Low =ON
HFP : 8-bit o r 10-bit
32kHz/64kHz/128 kHz
If HFP set to 10-bit, it only supports HFP=32kHz, LFP=127Hz
If HFP set to 8-bit, it supports
HFP=32kHz, LFP=127Hz
HFP=64kHz, LFP=254Hz
HFP=128kHz, LFP=508Hz
Each 1/256 of LFP contains 0/1024~1024/1024 of HFP
Figure 9
work together, the total PWM steps are 8-bit+10-bit
(261890 steps).
Writing new data continuously to the PWM registers
can modulate the brightness of the LEDs to achieve
color mixing and breathing effect.
PWM FREQUENCY SELECT
The IS31FL3246 output channels operate with a
default 8 bit PWM resolution mode and the low
frequency PWM at 127Hz and high frequency at
32kHz (the oscillator frequency is 8MHz). Because all
the OUTx channels are synchronized, the DC power
supply will experience large instantaneous current
surges when the OUTx channels turn ON. These
current surges will generate an AC ripple on the power
supply which cause stress to the decoupling
capacitors. When the AC ripple is applied to a
monolithic ceramic capacitor chip (MLCC) it will
expand and contract causing the PCB to flex and
generate audible hum in the range of between 200Hz
to 18kHz, to avoid this hum, there are many
countermeasures, such as selecting the capacitor type
and value which will not cause the PCB to flex and
contract.
An additional option for avoiding audible hum is to set
the
IS31FL3246’s
output
PWM
frequency
above/below the audible range. The Control Register
(00h) can be used to set the switching frequency to
127Hz~504Hz as shown in Table 4, all the high
frequency PWM (HFP) is higher than 20kHz, and can
select lower low frequency PWM (LFP) to reduce the
audible hum.
12 RGB COMBINATIONS
36 channels control by independent PWM registers as
show in Table 7, or 36 channels compose into 12 RGB
combinations. All 3 channels in one RGB
combinations
(OUT1~3,
OUT4~6...OUT34~36)
controlled by the same PWM register. PWM map in 12
RGB as show in Table 8.
PHASE DELAY and CLOCK PHASE
To reduce audible noise due to PWM switching, the
IS31FL3246 features Phase Delay and Clock Phase
schemes. When Phase Delay and Clock Phase are
disabled (default) all of the outputs turn on
simultaneously causing large current draw from the
ceramic capacitors and pausible audible noise.
PWM Timing Diagram
The Low Frequency PWM Duty Registers (49h~6Ch)
can change a low frequency PWM (LFP) duty with
between 0/256 and 255/256. Each of the LFP’s 1/256
unit contain another PWM method, HFP, 8-bit or 10-bit,
work at 32kHz or higher frequency, change the PWM
duty from 0/1024~1023/1024. When LFP and HFP
Lumissil Microsystems – www.lumissil.com
Rev. C, 10/08/2021
16
IS31FL3246
VCC
VCC
Ton
OUT1~OUT6
Clock Phase 1
Toff
OUT[1+(n-1)*6] Ton
Toff
OUT7~OUT12
OUT[2+(n-1)*6] Ton
Toff
OUT13~OUT18
OUT[3+(n-1)*6] Ton
Toff
OUT19~OUT24
OUT[4+(n-1)*6] Ton
Toff
OUT25~OUT30
OUT[5+(n-1)*6] Ton
Toff
OUT[6+(n-1)*6] Ton
OUT31~OUT36
Toff
1/fOUT
Turn on together resulting power ripple
1/fOUT
Turn on together resulting power ripple
Figure 12
Figure 10
Phase Delay and Clock Phase disable for both LFP and
HFP
The PDE bit of register 71h will enable the Phase
Delay function so at power-on the OUTx channel will
not all turn on at the same time to minimize peak load
current, resulting in reduced voltage ripple on the LED
power supply rail. Phase Delay separates the 36
outputs as 6 groups, OUT1~OUT6 as group 1,
OUT7~OUT12 as group 2…OUT31~OUT36 as group
6, when Phase Delay is enabled, group 2 will have a
1/(6×fOUT) time delay than group 1, group 3 will also
have a 1/(6×fOUT) time delay than group 2, and so on.
When PSn is set to “1”, OUT[1+(n-1)×6],
OUT[3+(n-1)×6], OUT[5+(n-1)×6] will keep the phase
1, the turning on edge of the PWM pulse is fixed from
starting of PWM cycle as below, but OUT[2+(n-1)×6],
OUT[4+(n-1)×6], OUT[6+(n-1)×6] will change to phase
2, the turning off edge of the PWM pulse is fixed from
ending of PWM cycle as below, the rising and falling
edges will cancel the power ripple.
VCC
Clock Phase 1
OUT[1+(n-1)*6] Ton
VCC
OUT[2+(n-1)*6]
OUT1~OUT6
OUT[3+(n-1)*6] Ton
OUT7~OUT12
OUT[4+(n-1)*6]
OUT13~OUT18
OUT[5+(n-1)*6] Ton
OUT19~OUT24
OUT[6+(n-1)*6]
OUT25~OUT30
OUT31~OUT36
Ton
Figure 13
Toff
1/fOUT
tDELAY =1/(6*fOUT)
Figure 11
PDE= “1” Phase Delay Enable
PSn= “0” Clock Phase disable
Toff
Clock Phase 2
Toff
Ton
Toff
Toff
Ton
Toff
Toff
Ton
1/fOUT
Rising & Falling edges canceled the power ripple
PSn= “1” Clock Phase enable
Phase Delay feature and Clock Phase options can
work together to minimize the voltage ripple of LED
power supply.
The HLS bit of register 71h can select the Group Phase
Delay schemes to apply on low frequency PWM (LFP)
or high frequency PWM (HFP), if it applys on LFP, it
redudes the LED power supply rail voltage ripple of low
frequency (127Hz~504Hz), if it applys on HFP, it
redudes the LED power supply rail voltage ripple of
high frequency (32kHz~128Hz). Since HFP frequency
is higher than 20kHz and enough to avoid the audible,
it is recommend to choose the schemes to apply on
LFP to reduce the the LED power supply rail voltage
ripple of low frequency (127Hz~504Hz).
Also in each group of outputs, there is a Clock Phase
option PS[n](n=1~6), when PSn of 71h register is set to
“0” (default), all outputs in group n keep the phase 1.
Lumissil Microsystems – www.lumissil.com
Rev. C, 10/08/2021
17
IS31FL3246
If the VCC supply drops below 1.75V but remains
above 0.1V during SDB pulled low, please re-initialize
all Function Registers before SDB pulled high.
1/fOUT
Clock Phase 1
OUT1/3/5 Ton
Toff
Clock Phase 2
OUT2/4/6
Toff
LAYOUT
Ton
The IS31FL3246 consumes lots of power so good
PCB layout will help improve the reliability of the chip.
Please consider below factors when layout the PCB.
tDELAY=1/(6*fOUT)
Clock Phase 1
OUT7/9/11
Ton
Toff
Clock Phase 2
OUT8/10/12
Toff
Power Supply Lines
Ton
When designing the PCB layout, the first pcb trace to
consider is the power supply trace and GND
connections, especially those traces with high current.
Also the digital and analog blocks’ supply line and
GND should be separated to avoid noise from digital
block affecting the analog block.
tDELAY=1/(6*fOUT)
Clock Phase 1
OUT31/33/35
OUT32/34/36
Figure 14
Ton
Toff
Clock Phase 2
Toff
Ton
PDE= “1” Phase Delay enable, PSn= “1” (n=1~6) Clock
Phase Enable
Phase Delay feature and Clock Phase options can
work together to minimize the voltage ripple of LED
power supply.
OPERATING MODE
IS31FL3246 can operate in PWM Mode or DC Mode.
The brightness of each LED can be modulated with
261890 steps by PWM registers. In DC Mode, there is
no PWM and Iout=Iout(MAX) always.
At least one 0.1μF capacitor, if possible with a 1μF
capacitor is recommended to connected to the ground
at power supply pin of the chip, and it needs to close to
the chip and the ground net of the capacitor should be
well connected to the GND plane.
RISET
RISET should be close to the chip and the ground side
should well connect to the GND plane.
Thermal Consideration
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
The over temperature of the chip may result in
deterioration of the properties of the chip. The thermal
pad of IS31FL3246 should connect to GND net and
need to use 9 or 16 vias connect to GND copper area,
the GND area should be as large area as possible to
help radiate the heat from the IS31FL3246.
SHUTDOWN MODE
Current Rating Example
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
For a RISET=3.3kΩ application, the current rating for
each net is as follows:
Software Shutdown
By setting the SSD bit of the Control Register (00h) to
“0”, the IS31FL3246 will operate in software shutdown
mode. When the IS31FL3246 is in software shutdown,
all current sources are switched off, so the LEDs are
OFF but all registers accessible. Typical current
consume is 0.9μA (VCC=3.6V).
Hardware Shutdown
The chip enters hardware shutdown when the SDB pin
is pulled low. All analog circuits are disabled during
hardware shutdown, typical the current consumption is
0.9μA (VCC=3.6V).
• VCC pin maximum current is lower than 10mA when
VCC=5V, but the VLED+ net is provide total current of
all outputs, its current can as much as
23mA×36=828mA, recommend trace width for VCC
pin: 0.20mm~0.3mm, recommend trace width for
VLED+ net: 0.30mm~0.5mm
• Output pins=23mA, recommend trace width is
0.2mm~0.254mm
• All other pins
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