DSP56F801FA80

DSP56F801/D Rev. 13.0, 02/2004 56F801 Technical Data 56F801 16-bit Hybrid Controller • Up to 30 MIPS operation at 60MHz core frequency • 8K × 16-bit words Program Flash • 1K × 16-bit words Program RAM • Up to 40 MIPS operation at 80MHz core frequency • 2K × 16-bit words Data Flash • DSP and MCU functionality in a unified, C-efficient architecture • 1K × 16-bit words Data RAM • 2K × 16-bit words Boot Flash • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • Serial Peripheral Interface (SPI) • General Purpose Quad Timer • JTAG/OnCETM port for debugging • On-chip relaxation oscillator • 11 shared GPIO • 48-pin LQFP Package • Hardware DO and REP loops • 6-channel PWM Module • Two 4-channel, 12-bit ADCs • Serial Communications Interface (SCI) 6 PWM Outputs PWMA RESET Fault Input IRQA 6 VCAPC VDD VSS 2 5* 4 JTAG/ OnCE Port 4 4 A/D1 A/D2 VREF 3 Quad Timer C Program Memory 8188 x 16 Flash 1024 x 16 SRAM Quad Timer D or GPIO Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 1024 x 16 SRAM 2 4 Digital Reg SCI0 or GPIO SPI or GPIO Program Controller and Hardware Looping Unit • • 16-Bit 56800 Core • CGDB XAB1 XAB2 • INTERRUPT CONTROLS 16 COP/ Watchdog ApplicationSpecific Memory & Peripherals • • IPBB CONTROLS 16 COP RESET MODULE CONTROLS ADDRESS BUS [8:0] IPBus Bridge (IPBB) DATA BUS [15:0] *includes TCS pin which is reserved for factory use and is tied to VSS Figure 1. 56F801 Block Diagram © Motorola, Inc., 2004. All rights reserved. Bit Manipulation Unit PLL • XDB2 • Analog Reg Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Address Generation Unit PAB PDB VSSA Low Voltage Supervisor ADC Interrupt Controller VDDA Clock Gen or Optional Internal Relaxation Osc. GPIOB3/XTAL GPIOB2/EXTAL Part 1 Overview 1.1 56F801 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Two 36-bit accumulators including extension bits • 16-bit bidirectional barrel shifter • Parallel instruction set with unique DSP addressing modes • Hardware DO and REP loops • Three internal address buses and one external address bus • Four internal data buses and one external data bus • Instruction set supports both DSP and controller functions • Controller style addressing modes and instructions for compact code • Efficient C compiler and local variable support • Software subroutine and interrupt stack with depth limited only by memory • JTAG/OnCE debug programming interface 1.1.2 Memory • Harvard architecture permits as many as three simultaneous accesses to Program and Data memory • On-chip memory including a low-cost, high-volume Flash solution — 8K × 16 bit words of Program Flash — 1K × 16-bit words of Program RAM — 2K × 16-bit words of Data Flash — 1K × 16-bit words of Data RAM — 2K × 16-bit words of Boot Flash • 1.1.3 2 Programmable Boot Flash supports customized boot code and field upgrades of stored code through a variety of interfaces (JTAG, SPI) Peripheral Circuits for 56F801 • Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime insertion; supports both center- and edge-aligned modes • Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two 4-multiplexed inputs; ADC and PWM modules can be synchronized • General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines) • Serial Communication Interface (SCI) with two pins (or two additional GPIO lines) • Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines) 56F801 Technical Data 56F801 Description • Eleven multiplexed General Purpose I/O (GPIO) pins • Computer-Operating Properly (COP) watchdog timer • One dedicated external interrupt pin • External reset pin for hardware reset • JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging • Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller core clock • Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for lower system cost and two additional GPIO lines 1.1.4 Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • Uses a single 3.3V power supply • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Wait and Stop modes available 1.2 56F801 Description The 56F801 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F801 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM) module. This modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functionality. Complementary operation permits programmable dead-time insertion, 56F801 Technical Data 3 and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width control (0% to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-bycycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The PWM is doublebuffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital Converters. The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility in the choice of either on-chip or externally supplied frequency reference for chip timing operations. Application code is used to select which source is to be used. 1.3 State of the Art Development Environment • Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-touse component-based software application creation with an expert knowledge system. • The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Product Documentation The four documents listed in Table 1 are required for a complete description and proper design with the 56F801. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors. Table 1. 56F801 Chip Documentation Topic 4 Description Order Number DSP56800 Family Manual Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set DSP56800FM/D DSP56F801/803/805/807 User’s Manual Detailed description of memory, peripherals, and interfaces of the 56F801, 56F803, 56F805, and 56F807 DSP56F801-7UM/D 56F801 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56F801/D 56F801 Product Brief Summary description and block diagram of the 56F801 core, memory, peripherals and interfaces DSP56F801PB/D DSP56F801 Errata Details any chip issues that might be present DSP56F801E/D 56F801 Technical Data Data Sheet Conventions 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: 1. Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 13, each table row describes the signal or signals present on a pin. Table 2. Functional Group Pin Allocations Number of Pins Detailed Description Power (VDD or VDDA) 5 Table 3 Ground (VSS or VSSA) 6 Table 4 Supply Capacitors 2 Table 5 PLL and Clock 2 Table 6 Interrupt and Program Control 2 Table 7 Pulse Width Modulator (PWM) Port 7 Table 8 Serial Peripheral Interface (SPI) Port1 4 Table 9 Serial Communications Interface (SCI) Port1 2 Table 10 Analog-to-Digital Converter (ADC) Port 9 Table 11 Quad Timer Module Port 3 Table 12 JTAG/On-Chip Emulation (OnCE) 6 Table 13 Functional Group 1. Alternately, GPIO pins 56F801 Technical Data 5 Power Port Ground Port Power Port Ground Port VDD 4 VSS 5* VDDA 1 VSSA 1 Other Supply Port VCAPC PLL and Clock or GPIO EXTAL (GPIOB2) XTAL (GPIOB3) PWMA0-5 6 2 1 FAULTA0 1 SCLK (GPIOB4) 1 MOSI (GPIOB5) 1 MISO (GPIOB6) 1 SS (GPIOB7) 1 TXD0 (GPIOB0) 1 RXD0 (GPIOB1) SCI0 Port or GPIO 8 ANA0-7 ADCA Port 1 VREF 3 TD0-2 (GPIOA0-2) 1 IRQA 1 1 56F801 TCK TMS JTAG/OnCE Port TDI TDO TRST DE SPI Port or GPIO 1 1 1 1 1 Quad Timer D or GPIO Interrupt/ Program Control RESET 1 1 *includes TCS pin which is reserved for factory use and is tied to VSS Figure 2. 56F801 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parenthesis. 6 56F801 Technical Data Power and Ground Signals 2.2 Power and Ground Signals Table 3. Power Inputs No. of Pins Signal Name Signal Description 4 VDD Power—These pins provide power to the internal structures of the chip, and should all be attached to VDD. 1 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply. Table 4. Grounds No. of Pins Signal Name Signal Description 4 VSS GND—These pins provide grounding for the internal structures of the chip, and should all be attached to VSS. 1 VSSA Analog Ground—This pin supplies an analog ground. 1 TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS. Table 5. Supply Capacitors and VPP No. of Pins Signal Name Signal Type State During Reset 2 VCAPC Supply Supply Signal Description VCAPC—Connect each pin to a 2.2 µFor greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, refer to Section 5.2. 2.3 Clock and Phase Locked Loop Signals Table 6. PLL and Clock No. of Pins Signal Name Signal Type State During Reset 1 EXTAL Input Input External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. GPIOB2 Input/ Output Input Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that can be programmed as an input or output pin. This I/O can be utilized when using the on-chip relaxation oscillator so the EXTAL pin is not needed. 56F801 Technical Data Signal Description 7 Table 6. PLL and Clock (Continued) No. of Pins Signal Name Signal Type State During Reset 1 XTAL Output Chipdriven Signal Description Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more information, please refer to Section 3.5.3. GPIOB3 Input/ Output Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that can be programmed as an input or output pin. This I/O can be utilized when using the on-chip relaxation oscillator so the XTAL pin is not needed. Input 2.4 Interrupt and Program Control Signals Table 7. Interrupt and Program Control Signals State During Reset No. of Pins Signal Name Signal Type 1 IRQA Input (Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. 1 RESET Input (Schmitt) Input Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the hybrid controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. Signal Description To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. 2.5 Pulse Width Modulator (PWM) Signals Table 8. Pulse Width Modulator (PWMA) Signals 8 No. of Pins Signal Name Signal Type State During Reset 6 PWMA0-5 Output Tri-stated 1 FAULTA0 Input (Schmitt) Input Signal Description PWMA0-5— These are six PWMA output pins. FAULTA0— This fault input pin is used for disabling selected PWMA outputs in cases where fault conditions originate offchip. 56F801 Technical Data Serial Peripheral Interface (SPI) Signals 2.6 Serial Peripheral Interface (SPI) Signals Table 9. Serial Peripheral Interface (SPI) Signals State During Reset No. of Pins Signal Name Signal Type 1 MISO Input/ Output Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the highimpedance state if the slave device is not selected. GPIOB6 Input/ Output Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. Signal Description After reset, the default state is MISO. 1 MOSI Input/ Output Input SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. GPIOB5 Input/ Output Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. After reset, the default state is MOSI. 1 SCLK Input/ Output Input SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. GPIOB4 Input/ Output Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SCLK. 1 SS Input Input SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. GPIOB7 Input/ Output Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SS. 56F801 Technical Data 9 2.7 Serial Communications Interface (SCI) Signals Table 10. Serial Communications Interface (SCI0) Signals No. of Pins Signal Name Signal Type State During Reset 1 TXD0 Output Input Transmit Data (TXD0)—SCI0 transmit data output GPIOB0 Input/ Output Input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. Signal Description After reset, the default state is SCI output. 1 RXD0 Input Input Receive Data (RXD0)—SCI0 receive data input GPIOB1 Input/ Output Input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. After reset, the default state is SCI input. 2.8 Analog-to-Digital Converter (ADC) Signals Table 11. Analog to Digital Converter Signals No. of Pins Signal Name Signal Type State During Reset 4 ANA0-3 Input Input ANA0-3—Analog inputs to ADC, channel 1 4 ANA4-7 Input Input ANA4-7—Analog inputs to ADC, channel 2 1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to VDDA-0.3V for optimal performance. Signal Description 2.9 Quad Timer Module Signals Table 12. Quad Timer Module Signals No. of Pins Signal Name Signal Type State During Reset 3 TD0-2 Input/ Output Input TD0-2—Timer D Channel 0-2 GPIOA0-2 Input/ Output Input Port A GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. Signal Description After reset, the default state is the quad timer input. 10 56F801 Technical Data JTAG/OnCE 2.10 JTAG/OnCE Table 13. JTAG/On-Chip Emulation (OnCE) Signals No. of Pins Signal Name Signal Type 1 TCK Input (Schmitt) 1 TMS Input Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG (Schmitt) high internally TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. 1 TDI Input Input, pulled Test Data Input—This input pin provides a serial input data stream to (Schmitt) high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. 1 TDO 1 TRST 1 DE Output State During Reset Signal Description Input, pulled Test Clock Input—This input pin provides a gated clock to low internally synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. Tri-stated Test Data Output—This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Input Input, pulled Test Reset—As an input, a low signal on this pin provides a reset (Schmitt) high internally signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Output Output Debug Event—DE provides a low pulse on recognized debug events. Part 3 Specifications 3.1 General Characteristics The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 14 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. 56F801 Technical Data 11 CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 14. Absolute Maximum Ratings Characteristic Symbol Min Max Unit Supply voltage VDD VSS – 0.3 VSS + 4.0 V All other input voltages, excluding Analog inputs VIN VSS – 0.3 VSS + 5.5V V Analog inputs ANA0-7 and VREF VIN VSSA– 0.3 VDDA+ 0.3 V Analog inputs EXTAL, XTAL VIN VSSA– 0.3 VSSA+ 3.0 V I — 10 mA Current drain per pin excluding VDD, VSS, & PWM ouputs Table 15. Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Supply voltage, digital VDD 3.0 3.3 3.6 V Supply Voltage, analog VDDA 3.0 3.3 3.6 V ADC reference voltage VREF 2.7 – VDDA V TA –40 – 85 °C Ambient operating temperature 12 56F801 Technical Data General Characteristics Table 16. Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 48-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 50.6 °C/W 2 RθJMA 47.4 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) RθJMA (2s2p) 39.1 °C/W 1,2 Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 37.9 °C/W 1,2 Junction to case RθJC 17.3 °C/W 3 Junction to center of case ΨJT 1.2 °C/W 4, 5 I/O pin power dissipation P I/O User Determined W Power dissipation PD P D = (IDD x VDD + P I/O) W PDMAX (TJ - TA) /θJA °C Junction to center of case Notes: 1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. 2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in steady state customer environments. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Section 5.1 from more details on thermal design considerations. 56F801 Technical Data 13 3.2 DC Electrical Characteristics Table 17. DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) VIHC 2.25 — 2.75 V Input low voltage (XTAL/EXTAL) VILC 0 — 0.5 V Input high voltage [GPIOB(2:3)]1 VIH[GPIOB(2:3)] 2.0 — 3.6 V Input low voltage [GPIOB(2:3)]1 VIL[GPIOB(2:3)] -0.3 — 0.8 V Input high voltage (Schmitt trigger inputs)2 VIHS 2.2 — 5.5 V Input low voltage (Schmitt trigger inputs)2 VILS -0.3 — 0.8 V Input high voltage (all other digital inputs) VIH 2.0 — 5.5 V Input low voltage (all other digital inputs) VIL -0.3 — 0.8 V Input current high (pullup/pulldown resistors disabled, VIN=VDD) IIH -1 — 1 µA Input current low (pullup/pulldown resistors disabled, VIN=VSS) IIL -1 — 1 µA Input current high (with pullup resistor, VIN=VDD) IIHPU -1 — 1 µA Input current low (with pullup resistor, VIN=VSS) IILPU -210 — -50 µA Input current high (with pulldown resistor, VIN=VDD) IIHPD 20 — 180 µA Input current low (with pulldown resistor, VIN=VSS) IILPD -1 — 1 µA Nominal pullup or pulldown resistor value RPU, RPD 30 KΩ Output tri-state current low IOZL -10 — 10 µA Output tri-state current high IOZH -10 — 10 µA Input current high (analog inputs, VIN=VDDA)3 IIHA -15 — 15 µA Input current low (analog inputs, VIN=VSSA)3 IILA -15 — 15 µA Output High Voltage (at IOH) VOH VDD – 0.7 — — V Output Low Voltage (at IOL) VOL — — 0.4 V Output source current IOH 4 — — mA Output sink current IOL 4 — — mA IOHP 10 — — mA PWM pin output source current4 14 56F801 Technical Data DC Electrical Characteristics Table 17. DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit PWM pin output sink current5 IOLP 16 — — mA Input capacitance CIN — 8 — pF Output capacitance COUT — 12 — pF VDD supply current IDDT6 Run7 (80MHz operation) — 120 130 mA Run7 (60MHz operation) — 102 111 mA Wait8 — 96 102 mA Stop — 62 70 mA Low Voltage Interrupt, external power supply9 VEIO 2.4 2.7 3.0 V Low Voltage Interrupt, internal power supply10 VEIC 2.0 2.2 2.4 V Power on Reset11 VPOR — 1.7 2.0 V 1. Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant. 2. Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST. 3. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 4. PWM pin output source current measured with 50% duty cycle. 5. PWM pin output sink current measured with 50% duty cycle. 6. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 7. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 8. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL enabled. 9. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V). 11. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates. 56F801 Technical Data 15 160 IDD Digital IDD Analog IDD Total IDD (mA) 120 80 40 0 10 20 30 40 60 50 70 80 Freq. (MHz) Figure 3. Maximum Run IDD vs. Frequency (see Note 7. in Table 17) 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 4 the levels of VIH and VIL for an input signal are shown. VIH Input Signal Low High 90% 50% 10% Midpoint1 Fall Time VIL Rise Time Note: The midpoint is VIL + (VIH – VIL)/2. Figure 4. Input Signal Measurement References Figure 5 shows the definitions of the following signal states: 16 • Active state, when a bus or signal is driven, and enters a low impedance state. • Tri-stated, when a bus or signal is placed in a high impedance state. • Data Valid state, when a signal level has reached VOL or VOH. • Data Invalid state, when a signal level is in transition between VOL and VOH. 56F801 Technical Data Flash Memory Characteristics Data2 Valid Data1 Valid Data1 Data3 Valid Data2 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 5. Signal States 3.4 Flash Memory Characteristics Table 18. Flash Memory Truth Table Mode XE1 YE2 SE3 OE4 PROG5 ERASE6 MAS17 NVSTR8 Standby L L L L L L L L Read H H H H L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H 1. 2. 3. 4. 5. 6. 7. 8. X address enable, all rows are disabled when XE = 0 Y address enable, YMUX is disabled when YE = 0 Sense amplifier enable Output enable, tri-state Flash data out bus when OE = 0 Defines program cycle Defines erase cycle Defines mass erase cycle, erase whole block Defines non-volatile store cycle Table 19. IFREN Truth Table Mode IFREN = 1 IFREN = 0 Read Read information block Read main memory block Word program Program information block Program main memory block Page erase Erase information block Erase main memory block Mass erase Erase both block Erase main memory block 56F801 Technical Data 17 Table 20. Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Figure Program time Tprog* 20 – – us Figure 6 Erase time Terase* 20 – – ms Figure 7 Mass erase time Tme* 100 – – ms Figure 8 Endurance1 ECYC 10,000 20,000 – cycles Data Retention1 @ 5000 cycles DRET 10 30 – years The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time Tnvs* – 5 – us Figure 6, Figure 7, Figure 8 NVSTR hold time Tnvh* – 5 – us Figure 6, Figure 7 NVSTR hold time (mass erase) Tnvh1* – 100 – us Figure 8 NVSTR to program set up time Tpgs* – 10 – us Figure 6 Recovery time Trcv* – 1 – us Figure 6, Figure 7, Figure 8 Cumulative program HV period2 Thv – 3 – ms Figure 6 Program hold time3 Tpgh – – – Figure 6 Address/data set up time3 Tads – – – Figure 6 Address/data hold time3 Tadh – – – Figure 6 1. One cycle is equal to an erase program and read. 2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. 18 56F801 Technical Data Flash Memory Characteristics IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs Tprog Tpgh NVSTR Tpgs Tnvh Trcv Thv Figure 6. Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 7. Flash Erase Cycle 56F801 Technical Data 19 IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 8. Flash Mass Erase Cycle 3.5 External Clock Operation The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator. To generate a reference frequency using the internal crystal oscillator circuit, a reference crystal external to the chip must be connected between the EXTAL and XTAL pins. Paragrahs 3.5.1 and 3.5.4 describe these methods of clocking. Whichever type of clock derivation is used provides a reference signal to a phaselocked loop (PLL) within the 56F801. In turn, the PLL generates a master reference frequency that determines the speed at which chip operations occur. Application code can be set to change the frequency source between the relaxation oscillator and crystal oscillator or external source, and power down the relaxation oscillator if desired. Selection of which clock is used is determined by setting the PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2). If the bit is set to 1, the external crystal oscillator circuit is selected. If the bit is set to 0, the internal relaxation oscillator is selected, and this is the default value of the bit when power is first applied. 3.5.1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 23. Figure 9 shows a recommended crystal oscillator circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 10 no external load capacitors should be used. 20 56F801 Technical Data External Clock Operation The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: CL1 * CL2 CL = CL1 + CL2 12 * 12 + Cs = + 3 = 6 + 3 = 9pF 12 + 12 This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit. EXTAL XTAL Rz Recommended External Crystal Parameters: Rz = 1 to 3 MΩ fc = 8MHz (optimized for 8MHz) fc Figure 9. External Crystal Oscillator Circuit 3.5.2 Ceramic Resonator It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 9 no external load capacitors should be used. EXTAL XTAL Rz Recommended Ceramic Resonator Parameters: Rz = 1 to 3 MΩ fc = 8MHz (optimized for 8MHz) fc Figure 10. Connecting a Ceramic Resonator Note: Motorola recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). 3.5.3 External Clock Source The recommended method of connecting an external clock is given in Figure 11. The external clock source is connected to XTAL and the EXTAL pin is grounded. 56F801 Technical Data 21 56F801 XTAL EXTAL External Clock VSS Figure 11. Connecting an External Clock Signal Table 21. External Clock Operation Timing Requirements3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)1 fosc 0 — 802 MHz Clock Pulse Width3, 4 tPW 6.25 — — ns 1. 2. 3. 4. See Figure 11 for details on using the recommended connection of an external clock driver. May not exceed 60MHz for the DSP56F801FA60 device. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. Parameters listed are guaranteed by design. VIH External Clock 90% 50% 10% 90% 50% 10% tPW tPW VIL Note: The midpoint is VIL + (VIH – VIL)/2. Figure 12. External Clock Timing 3.5.4 Use of On-Chip Relaxation Oscillator An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal are not used. During a 56F801 boot or reset sequence, the relaxation oscillator is enabled by default, and the PRECS bit in the PLLCR word is set to 0 (Section 3.5). If an external oscillator is connected, the relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. When this occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a changeover between internal and external oscillators is required at startup, internal device circuits compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within ±0.25% of 8MHz by trimming an internal capacitor. Bits 0-7 of the IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this preset value to increase or decrease capacitance. The default value of this trim is 128 units, making the power-up default capacitor size 432 units. Each unit added or deleted changes the output frequency by about 0.2%, allowing incremental adjustment until the desired frequency accuracy is achieved. 22 56F801 Technical Data External Clock Operation Table 22. Relaxation Oscillator Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit ∆f — +2 +5 % Frequency Drift over Temp ∆f/∆t — +0.1 — %/oC Frequency Drift over Supply ∆f/∆V — 0.1 — %/V ∆fT — +0.25 — % Frequency Accuracy1 Trim Accuracy 1. Over full temperature range. 8.2 Output Frequency 8.1 8.0 7.9 7.8 7.7 7.6 -40 -25 -5 15 35 55 75 85 Temperature (oC) Figure 13. Typical Relaxation Oscillator Frequency vs. Temperature (Trimmed to 8MHz @ 25oC) 56F801 Technical Data 23 11 10 9 8 7 6 5 0 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 Figure 14. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC 3.5.5 Phase Locked Loop Timing Table 23. PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit fosc 4 8 10 MHz fout/2 40 — 803 MHz PLL stabilization time4 0o to +85oC tplls — 10 — ms PLL stabilization time4 -40o to 0oC tplls — 100 200 ms External reference crystal frequency for the PLL1 PLL output frequency2 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the User Manual. ZCLK = fop 3. Will not exceed 60MHz for the DSP56F801FA60 device. 4. This is the minimum time required after the PLL setup is changed to ensure reliable operation. 24 56F801 Technical Data Reset, Stop, Wait, Mode Select, and Interrupt Timing 3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 24. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit See RESET Assertion to Address, Data and Control Signals High Impedance tRAZ — 21 ns Figure 15 Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 tRA 275,000T 128T — — ns ns RESET De-assertion to First External Address Output tRDA 33T 34T ns Figure 15 Edge-sensitive Interrupt Request Width tIRW 1.5T — ns Figure 16 IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine tIDM 15T — ns Figure 17 IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine tIG 16T — ns Figure 17 IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 tIRI 13T — ns Figure 18 IRQA Width Assertion to Recover from Stop State4 tIW 2T — ns Figure 19 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tIF Figure 15 Figure 19 — — Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tIRQ Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 tII 275,000T 12T ns ns Figure 20 — — 275,000T 12T ns ns Figure 20 — — 275,000T 12T ns ns 1. 2. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: • After power-on reset • When recovering from Stop state 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. 56F801 Technical Data 25 RESET tRA tRAZ tRDA A0–A15, D0–D15 First Fetch PS, DS, RD, WR First Fetch Figure 15. Asynchronous Reset Timing IRQA, IRQB tIRW Figure 16. External Interrupt Timing (Negative-Edge-Sensitive) A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 17. External Level-Sensitive Interrupt Timing 26 56F801 Technical Data Reset, Stop, Wait, Mode Select, and Interrupt Timing IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 18. Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 19. Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0–A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 20. Recovery from Stop State Using IRQA Interrupt Service 56F801 Technical Data 27 3.7 Serial Peripheral Interface (SPI) Timing Table 25. SPI Timing1 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Cycle time Master Slave Symbol tELD Enable lag time Master Slave tELG Clock (SCK) high time Master Slave tCH Clock (SCK) low time Master Slave tCL Data setup time required for inputs Master Slave tDS Data hold time required for inputs Master Slave tDH Access time (time to data active from highimpedance state) Slave tA Disable time (hold time to high-impedance state) Slave tD Data Valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF 28 Max Unit 50 25 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 12.5 — — ns ns 24.1 25 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.0 ns ns tC Enable lead time Master Slave 1. Min See Figure Figures 21, 22, 23, 24 Figure 24 Figure 24 Figures 21, 22, 23, 24 Figures 21, 22, 23, 24 Figures 21, 22, 23, 24 Figures 21, 22, 23, 24 Figure 24 Figure 24 Figures 21, 22, 23, 24 Figures 21, 22, 23, 24 Figures 21, 22, 23, 24 Figures 21, 22, 23, 24 Parameters listed are guaranteed by design. 56F801 Technical Data Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tF tCH tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tF tR Figure 21. SPI Master Timing (CPHA = 0) SS SS is held High on master (Input) tF tC tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH MISO (Input) MSB in tDI tDV(ref) MOSI (Output) Master MSB out tDS tR tDH Bits 14–1 LSB in tDV Bits 14– 1 tF Master LSB out tR Figure 22. SPI Master Timing (CPHA = 1) 56F801 Technical Data 29 SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDS tR tF tD Bits 14–1 Slave LSB out tDV tDI tDI tDH MOSI (Input) MSB in Bits 14–1 LSB in Figure 23. SPI Slave Timing (CPHA = 0) SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tCH tELG tELD SCLK (CPOL = 1) (Input) tR tDV tCL tR tCH MISO (Output) Slave MSB out Bits 14–1 tDV tDS tDH MOSI (Input) MSB in tD tF tA Bits 14–1 Slave LSB out tDI LSB in Figure 24. SPI Slave Timing (CPHA = 1) 30 56F801 Technical Data Quad Timer Timing 3.8 Quad Timer Timing Table 26. Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit PIN 4T+6 — ns Timer input high/low period PINHL 2T+3 — ns Timer output period POUT 2T — ns POUTHL 1T — ns Timer input period Timer output high/low period 1. 2. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL POUTHL POUTHL Timer Outputs POUT Figure 25. Timer Timing 3.9 Serial Communication Interface (SCI) Timing Table 27. SCI Timing4 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit BR — (fMAX*2.5)/(80) Mbps RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width TXDPW 0.965/BR 1.04/BR ns Baud Rate1 1. 2. 3. 4. fMAX is the frequency of operation of the system clock in MHz. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. Parameters listed are guaranteed by design. 56F801 Technical Data 31 RXD SCI receive data pin (Input) RXDPW Figure 26. RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 27. TXD Pulse Width 3.10 Analog-to-Digital Converter (ADC) Characteristics Table 28. ADC Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14 (for optimal performance), ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit VADCIN 01 — VREF2 V Resolution RES 12 — 12 Bits Integral Non-Linearity3 INL — +/- 4 +/- 5 LSB4 Differential Non-Linearity DNL — +/- 0.9 +/- 1 LSB4 ADC input voltages Monotonicity GUARANTEED ADC internal clock5 fADIC 0.5 — 5 MHz Conversion range RAD VSSA — VDDA V Conversion time tADC — 6 — tAIC cycles6 Sample time tADS — 1 — tAIC cycles6 Input capacitance CADI — 5 — pF6 Gain Error (transfer gain)5 EGAIN 1.00 1.10 1.15 — VOFFSET +10 +230 +325 mV THD 55 60 — dB Signal-to-Noise plus Distortion5 SINAD 54 56 — dB Effective Number of Bits5 ENOB 8.5 9.5 — bit Offset Voltage5 Total Harmonic Distortion5 32 56F801 Technical Data Analog-to-Digital Converter (ADC) Characteristics Table 28. ADC Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14 (for optimal performance), ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit SFDR 60 65 — dB Bandwidth BW — 100 — KHz ADC Quiescent Current (both ADCs) IADC — 50 — mA VREF Quiescent Current (both ADCs) IVREF — 12 16.5 mA Spurious Free Dynamic Range5 1. For optimum ADC performance, keep the minimum VADCIN value > 250mV. Inputs less than 250mV volts may convert to a digital output code of 0 or cause erroneous conversions. 2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VDDA-0.3V. 3. Measured in 10-90% range. 4. 5. 6. LSB = Least Significant Bit. Guaranteed by characterization. tAIC = 1/fADIC ADC analog input 1 3 2 4 Figure 28. Equivalent Analog Input Circuit 1. 2. 3. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf) Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf) Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms) 4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf) 56F801 Technical Data 33 3.11 JTAG Timing Table 29. JTAG Timing 1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 10 MHz TCK cycle time tCY 100 — ns TCK clock pulse width tPW 50 — ns TMS, TDI data setup time tDS 0.4 — ns TMS, TDI data hold time tDH 1.2 — ns TCK low to TDO data valid tDV — 26.6 ns TCK low to TDO tri-state tTS — 23.5 ns tTRST 50 — ns tDE 8T — ns TRST assertion time DE assertion time 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW tPW VIH VM TCK (Input) VM = VIL + (VIH – VIL)/2 VM VIL Figure 29. Test Clock Input Timing Diagram 34 56F801 Technical Data JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 30. Test Access Port Timing Diagram TRST (Input) tTRST Figure 31. TRST Timing Diagram DE tDE Figure 32. OnCE—Debug Event 56F801 Technical Data 35 Part 4 Packaging 4.1 Package and Pin-Out Information 56F801 ANA5 ANA6 ANA7 ORIENTATION MARK TDO ANA4 PIN 37 TD1 TD2 PWMA0 VCAPC1 VDD VSS PWMA1 PWMA2 PWMA3 PWMA4 PWMA5 This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801. ANA3 VREF PIN 1 /SS ANA2 Motorola MISO ANA1 MOSI ANA0 SCLK FAULTA0 56F801 TXDO VSS VDD VSS VDD VSSA PIN 25 RXD0 VDDA PIN 13 DE TRST TDO XTAL EXTAL VDD VSS VCAPC2 TDI IREQA TMS TCK TCS RESET Figure 33. Top View, 56F801 48-pin LQFP Package 36 56F801 Technical Data Package and Pin-Out Information 56F801 Table 30. 56F801 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 TD0 13 TCS 25 RESET 37 ANA5 2 TD1 14 TCK 26 VDDA 38 ANA6 3 TD2 15 TMS 27 VSSA 39 ANA7 4 SS 16 IREQA 28 VDD 40 PWMA0 5 MISO 17 TDI 29 VSS 41 VCAPC1 6 MOSI 18 VCAPC2 30 FAULTA0 42 VDD 7 SCLK 19 VSS 31 ANA0 43 VSS 8 TXD0 20 VDD 32 ANA1 44 PWMA1 9 VSS 21 EXTAL 33 ANA2 45 PWMA2 10 VDD 22 XTAL 34 VREF 46 PWMA3 11 RXD0 23 TDO 35 ANA3 47 PWMA4 12 DE 24 TRST 36 ANA4 48 PWMA5 56F801 Technical Data 37 0.200 AB T-U Z 9 DETAIL Y A P A1 48 37 1 36 T U B V AE B1 12 25 13 AE V1 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. Z S1 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA T, U, Z S DETAIL Y 4X 0.200 AC T-U Z 0.080 AC G AB AD AC M° BASE METAL TOP & BOTTOM R J 0.250 N MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 ° 7° 12 ° REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF C E GAUGE PLANE 4X F D 0.080 M AC T-U Z SECTION AE-AE H CASE 932-03 ISSUE F W L° K DETAIL AD AA Figure 34. 48-pin LQFP Mechanical Information 38 56F801 Technical Data Thermal Design Considerations Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: TJ = T A + ( P D × R θJA ) Where: TA = ambient temperature °C RθJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: RθJA = RθJC + R θCA Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: • Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. • Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. • Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. 56F801 Technical Data 39 The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 5.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation: 40 • Provide a low-impedance path from the board power supply to each VDD pin on the hybrid controller, and from the board ground to each VSS (GND) pin. • The minimum bypass requirement is to place 0.1 µF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. • Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a highgrade capacitor such as a tantalum capacitor. • Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. • Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. 56F801 Technical Data Electrical Design Considerations • Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. • Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. 56F801 Technical Data 41 Part 6 Ordering Information Table 31 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 31. DSP56F801 Ordering Information 42 Part Supply Voltage 56F801 3.0–3.6 V 56F801 3.0–3.6 V Pin Count Frequency (MHz) Order Number Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80 Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60 Package Type 56F801 Technical Data Electrical Design Considerations 56F801 Technical Data 43 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2004 DSP56F801/D