S-8253C/D Series
www.ablic.com
www.ablicinc.com
© ABLIC Inc., 2008-2018
BATTERY PROTECTION IC
FOR 2-SERIES OR 3-SERIES-CELL PACK
Rev.2.5_00
The S-8253C/D Series is a protection ICs for 2-series or 3-series cell lithium-ion rechargeable battery and includes highaccuracy voltage detector and delay circuit.
This IC is suitable for protecting lithium-ion battery packs from overcharge, overdischarge and overcurrent.
Features
(1)
High-accuracy voltage detection for each cell
• Overcharge detection voltage n (n = 1 to 3)
3.900 V to 4.400 V (50 mV step)
Accuracy ±25 mV
*1
Accuracy ±50 mV
• Overcharge release voltage n (n = 1 to 3)
3.800 V to 4.400 V
• Overdischarge detection voltage n (n = 1 to 3)
2.000 V to 3.000 V (100 mV step) Accuracy ±80 mV
*2
Accuracy ±100 mV
• Overdischarge release voltage n (n = 1 to 3)
2.000 V to 3.400 V
(2) Three-level overcurrent detection (Including load short circuiting detection)
• Overcurrent detection voltage 1
0.050 V to 0.300 V (50 mV step)
Accuracy ±25 mV
• Overcurrent detection voltage 2
0.500 V (Fixed)
• Overcurrent detection voltage 3
1.200 V (Fixed)
(3) Delay time (Overcharge, overdischarge, overcurrent) is available by only using an internal circuit. (External
capacitors are unnecessary).
(4) Charge / discharge operation can be inhibited by the control pin.
(5) 0 V battery charge function available / unavailable is selectable.
(6) High-withstand voltage
Absolute maximum rating 26 V
(7) Wide range of operating voltage
2 V to 24 V
(8) Wide range of operating temperature
−40°C to +85°C
(9) Low current consumption
• During operation
28 μA max. (+25°C)
• During power-down 0.1 μA max. (+25°C)
*3
(10) Lead-free, Sn100%, halogen-free
Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage
(Overcharge hysteresis voltage n (n = 1 to 3) can be selected in 0 V, or in 0.1 V to 0.4 V in 50 mV step.)
*2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage n (n = 1 to 3) can be selected in 0 V, or in 0.2 V to 0.7 V in 100 mV step.)
*3. Refer to “Product Name Structure” for details.
*1.
Applications
• Lithium-ion rechargeable battery packs
• Lithium polymer rechargeable battery packs
Package
•
8-Pin TSSOP
1
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Block Diagrams
1.
S-8253C Series
VDD
DOP
Oscillator, counter,
controller
COP
−
+
+
−
+
−
95 kΩ
VMP
900 kΩ
VC1
−
+
+
−
+
−
+
−
VC2
CTLH
200 nA
CTLM
CTL
Remark
+
−
VSS
All diodes shown in figure are parasitic diodes.
Figure 1
2
−
+
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
2.
S-8253D Series
VDD
DOP
Oscillator, counter,
controller
COP
−
+
+
−
+
−
95 kΩ
VMP
900 kΩ
VC1
−
+
+
−
+
−
+
−
VC2
CTLH
200 nA
CTLM
CTL
Remark
−
+
+
−
VSS
All diodes shown in figure are parasitic diodes.
Figure 2
3
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Product Name Structure
1.
Product Name
1. 1
Environmental code = U, S
S-8253
x
xx
-
T8T1
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
S:
Lead-free, halogen-free
Package abbreviation and IC packing specifications*1
T8T1: 8-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
Product series name
C:
2-cell
D:
3-cell
*1. Refer to the tape drawing.
*2. Refer to “3. Product Name List”.
1. 2
Environmental code = G
S-8253
x
xx
-
T8T1
G
Z
Fixed
Environmental code
G:
Lead-free (for details, please contact our sales office)
Package abbreviation and IC packing specifications*1
T8T1: 8-Pin TSSOP, Tape
*2
Serial code
Sequentially set from AA to ZZ
Product series name
C:
2-cell
D:
3-cell
*1.
*2.
2.
Refer to the tape drawing.
Refer to “3. Product Name List”.
Package
Environmental code = G, S
Package
FT008-A-P-SD
Drawing Code
Tape
FT008-E-C-SD
Reel
FT008-E-R-SD
Environmental code = U
FT008-A-P-SD
FT008-E-C-SD
FT008-E-R-S1
Package Name
8-Pin TSSOP
4
Rev.2.5_00
3.
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Product Name List
Table 1
S-8253C Series (For 2-Serial Cell)
Overcharge
detection voltage
[VCU]
Overcharge
release voltage
[VCL]
Overdischarge
detection voltage
[VDL]
Overdischarge
release voltage
[VDU]
Overcurrent
detection voltage 1
[VIOV1]
S-8253CAA-T8T1
4.350 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.300 ± 0.025 V
Available
S-8253CAC-T8T1y
4.350 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.080 ± 0.025 V
Available
S-8253CAD-T8T1
4.250 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.120 ± 0.025 V
Available
S-8253CAH-T8T1
4.350 ± 0.025 V
4.150 ± 0.050 V
2.300 ± 0.080 V
2.300 ± 0.080 V
0.090 ± 0.025 V
Available
S-8253CAI-T8T1
4.250 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.200 ± 0.025 V
Available
S-8253CAJ-T8T1
4.250 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.120 ± 0.025 V
Available
S-8253CAK-T8T1
4.250 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.300 ± 0.025 V
Available
S-8253CAL-T8T1y
4.400 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.120 ± 0.025 V
Available
S-8253CAM-T8T1y
4.225 ± 0.025 V
4.025 ± 0.050 V
2.600 ± 0.080 V
2.900 ± 0.100 V
0.200 ± 0.025 V
Available
S-8253CAN-T8T1U
4.400 ± 0.025 V
4.100 ± 0.050 V
2.800 ± 0.080 V
3.000 ± 0.100 V
0.300 ± 0.025 V
Available
S-8253CAO-T8T1U
4.400 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.150 ± 0.025 V
Available
S-8253CAP-T8T1U
4.350 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.300 ± 0.025 V
Unavailable
S-8253CAQ-T8T1U
3.800 ± 0.025 V
3.700 ± 0.050 V
2.200 ± 0.080 V
2.400 ± 0.100 V
0.100 ± 0.025 V
Unavailable
S-8253CAR-T8T1U
4.450 ± 0.025 V
4.200 ± 0.050 V
2.800 ± 0.080 V
3.000 ± 0.100 V
0.120 ± 0.025 V
Available
Model No.
0 V battery
charge function
Remark 1. : GZ or U
y: S or U
2. Please select products of environmental code = U for Sn 100%, halogen-free products.
Table 2
S-8253D Series (For 3-Series Cell)
Model No.
Overcharge
detection voltage
[VCU]
Overcharge
release voltage
[VCL]
Overdischarge
detection voltage
[VDL]
Overdischarge
release voltage
[VDU]
Overcurrent
detection voltage 1
[VIOV1]
S-8253DAA-T8T1
4.350 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.300 ± 0.025 V
Available
S-8253DAB-T8T1
4.300 ± 0.025 V
4.050 ± 0.050 V
2.700 ± 0.080 V
3.000 ± 0.100 V
0.200 ± 0.025 V
Unavailable
S-8253DAD-T8T1y
4.250 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.120 ± 0.025 V
Available
S-8253DAI-T8T1
4.350 ± 0.025 V
4.150 ± 0.050 V
2.200 ± 0.080 V
2.400 ± 0.100 V
0.160 ± 0.025 V
Available
S-8253DAK-T8T1y
4.350 ± 0.025 V
4.050 ± 0.050 V
2.400 ± 0.080 V
2.700 ± 0.100 V
0.300 ± 0.025 V
Available
S-8253DAL-T8T1U
4.250 ± 0.025 V
4.050 ± 0.050 V
2.600 ± 0.080 V
2.900 ± 0.100 V
0.120 ± 0.025 V
Available
S-8253DAM-T8T1U
3.800 ± 0.025 V
3.700 ± 0.050 V
2.200 ± 0.080 V
2.400 ± 0.100 V
0.100 ± 0.025 V
Unavailable
S-8253DAN-T8T1U
4.250 ± 0.025 V
4.050 ± 0.050 V
2.600 ± 0.080 V
2.900 ± 0.100 V
0.150 ± 0.025 V
Available
0 V battery
charge function
Remark 1. : GZ or U
y: S or U
2. Please select products of environmental code = U for Sn 100%, halogen-free products.
5
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Pin Configuration
Table 3
8-Pin TSSOP
Top view
DOP
COP
VMP
CTL
1
2
3
4
8
7
6
5
Figure 3
VDD
VC1
VC2
VSS
Pin No.
Symbol
1
DOP
2
COP
3
VMP
4
CTL
5
VSS
6
VC2
7
VC1
8
VDD
6
Pin No.
Symbol
1
DOP
2
COP
3
VMP
4
CTL
5
VSS
6
VC2
7
VC1
8
VDD
S-8253C Series
Description
Connection pin for discharge control FET gate
(CMOS output)
Connection pin for charge control FET gate
(Nch open-drain output)
Pin for voltage detection between VDD and VMP
(Detection pin for overcurrent)
Input pin for charge / discharge control signal,
Pin for shortening test time
( L : Normal operation,
H : inhibit charge / discharge
M (VDD × 1 / 2) : shorten test time)
Input pin for negative power supply,
Connection pin for negative voltage of battery 2
No connection *1
Connection pin for negative voltage of battery 1,
for positive voltage of battery 2
Input pin for positive power supply,
Connection pin for positive voltage of battery 1
Table 4
*1.
Rev.2.5_00
S-8253D Series
Description
Connection pin for discharge control FET gate
(CMOS output)
Connection pin for charge control FET gate
(Nch open-drain output)
Pin for voltage detection between VDD and VMP
(Detection pin for overcurrent)
Input pin for charge / discharge control signal,
pin for shortening test time
( L : Normal operation,
H : inhibit charge / discharge,
M (VDD × 1 / 2) : shorten test time)
Input pin for negative power supply,
Connection pin for negative voltage of battery 3
Connection pin for negative voltage of battery 2,
for positive voltage of battery 3
Connection pin for negative voltage of battery 1,
for positive voltage of battery 2
Input pin for positive power supply,
Connection pin for positive voltage of battery 1
No connection is electrically open. This pin can be connected to VDD or VSS.
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Absolute Maximum Ratings
Table 5
(Ta = 25°C unless otherwise specified)
Item
Symbol
Applicable Pin
Absolute Maximum Rating
Unit
Input voltage between VDD and VSS
VDS
⎯
Input pin voltage
VIN
VC1, VC2
VMP pin input voltage
VVMP
VMP
VSS − 0.3 to VSS + 26
V
DOP pin output voltage
VDOP
DOP
VSS − 0.3 to VDD + 0.3
V
COP pin output voltage
VCOP
COP
VSS − 0.3 to VVMP + 0.3
V
CTL pin input voltage
VIN_CTL
CTL
VSS − 0.3 to VDD + 0.3
V
Power dissipation
PD
⎯
Operating ambient temperature
Topr
Storage temperature
Tstg
VSS − 0.3 to VSS + 26
V
VSS − 0.3 to VDD + 0.3
V
300 (When not mounted on board)
mW
700*1
mW
⎯
− 40 to + 85
°C
⎯
− 40 to + 125
°C
*1. When mounted on board
[Mounted board]
(1) Board size :
114.3 mm × 76.2 mm × t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
800
Power Dissipation (PD) [mW]
700
600
500
400
300
200
100
0
0
50
100
150
Ambient Temperature (Ta) [°C]
Figure 4
Power Dissipation of Package (When Mounted on Board)
7
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Electrical Characteristics
1.
Characteristics Other Than Detection Delay Time
Table 6 (1 / 2)
Item
Symbol
Condition
Min.
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
condicircuit
tion
DETECTION VOLTAGE
Overcharge detection voltage n
VCUn
3.900 V to 4.400 V, Adjustable
Overcharge release voltage n
VCLn
3.800 V to 4.400 V,
Adjustable
VCL ≠ VCU
VCL = VCU
Overdischarge detection voltage n
VDLn
2.000 V to 3.000 V, Adjustable
Overdischarge release voltage n
VDUn
2.000 V to 3.400 V,
Adjustable
VDL ≠ VDU
VDL = VDU
Overcurrent detection voltage 1
VIOV1
Overcurrent detection voltage 2
Overcurrent detection voltage 3
Temperature coefficient 1 *1
Temperature coefficient 2 *2
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage
0 V battery charge inhibition battery voltage
INTERNAL RESISTANCE
Resistance between VMP and VDD
Resistance between VMP and VSS
VIOV2
VIOV3
TCOE1
TCOE2
0.050 V to 0.300 V, Adjustable
Based on VDD
Based on VDD
Based on VDD
*3
Ta = 0°C to 50°C
*3
Ta = 0°C to 50°C
V0CHA
V0INH
0 V battery charging; available
0 V battery charging; unavailable
RVMD
RVMS
V1 = V2 = V3 = 3.5 V, VVMP = VSS
*4
V1 = V2 = V3 = 1.8 V, VVMP = VDD
8
*4
VCUn
−0.025
VCLn
−0.050
VCLn
−0.025
VDLn
−0.080
VDUn
−0.100
VDUn
−0.080
VIOV1
−0.025
0.400
0.900
−1.0
−0.5
0.500
1.200
0
0
⎯
0.4
0.8
0.7
1.5
1.1
70
450
95
900
120
1800
VCUn
VCLn
VCLn
VDLn
VDUn
VDUn
VIOV1
VCUn
V
+0.025
VCLn
V
+0.050
VCLn
V
+0.025
VDLn
V
+0.080
VDUn
V
+0.100
VDUn
V
+0.080
VIOV1
V
+0.025
0.600
V
1.500
V
1.0
mV / °C
0.5
mV / °C
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
⎯
⎯
1
1
⎯
⎯
V
V
12
12
5
5
kΩ
kΩ
6
6
2
2
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Table 6 (2 / 2)
Item
INPUT VOLTAGE
Operating voltage
between VDD and VSS
Symbol
VDSOP
Condition
Output voltage of DOP and COP fixed
Min.
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
condicircuit
tion
2
⎯
24
V
⎯
⎯
CTL input voltage “H”
VCTLH
⎯
VDD
−0.5
⎯
⎯
V
7
1
CTL input voltage “L”
VCTLL
⎯
⎯
⎯
VSS
+0.5
V
7
1
INPUT CURRENT
*4
IOPE
V1 = V2 = V3 = 3.5 V
⎯
μA
Current consumption during operation
14
28
5
2
*4
V1 = V2 = V3 = 1.5 V
⎯
⎯
0.1
Current consumption during power-down IPDN
μA
5
2
*4
IVC1
V1 = V2 = V3 = 3.5 V
−0.3
0
0.3
VC1 pin current
μA
9
3
*4
IVC2
V1 = V2 = V3 = 3.5 V
−0.3
0
0.3
VC2 pin current
μA
9
3
*4
I
V1
=
V2
=
V3
=
3.5
V,
V
=
V
⎯
⎯
0.1
CTL pin current “H”
μA
8
3
CTLH
CTL1
DD
*4
ICTLL
V1 = V2 = V3 = 3.5 V, VCTL1 = VSS
−0.4
–0.2
⎯
CTL pin current “L”
μA
8
3
OUTPUT CURRENT
ICOH
VCOP = 24 V
⎯
⎯
0.1
μA
COP pin leakage current
10
4
ICOL
VCOP = VSS + 0.5 V
10
⎯
⎯
COP pin sink current
μA
10
4
I
V
=
V
−
0.5
V
10
⎯
⎯
DOP pin source current
μA
11
4
DOH
DOP
DD
IDOL
VDOP = VSS + 0.5 V
10
⎯
⎯
DOP pin sink current
μA
11
4
*1. Voltage temperature coefficient 1 : Overcharge detection voltage
*2. Voltage temperature coefficient 2 : Overcurrent detection voltage 1
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
*4. The S-8253C Series does not have V3 because this IC is for 2-series cell battery protection.
9
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
2.
(1)
Rev.2.5_00
Detection Delay Time
S-8253CAA, S-8253CAC, S-8253CAD, S-8253CAI, S-8253CAJ, S-8253CAK, S-8253CAL, S-8253CAM,
S-8253CAN, S-8253CAO, S-8253CAP, S-8253CAQ, S-8253CAR, S-8253DAA, S-8253DAB, S-8253DAD,
S-8253DAK, S-8253DAL, S-8253DAM, S-8253DAN
Table 7
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
⎯
0.92
1.15
1.38
s
3
1
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
tDL
tIOV1
tIOV2
tIOV3
⎯
⎯
⎯
⎯
115
7.2
3.6
220
144
9
4.5
300
173
10.8
5.4
380
ms
ms
ms
μs
3
4
4
4
1
1
1
1
Condition
Min.
Typ.
Max.
Unit
Test
Condition
Test
Circuit
(2)
S-8253DAI
Table 8
Item
Symbol
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
⎯
0.92
1.15
1.38
s
3
1
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
tDL
tIOV1
tIOV2
tIOV3
⎯
⎯
⎯
⎯
115
3.6
0.89
220
144
4.5
1.1
300
173
5.4
1.4
380
ms
ms
ms
μs
3
4
4
4
1
1
1
1
Condition
Min.
Typ.
Max.
Unit
Test
Condition
Test
Circuit
(3)
S-8253CAH
Table 9
Item
Symbol
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
⎯
0.92
1.15
1.38
s
3
1
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
tDL
tIOV1
tIOV2
tIOV3
⎯
⎯
⎯
⎯
115
14.5
3.6
220
144
18
4.5
300
173
22
5.4
380
ms
ms
ms
μs
3
4
4
4
1
1
1
1
10
Rev.2.5_00
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Test Circuits
1.
Overcharge Detection Voltage 1, Overcharge Release Voltage 1, Overdischarge Detection Voltage 1,
Overdischarge Release Voltage 1
(Test Condition 1, Test Circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0 V, and the
COP and DOP pins are “L” (VDD × 0.1 V or lower) (this status is referred to as the initial status).
1. 1
Overcharge Detection Voltage 1 (VCU1), Overcharge Release Voltage 1 (VCL1)
Overcharge detection voltage 1 (VCU1) is the voltage of V1 when the voltage of the COP pin is “H” (VDD × 0.9 V or
more) after the V1 voltage has been gradually increased starting at the initial status. Overcharge release voltage
1 (VCL1) is the voltage of V1 when the voltage at the COP pin is low after the V1 voltage has been gradually
decreased.
1. 2
Overdischarge Detection Voltage 1 (VDL1), Overdischarge Release Voltage 1 (VDU1)
Overdischarge detection voltage 1 (VDL1) is the voltage of V1 when the voltage of the DOP pin is high after the V1
voltage has been gradually decreased starting at the initial status. Overdischarge release voltage 1 (VDU1) is the
voltage of V1 when the voltage at the DOP pin is low after the V1 voltage has been gradually increased.
By changing Vn (n = 2: S-8253C Series, n = 2, 3: S-8253D Series) the overcharge detection voltage (VCUn),
overcharge release voltage (VCLn), overdischarge detection voltage (VDLn), and overdischarge release voltage (VDUn)
can be measured in the same way as when n = 1.
2.
Overcurrent Detection Voltage 1, Overcurrent Detection Voltage 2, Overcurrent Detection Voltage 3
(Test Condition 2, Test Circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
2. 1
Overcurrent Detection Voltage 1 (VIOV1)
Overcurrent detection voltage 1 (VIOV1) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high after the V5 voltage has been gradually increased starting at the initial status.
2. 2
Overcurrent Detection Voltage 2 (VIOV2)
Overcurrent detection voltage 2 (VIOV2) is a voltage at V5 when; by increasing a voltage at V5 instantaneously
(within 10 μs) from the initial state, the voltages of the COP and DOP pin are set to “H”, and its delay time is in the
range of minimum to maximum value of overcurrent detection delay time 2 (tIOV2).
2. 3
Overcurrent Detection Voltage 3 (VIOV3)
Overcurrent detection voltage 3 (VIOV3) is a voltage at V5 when; by increasing a voltage at V5 instantaneously
(within 10 μs) from the initial state, the voltages of the COP and DOP pin are set to “H”, and its delay time is in the
range of minimum to maximum value of overcurrent detection delay time 3 (tIOV3).
11
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
3.
Rev.2.5_00
Overcharge Detection Delay Time, Overdischarge Detection Delay Time
(Test Condition 3, Test Circuit 1)
Confirm that V1 = V2 = 3.5 V (in S-8253C Series), V1 = V2 = V3 = 3.5 V (in S-8253D Series), V4 = 0 V, V5 = 0 V, and
the COP pin and DOP pin are low (this status is referred to as the initial status).
3. 1
Overcharge Detection Delay Time (tCU)
The overcharge detection delay time (tCU) is the time it takes for the voltage of the COP pin to change from low to
high after the voltage of V1 is instantaneously changed from overcharge detection voltage 1 (VCU1) − 0.2 V to
overcharge detection voltage 1 (VCU1) + 0.2 V (within 10 μs) starting at the initial status.
3. 2
Overdischarge Detection Delay Time (tDL)
The overdischarge detection delay time (tDL) is the time it takes for the voltage of the DOP pin to change from low
to high after the voltage of V1 is instantaneously changed from overdischarge detection voltage 1 (VDL1) + 0.2 V to
overdischarge detection voltage 1 (VDL1) − 0.2 V (within 10 μs) starting at the initial status.
4.
Overcurrent Detection Delay Time 1, Overcurrent Detection Delay Time 2, Overcurrent Detection
Delay Time 3
(Test Condition 4, Test Circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
4. 1
Overcurrent Detection Delay Time 1 (tIOV1)
Overcurrent detection delay time 1 (tIOV1) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 0.35 V (within 10 μs) starting at the initial status.
4. 2
Overcurrent Detection Delay Time 2 (tIOV2)
Overcurrent detection delay time 2 (tIOV2) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 0.7 V (within 10 μs) starting at the initial status.
4. 3
Overcurrent Detection Delay Time 3 (tIOV3)
Overcurrent detection delay time 3 (tIOV3) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 1.6 V (within 10 μs) starting at the initial status.
5.
Current Consumption during Operation, Current Consumption during Power-down
(Test Condition 5, Test Circuit 2)
5. 1
Current Consumption during Operation (IOPE)
The current consumption during operation (IOPE) is the current of the VSS pin (ISS) when V1 = V2 = 3.5 V
(S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), S1 = ON, and S2 = OFF.
5. 2
Current Consumption during Power-down (IPDN)
The current consumption during power-down (IPDN) is the current of the VSS pin (ISS) when V1 = V2 = 1.5 V
(S-8253C Series), V1 = V2 = V3 = 1.5 V (S-8253D Series), S1 = OFF, and S2 = ON.
12
Rev.2.5_00
6.
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Resistance between VMP and VDD, Resistance between VMP and VSS
(Test Condition 6, Test Circuit 2)
Confirm that V1 = V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), S1 = ON, and S2 = OFF (this
status is referred to as the initial status).
6. 1
Resistance between VMP and VDD (RVMD)
The resistance between VMP and VDD (RVMD) is determined based on the current of the VMP pin (IVMD) after S1
and S2 are switched to OFF and ON, respectively, starting at the initial status.
S-8253C Series : RVMD = (V1 + V2) / IVMD
S-8253D Series : RVMD = (V1 + V2 + V3) / IVMD
6. 2
Resistance between VMP and VSS (RVMS)
The resistance between VMP and VSS (RVMS) is determined based on the current of the VMP pin (IVMS) after V1 =
V2 = 1.8 V (S-8253C Series) or V1 = V2 = V3 = 1.8 V (S-8253D Series) are set starting at the initial status.
S-8253C Series : RVMS = (V1 + V2) / IVMS
S-8253D Series : RVMS = (V1 + V2 + V3) / IVMS
7.
CTL Pin Input Voltage “H”
(Test Condition 7, Test Circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
7. 1
CTL Pin Input Voltage “H” (VCTLH)
The CTL pin input voltage “H” (VCTLH) is the voltage of V4 when the voltages of the COP pin and DOP pin are high
after the voltage of V4 has been gradually increased starting at the initial status.
8.
CTL Pin Input Voltage “L”
(Test condition 7, Test circuit 1)
Confirm that V1 = V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0.35 V, and
the COP pin and DOP pin are high (this status is referred to as the initial status).
8. 1
CTL Pin Input Voltage “L” (VCTLL)
The CTL pin input voltage “L” (VCTLL) is the voltage of V4 when the voltages of the COP pin and DOP pin are low
after the voltage of V4 has been gradually increased starting at the initial status.
9.
CTL Pin Current “H”, CTL Pin Current “L”
(Test Condition 8, Test Circuit 3)
9. 1
CTL Pin Current “H” (ICTLH), CTL Pin Current “L” (ICTLL)
The CTL pin current “H” (ICTLH) is the current that flows through the CTL pin when V1 = V2 = 3.5 V (S-8253C
Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), and S3 = ON, S4 = OFF. The CTL pin current “L” (ICTLL) is the
current that flows through the CTL pin when S3 = OFF and S4 = ON after that.
13
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
10.
Rev.2.5_00
VC1 Pin Current, VC2 Pin Current
(Test Condition 9, Test Circuit 3)
10. 1
VC1 Pin Current (IVC1), VC2 Pin Current (IVC2)
The VC1 pin current (IVC1) is the current that flows through the VC1 pin when V1 = V2 = 3.5 V (S-8253C Series),
V1 = V2 = V3 = 3.5 V (S-8253D Series), and S3 = OFF, S4 = ON. Similarly, the VC2 pin current (IVC2) is the
current that flows through the VC2 pin under these conditions (S-8253D Series only).
11.
COP Pin Leakage Current, COP Pin Sink Current
(Test Condition 10, Test Circuit 4)
11. 1
COP Pin Leakage Current (ICOH)
The COP pin leakage current (ICOH) is the current that flows through the COP pin when V1 = V2 = 12 V (S-8253C
Series), V1 = V2 = V3 = 8 V (S-8253D Series), S6 = S7 = S8 = OFF, and S5 = ON.
11. 2
COP Pin Sink Current (ICOL)
The COP pin sink current (ICOL) is the current that flows through the COP pin when V1 = V2 = 3.5 V (S-8253C
Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V6 = 0.5 V, S5 = S7 = S8 = OFF, and S6 = ON.
12.
DOP Pin Source Current, DOP Pin Sink Current
(Test Condition 11, Test Circuit 4)
12. 1
DOP Pin Source Current (IDOH)
The DOP pin source current (IDOH) is the current that flows through the DOP pin when V1 = V2 = 1.8 V (S-8253C
Series), V1 = V2 = V3 = 1.8 V (S-8253D Series), V7 = 0.5 V, S5 = S6 = S8 = OFF, and S7 = ON.
12. 2
DOP Pin Sink Current (IDOL)
The DOP pin sink current (IDOL) is the current that flows through the DOP pin when V1 = V2 = 3.5 V (S-8253C
Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V8 = 0.5 V, S5 = S6 = S7 = OFF, and S8 = ON.
13.
0 V Battery Charge Starting Charger Voltage (Product with 0 V Battery Charge Function),
0 V Battery Charge Inhibition Battery Voltage (Product with 0 V Battery Charge Inhibition Function)
(Test Condition 12, Test Circuit 5)
13. 1
0 V Battery Charge Starting Charger Voltage (V0CHA) (Product with 0 V Battery Charge Function)
The COP pin voltage should be lower than V0CHA max. − 1 V when V1 = V2 = 0 V (S-8253C Series), V1 = V2 = V3
= 0 V (S-8253D Series), and V9 = VVMP = V0CHA max.
13. 2
0 V Battery Charge Inhibition Battery Voltage (V0INH) (Product with 0 V Battery Charge Inhibition Function)
The COP pin voltage should be higher than VVMP − 1 V when V1 = V2 = V0INH min. (S-8253C Series), V1 = V2 = V3
= V0INH min. (S-8253D Series), and V9 = VVMP = 24 V.
14
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
S-8253C
V
S-8253D
V
V
1 DOP
V
VDD 8
1 DOP
V1
1 MΩ
2 COP
VC1 7
V1
2 COP
V5
V2
3 VMP
VDD 8
1 MΩ
VC1 7
V5
V2
VC2 6
3 VMP
VC2 6
4 CTL
VSS 5
1 μF
4 CTL
1 μF
VSS 5
V4
V3
V4
Figure 5
Test Circuit 1
S-8253D
S-8253C
1 DOP
1 DOP
VDD 8
V1
S1
2 COP
VDD 8
V1
S1
VC1 7
2 COP
VC1 7
3 VMP
VC2 6
4 CTL
VSS 5
V2
V2
A
3 VMP
VC2 6
4 CTL
VSS 5
A
1 μF
S2
1 μF
A
S2
Figure 6
Test Circuit 2
S-8253D
S-8253C
1 DOP
1 DOP
VDD 8
V1
S3
2 COP
VC1 7
VDD 8
V1
S3
A
2 COP
VC1 7
A
3 VMP
VC2 6
A
4 CTL
VSS 5
V2
V2
3 VMP
VC2 6
4 CTL
VSS 5
1 μF
A
V3
A
1 μF
A
V3
S4
S4
Figure 7
Test Circuit 3
15
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
S5
S7
S5
S-8253C
S7
V7
A
S-8253D
V7
1 DOP
VDD 8
A
V8
A
Rev.2.5_00
V1
2 COP
1 DOP
VDD 8
V8
VC1 7
A
V1
2 COP
VC1 7
3 VMP
VC2 6
V2
V2
V6
3 VMP
V6
VC2 6
1 μF
S6
S8
4 CTL
1 μF
VSS 5
S8
S6
Figure 8
4 CTL
VSS 5
Test Circuit 4
S-8253C
1 DOP
S-8253D
VDD 8
1 DOP
VDD 8
V1
2 COP
V
2 COP
V2
V9
VC1 7
1 MΩ
V2
3 VMP
VC2 6
1 μF
V9
VSS 5
4 CTL
Figure 9
16
V
VC2 6
1 μF
4 CTL
V1
VC1 7
1 MΩ
3 VMP
V3
Test Circuit 5
VSS 5
V3
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Operation
Remark Refer to “
1.
Battery Protection IC Connection Example”.
Normal Status
When the voltage of each of the batteries is in the range from VDLn to VCUn and the discharge current is lower than the
specified value (the VMP pin voltage is higher than VDD − VIOV1), the charging and discharging FETs are turned on.
This condition is called the normal status, and in this condition charging and discharging can be carried out freely.
Caution
2.
When the battery is connected for the first time, discharging may not be enabled.
short the VMP pin and VDD pin or connect the charger to restore the normal status.
In this case,
Overcharge Status
When the voltage of one of the batteries becomes higher than VCUn and the state continues for tCU or longer, the COP
pin becomes high impedance. Because the COP pin is pulled up to the EB+ pin voltage by an external resistor, the
charging FET is turned off to stop charging. This is called the overcharge status. The overcharge status is released
when one of the following two conditions holds.
(1) The voltage of each of the batteries becomes VCLn or lower.
(2) The voltage of each of the batteries is VCUn or lower, and the VMP pin voltage is VDD − VIOV1 or lower (since
the discharge current flows through the body diode of the charging FET immediately after discharging is
started when the charger is removed and a load is connected, the VMP pin voltage momentarily decreases
by approximately 0.6 V from the VDD pin voltage. The IC detects this voltage and releases the overcharging
status).
3.
Overdischarge Status
When the voltage of one of the batteries becomes lower than VDLn and the state continues for tDL or longer, the DOP
pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is called the
overdischarge status.
3. 1
Power-down Function
When the overdischarge status is reached, the VMP pin is pulled down to the VSS level by the internal RVMS
resistor of the IC. When the VMP pin voltage is 0.8 V typ. or lower, the power-down function starts to operate
and almost every circuit in the S-8253C/D Series stops working. The conditions of each output pin are as
follows.
(1) COP pin : High-Z
(2) DOP pin : VDD
The power-down function is released when the following condition holds.
(1) The VMP pin voltage is 0.8 V typ. or higher.
The overdischarge status is released when the following two conditions hold.
(1) In case the VMP pin voltage is 0.8 V typ. or higher and the VMP pin voltage is lower than VDD, the
overdischarge status is released when the voltage of each of the batteries is VDUn or higher.
(2) In case the VMP pin voltage is 0.8 V typ. or higher and the VMP pin voltage is VDD or higher, the
overdischarge status is released when the voltage of each of the batteries is VDLn or higher (when a
charger is connected and the VMP pin voltage is VDD or higher, overdischarge hysteresis is released and
discharge control FET is turned on at VDLn).
17
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
4.
Rev.2.5_00
Overcurrent Status
The S-8253C/D Series has three overcurrent detection levels (VIOV1, VIOV2, and VIOV3) and three overcurrent detection
delay times (tIOV1, tIOV2, and tIOV3) corresponding to each overcurrent detection level. When the discharging current
becomes higher than the specified value (the difference of the voltages of the VMP pin and VDD pin is greater than
VIOV1) and the state continues for tIOV1 or longer, the S-8253C/D Series enters the overcurrent status, in which the
DOP pin voltage becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high
impedance and is pulled up to the EB+ pin voltage to turn off the charging FET to stop charging, and the VMP pin is
pulled up to the VDD voltage by the internal resistor (RVMD). Operation of overcurrent detection levels 2, 3 (VIOV2,
VIOV3) and overcurrent detection delay times 2, 3 (tIOV2, tIOV3) are the same as for VIOV1 and tIOV1. The overcurrent
status is released when the following condition holds.
(1) The VMP pin voltage is VDD − VIOV1 or higher because a charger is connected or the load is released.
Caution
5.
The impedance that enables automatic restoration varies depending on the battery voltage and set
value of overcurrent detection voltage 1.
0 V Battery Charge Function
Regarding the charging of a self-discharged battery (0 V battery), the S-8253C/D Series has two functions from which
one should be selected.
(1) 0 V battery charging is allowed (0 V battery charging is available.)
When the charger voltage is higher than V0CHA, the 0 V battery can be charged.
(2) 0 V battery charging is inhibited (0 V battery charging is unavailable.)
When the battery voltage is V0INH or lower, the 0 V battery cannot be charged.
Caution
18
When the VDD pin voltage is lower than the minimum value of VDSOP, the operation of the
S-8253C/D Series is not guaranteed.
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
6.
Delay Circuit
The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter.
(Example)
Oscillator clock cycle (TCLK) :
Overcharge detection delay time (tCU) :
Overdischarge detection delay time (tDL) :
Overcurrent detection delay time 1 (tIOV1) :
Overcurrent detection delay time 2 (tIOV2) :
280 μs
1.15 s
144 ms
9 ms
4.5 ms
The overcurrent detection delay time 2 (tIOV2) and overcurrent detection delay time 3 (tIOV3) start when the
overcurrent detection voltage 1 (VIOV1) is detected. As soon as the overcurrent detection voltage 2 (VIOV2)
or overcurrent detection voltage 3 (VIOV3) is detected over the detection delay time for overcurrent 2 (tIOV2)
or overcurrent 3 (tIOV3) after the detection of overcurrent 1 (VIOV1), the S-8253C/D Series turns the
discharging control FET off within tIOV2 or tIOV3 of each detection.
Remark
VDD
DOP pin voltage
tD
0 ≤ tD ≤ tIOV2
VSS
Overcurrent detection
delay time 2 (tIOV2)
Time
VDD
VMP pin voltage
VIOV1
VIOV2
VIOV3
VSS
Time
Figure 10
7.
CTL Pin
The S-8253C/D Series has a control pin for charge / discharge control and shortening test time. The levels, “L”, “H”,
and “M”, of the voltage input to the CTL pin determine the status of the S-8253C/D Series: normal operation, charge /
discharge inhibition, or test time reduction. The CTL pin takes precedence over the battery protection circuit.
During normal use, short the CTL pin and VSS pin.
Table 10
CTL Pin Potential
Conditions Set by CTL Pin
Status of IC
COP Pin
DOP Pin
Open
Charge / discharge inhibited status
High-Z
VDD
High (VCTL ≥ VCTLH)
Charge / discharge inhibited status
High-Z
VDD
Status to shorten delay time *1
(*2)
(*2)
Middle (VCTLL < VCTL < VCTLH)
*2
( )
(*2)
Low (VCTLL ≥ VCTL)
Normal status
*1. In this status that delay time is shortened, only the overcharge detection delay time is shortened in 1/60 to 1/30.
*2. The pin status is controlled by the voltage detection circuit.
Caution
1.
2.
3.
If the potential of the CTL pin is middle, overcurrent detection voltage 1 (VIOV1) does not
operate.
If you use the middle potential of the CTL pin, contact ABLIC Inc. marketing department.
Please note unexpected behavior might occur when electrical potential difference between the
CTL pin (“L” level) and VSS is generated through the external filter (RVSS and CVSS) as a result of
input voltage fluctuations.
19
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Timing Charts
1.
Overcharge Detection and Overdischarge Detection
Battery
voltage
VHC
VCUn
VCLn
VDUn
VDLn
VHD
(n = 1 to 3)
VDD
DOP
pin voltage
VSS
VEB+
COP
pin voltage
High-Z
High-Z
VSS
VEB+
VDD
VIOV1
VMP
pin voltage
Charger
connection
Load
connection
Status*1
0.8 V
VSS
Overcharge detection
delay time ( tCU )
Overdischarge detection
delay time ( tDL )
*1. < 1 > : Normal status
< 2 > : Overcharge status
< 3 > : Overdischarge status
< 4 > : Power-down status
Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the
charger.
Figure 11
20
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
2.
Overcurrent Detection
VHC
VCUn
VCLn
Battery
voltage
VDUn
VDLn
VHD
(n = 1 to 3)
VDD
DOP
pin voltage
VSS
VEB+
COP
pin voltage
High-Z
High-Z
High-Z
VSS
VDD
VIOV1
VIOV2
VMP
pin voltage VIOV3
VSS
Load
connection
Status*1
*1.
Overcurrent detection
delay time 2 ( tIOV2 )
Overcurrent detection
delay time 1 ( tIOV1 )
Overcurrent detection
delay time 3 ( tIOV3)
< 1 > : Normal status
< 2 > : Overcurrent status
Remark
The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the
charger.
Figure 12
21
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Battery Protection IC Connection Examples
1.
S-8253C Series
Charging Discharging
FET
FET
EB+
RCOP
RDOP
S-8253C
RVMP
CTL
1 DOP
VDD 8
2 COP
VC1 7
3 VMP
VC2 6
4 CTL
VSS 5
CVC1
RVC1
CVSS
RVSS
RCTL
EB−
Figure 13
2.
S-8253D Series
Charging Discharging
FET
FET
EB+
RCOP
RDOP
S-8253D
RVMP
CTL
1 DOP
VDD 8
2 COP
VC1 7
3 VMP
VC2 6
4 CTL
VSS 5
RCTL
EB−
Figure 14
22
CVC1
RVC1
CVC2
CVSS
RVC2
RVSS
Rev.2.5_00
Rev.2.5_00
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Table 11
No.
1
2
3
4
5
6
7
8
9
10
Symbol
RVC1
RVC2
RDOP
RCOP
RVMP
RCTL
RVSS
CVC1
CVC2
CVSS
Constants for External Components
Typ.
1
1
5.1
1
5.1
1
51
0.1
0.1
2.2
Range
0.51 to 1*1
0.51 to 1*1
2 to 10
0.1 to 1
1 to 10
1 to 100
5.1 to 51*1
0.1 to 0.47*1
0.1 to 0.47*1
1 to 10*1
Unit
kΩ
kΩ
kΩ
MΩ
kΩ
kΩ
Ω
μF
μF
μF
*1. Please set up a filter constant to be RVSS × CVSS ≥ 51 μF • Ω and to be
RVC1 × CVC1 = RVC2 × CVC2 = RVSS × CVSS.
Caution 1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do
not guarantee proper operation. Perform thorough evaluation using the actual application to set the
constant.
23
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Precautions
24
Rev.2.5_00
•
The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
•
Batteries can be connected in any order, however, there may be cases when discharging cannot be performed when a
battery is connected. In this case, short the VMP pin and VDD pin or connect the battery charger to return to the
normal mode.
•
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
•
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
Characteristics (Typical Data)
Current Consumption
IOPE vs. VDD
1. 4
0
5
10
15
VDD [V]
20
(S-8253CAA)
IOPE [μA]
40
35
30
25
20
15
10
5
0
−40 −25
0
25
Ta [°C]
50
75 85
40
35
30
25
20
15
10
5
0
(S-8253DAA)
0
5
10
15
VDD [V]
20
(S-8253DAA)
40
35
30
25
20
15
10
5
0
−40 −25
0
25
Ta [°C]
50
75 85
IPDN vs. VDD
(S-8253CAA)
IPDN [μA]
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
5
10
15
VDD [V]
20
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
(S-8253DAA)
0
5
10
15
VDD [V]
20
IPDN vs. Ta
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
−40 −25
(S-8253CAA)
IPDN [μA]
1. 3
(S-8253CAA)
IOPE vs. Ta
IOPE [μA]
1. 2
40
35
30
25
20
15
10
5
0
IOPE [μA]
IOPE [μA]
1. 1
IPDN [μA]
1.
IPDN [μA]
0
25
Ta [°C]
50
75 85
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
−40 −25
(S-8253DAA)
0
25
Ta [°C]
50
75 85
25
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Overcharge Detection / Release Voltage, Overdischarge Detection / Release Voltage, Overcurrent
Detection Voltage, and Delay Times (S-8253CAA, S-8253DAA)
0
25
Ta [°C]
50
7585
2. 4
VDL [μA]
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
2.64
2.62
2.60
−40 −25
0
25
Ta [°C]
50
75 85
tCU vs. Ta
tCU [ms]
2. 5
4.375
4.370
4.365
4.360
4.355
4.350
4.345
4.340
4.335
4.330
4.325
−40 −25
VDU vs. Ta
VDU [μA]
2. 3
2. 2
VCL [μA]
VCU vs. Ta
VCU [μA]
2. 1
2. 6
0
25
Ta [°C]
50
50
75 85
0
25
Ta [°C]
50
75 85
0
25
Ta [°C]
50
75 85
tDL vs. Ta
145
135
115
−40 −25
75 85
2. 8
VIOV1 [V]
0.325
0.320
0.315
0.310
0.305
0.300
0.295
0.290
0.285
0.280
0.275
25
Ta [°C]
125
VIOV1 vs. VDD
VIOV1 [V]
2.48
2.46
2.44
2.42
2.40
2.38
2.36
2.34
2.32
−40 −25
155
1120
0
VDL vs. Ta
1220
920
−40 −25
26
4.10
4.09
4.08
4.07
4.06
4.05
4.04
4.03
4.02
4.01
4.00
−40 −25
173
165
1020
2. 7
VCL vs. Ta
1380
1320
tDL [ms]
2.
Rev.2.5_00
7
8
9
10
11
VDD [V]
12
13
VIOV1 vs. Ta
0.325
0.320
0.315
0.310
0.305
0.300
0.295
0.290
0.285
0.280
0.275
−40 −25
0
25
Ta [°C]
50
75 85
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
Rev.2.5_00
7
8
9
10
11
VDD [V]
12
13
VIOV2 [V]
VIOV3 vs. VDD
2. 12
1.4
1.3
1.3
1.2
1.1
7
8
9
10
11
VDD [V]
12
2. 14
tIOV1 [ms]
tIOV1 [ms]
7
8
9
10
11
VDD [V]
12
13
2. 16
tIOV2 [ms]
tIOV2 [ms]
50
75 85
1.2
1.1
0.9
−40 −25
13
tIOV2 vs. VDD
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
25
Ta [°C]
1.0
tIOV1 vs. VDD
10.8
10.4
10.0
9.6
9.2
8.8
8.4
8.0
7.6
7.2
0
VIOV3 vs. Ta
1.4
0.9
2. 15
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
0.40
−40 −25
1.5
1.0
2. 13
VIOV2 vs. Ta
1.5
VIOV3 [V]
VIOV3 [V]
2. 11
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
0.40
2. 10
VIOV2 [V]
VIOV2 vs. VDD
2. 9
7
8
9
10
11
VDD [V]
12
13
0
25
Ta [°C]
50
75 85
0
25
Ta [°C]
50
75 85
0
25
Ta [°C]
50
75 85
tIOV1 vs. Ta
10.8
10.4
10.0
9.6
9.2
8.8
8.4
8.0
7.6
7.2
−40 −25
tIOV2 vs. Ta
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
−40 −25
27
BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK
S-8253C/D Series
tIOV3 vs. VDD
3.
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
2. 18
tIOV3 vs. Ta
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
−40 −25
tIOV3 [ms]
tIOV3 [ms]
2. 17
7
8
9
10
11
VDD [V]
12
13
0
25
Ta [°C]
50
75 85
COP / DOP Pin (S-8253CAA, S-8253DAA)
3. 1
ICOH vs. VCOP
3. 2
ICOL vs. VCOP
0.10
ICOL [mA]
ICOH [μA]
0.08
0.06
0.04
0.02
0
3. 3
0
4
8
12
16
VCOP [V]
20
IDOH vs. VDOP
3. 4
IDOL [mA]
IDOH [mA]
−1.0
−1.5
−2.0
0
1.8
VDOP [V]
3.6
5.4
0
3.
VCOP [V]
7.0
10.5
7.0
10.5
IDOL vs. VDOP
−0.5
−2.5
14
12
10
8
6
4
2
0
24
0
28
Rev.2.5_00
14
12
10
8
6
4
2
0
0
3.5
VDOP [V]
+0.3
3.00 -0.2
8
5
1
4
0.17±0.05
0.2±0.1
0.65
No. FT008-A-P-SD-1.2
TITLE
TSSOP8-E-PKG Dimensions
No.
FT008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
0.3±0.05
+0.1
8.0±0.1
ø1.55 -0.05
(4.4)
+0.4
6.6 -0.2
1
8
4
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-SD-1.0
TITLE
TSSOP8-E-Reel
No.
FT008-E-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-S1-1.0
TITLE
TSSOP8-E-Reel
FT008-E-R-S1-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
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caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com