STK15C88
256 Kbit (32K x 8) PowerStore nvSRAM
Functional Description
■
25 ns and 45 ns Access Times
■
Pin compatible with Industry Standard SRAMs
■
Automatic Nonvolatile STORE on power loss
■
Nonvolatile STORE under Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited Read/Write Endurance
■
Unlimited RECALL Cycles
■
1,000,000 STORE Cycles
The Cypress STK15C88 is a 256Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap™ technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations are also
available under software control.
■
100 year Data Retention
■
Single 5V+10% Power Supply
■
Commercial and Industrial Temperatures
■
28-pin (300 mil and 330 mil) SOIC packages
■
RoHS Compliance
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Features
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PowerStore nvSRAM products depend on the intrinsic system
capacitance to maintain system power long enough for an
automatic store on power loss. If the power ramp from 5 volts
to 3.6 volts is faster than 10 ms, consider our 14C88 or 16C88
for more reliable operation.
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-50593 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 11, 2009
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STK15C88
Contents
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Data Retention and Endurance ......................................... 8
Capacitance ........................................................................ 8
Thermal Resistance ............................................................ 8
AC Test Conditions ............................................................ 8
AC Switching Characteristics ........................................... 9
SRAM Read Cycle ........................................................ 9
Switching Waveforms ........................................................ 9
Switching Waveforms ......................................................10
AutoStore or Power Up RECALL ....................................11
Switching Waveforms ......................................................11
Software Controlled STORE/RECALL Cycle ..................12
Part Numbering Nomenclature ........................................13
Ordering Information ........................................................13
Package Diagrams ............................................................14
Sales, Solutions and Legal Information .........................16
Worldwide Sales and Design Support......................... 16
Products ...................................................................... 16
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Features ...............................................................................1
Functional Description .......................................................1
Logic Block Diagram ..........................................................1
Contents ..............................................................................2
Pin Configurations .............................................................3
Device Operation ................................................................4
SRAM Read .........................................................................4
SRAM Write .........................................................................4
AutoStore Operation ..........................................................4
Hardware RECALL (Power Up) ..........................................4
Software STORE .................................................................4
Software RECALL ...............................................................4
Hardware Protect ................................................................5
Noise Considerations .........................................................5
Low Average Active Power ................................................5
Best Practices .....................................................................5
Maximum Ratings ...............................................................7
DC Electrical Characteristics ............................................7
Document Number: 001-50593 Rev. *A
Page 2 of 16
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STK15C88
Pin Configurations
Figure 1. Pin Diagram - 28-Pin SOIC
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Table 1. Pin Definitions - 28-Pin SOIC
Pin Name
Alt
I/O Type
A0–A14
Input
DQ0-DQ7
Input or
Output
WE
CE
OE
VSS
VCC
Description
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Bidirectional Data I/O lines. Used as input or output lines depending on operation.
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Ground
Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-50593 Rev. *A
Page 3 of 16
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STK15C88
Device Operation
Software STORE
The STK15C88 is a versatile memory chip that provides
several modes of operation. The STK15C88 can operate as a
standard 32K x 8 SRAM. It has a 32K x 8 nonvolatile element
shadow to which the SRAM information can be copied, or from
which the SRAM can be updated in nonvolatile mode.
Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK15C88 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of
the nonvolatile elements. When a STORE cycle is initiated,
input and output are disabled until the cycle is completed.
SRAM Write
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Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, the sequence is aborted and no STORE or RECALL
takes place.
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To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
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The STK15C88 performs a READ cycle whenever CE and OE
are LOW while WE is HIGH. The address specified on pins
A0–14 determines the 32,768 data bytes accessed. When the
READ is initiated by an address transition, the outputs are
valid after a delay of tAA (READ cycle 1). If the READ is
initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the tAA access
time without the need for transitions on any control input pins,
and remains valid until another address change or until CE or
OE is brought HIGH.
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SRAM Read
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles are used
in the sequence. It is not necessary that OE is LOW for a valid
sequence. After the tSTORE cycle time is fulfilled, the SRAM is
again activated for READ and WRITE operation.
AutoStore Operation
Software RECALL
The STK15C88 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long as the
system power supply takes at least tSTORE to decay from
VSWITCH down to 3.6V, the STK15C88 will safely and automatically store the SRAM data in nonvolatile elements on power
down.
Data is transferred from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner
similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE controlled READ
operations is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
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A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common I/O pins
DQ0–7 are written into the memory if it has valid tSD, before the
end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If OE
is left LOW, internal circuitry turns off the output buffers tHZWE
after WE goes LOW.
In order to prevent unneeded STORE operations, automatic
STOREs will be ignored unless at least one WRITE operation
has taken place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are performed
regardless of whether a WRITE operation has taken place.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC <
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
If the STK15C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.
Document Number: 001-50593 Rev. *A
Internally, RECALL is a two step procedure. First, the SRAM
data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the
SRAM is once again ready for READ and WRITE operations.
The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an
unlimited number of times.
Page 4 of 16
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STK15C88
Hardware Protect
Figure 3. Current Versus Cycle Time (READ)
The STK15C88 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage conditions. When VCAP (VCC – 0.2V). All other inputs cycling.
at tRC= 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained
without output loads.
25°C Typical
Average Current
during AutoStore
Cycle
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
Average VCC Current tRC=25ns, CE > VIH
tRC=45ns, CE > VIH
(Standby, Cycling
TTL Input Levels)
VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
(Standby, Stable
CMOS Input Levels)
Input Leakage
Current
VCC = Max, VSS < VIN < VCC
-1
+1
μA
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
-5
+5
μA
Input HIGH Voltage
2.2
VCC +
0.5
V
Input LOW Voltage
VSS –
0.5
0.8
V
Output HIGH Voltage IOUT = –4 mA
Output LOW Voltage IOUT = 8 mA
2.4
V
0.4
V
Note
3. CE > VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Document Number: 001-50593 Rev. *A
Page 7 of 16
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STK15C88
Data Retention and Endurance
Parameter
Description
DATAR
Data Retention
NVC
Nonvolatile STORE Operations
Min
Unit
100
Years
1,000
K
Capacitance
In the following table, the capacitance parameters are listed.[4]
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0 V
5
7
pF
Thermal Resistance
(Junction to Case)
m
28-SOIC
(300 mil)
28-SOIC
(330 mil)
Unit
TBD
TBD
°C/W
TBD
TBD
°C/W
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Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.
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ΘJC
Thermal Resistance
(Junction to Ambient)
Test Conditions
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ΘJA
Description
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In the following table, the thermal resistance parameters are listed.[4]
Parameter
pF
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Thermal Resistance
Unit
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Description
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Parameter
Figure 4. AC Test Loads
R1 480Ω
5.0V
Output
30 pF
R2
255Ω
AC Test Conditions
Input Pulse Levels .................................................. 0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................