4-Character 5 x 7 Dot Matrix
Alphanumeric Programmable DisplayTM with Built-in CMOS Control Functions
Lead (Pb) Free Product - RoHS Compliant
PD243X, PD353X, PD443X
PD243X
PD353X
PD443X
DESCRIPTION
FEATURES
• Four Dot Matrix Characters in High Efficiency Red,
Red, and Bright Green
- PD2435/6/7, 5.08 mm (0.200") High
- PD3535/6/7, 6.86 mm (0.270") High
- PD4435/6/7, 11.43 mm (0.45") High
• Built-in Memory, Decoders, Multiplexer and Drivers
• Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°
• Categorized for Luminous Intensity
• 128 Character ASCII Format (Upper and Lower Case
Characters)
• 8 Bit Bidirectional Data BUS
• READ/WRITE Capability
• Dual In-Line Package Configuration, 15.2 mm (0.600")
Wide,
2.54 mm (0.100") Pin Centers
• End-Stackable Package
• Internal or External Clock
• Built-in Character Generator ROM
• TTL Compatible
• Easily Cascaded for Multidisplay Operation
• Less CPU Time Required
• Software Controlled Features:
- Programmable Highlight Attribute (Blinking,
Non-Blinking)
- Asynchronous Memory Clear Function
- Lamp Test
- Display Blank Function
- Single or Multiple Character Blinking Function
- Programmable Intensity (Three Brightness Levels)
• Extended Operating Temperature Range:
• PD243X, PD353X: –40°C to +85°C
• PD443X: –40°C to +70°C
These Programmable Displays are four digit display system modules. The characters are
5.08 mm by 3.56 mm (0.20" by 0.14") (PD243X),
6.86 mm by 5.08 mm (0.27" by 0.20") (PD353X), and
11.43 mm by 6.86 mm (0.45" by 0.27") (PD443X)
5 x 7 dot matrix arrays constructed with the latest solid
state technology in light emitting diodes. Driving and
controlling the LED arrays is a silicon gate CMOS integrated circuit. This integrated circuit provides all necessary LED drivers and complete multiplexing control
logic.
Additionally, the IC has the necessary ROM to decode
128 ASCII alphanumeric characters and enough RAM to
store the display’s complete four digit ASCII message
with special attributes. These attributes, all software programmable at the user’s discretion, include a lamp test,
brightness control, displaying cursors, alternating cursors
and characters, and flashing cursors or characters.
The CMOS IC also incorporates special interface control
circuitry to allow the user to control the module as a fully
supported microprocessor peripheral. The module, under
internal or external clock control, has asynchronous
read, write, and memory clear over an eight bit parallel,
TTL compatible, bi-directional data bus. Each module is
fully encapsulated within a package
25.4 x 17.8 x 5.08 mm (1.0" x 0.7" x 0.2") (PD253X),
35.6 x 18.3 x 7.24 mm (1.4" x 0.72" x 0.285") (PD353X),
and
38.1 x 20.8 x 7.24 mm (1.5" x 0.82" x 0.285") (PD443X).
The standard 20 pin DIP construction with two rows
spaced at 15.2 mm (0.6") on 2.54 mm (0.1") centers is
wave solderable.
See the end of this data sheet or refer to Appnotes 18, 19,
22, and 23 for further details on handling and assembling
OSRAM Programmable Displays.
2006-01-23
1
PD243X, PD353X, PD443X
Ordering Information
Type
2006-01-23
Color of Emission
Character Height
mm (inch)
Ordering Code
PD2435
PD2436
PD2437
high efficiency red
red
bright green
5.08
(0.200)
Q68000A3561
Q68000A8366
Q68000A3562
PD3535
PD3536
PD3537
high efficiency red
red
bright green
6.86
(0.270)
Q68000A7964
Q68000A8365
Q68000A7965
PD4435
PD4436
PD4437
high efficiency red
red
bright green
11.43
(0.450)
Q68000A8367
Q68000A8368
Q68000A8369
2
PD243X, PD353X, PD443X
Maximum Ratings
Top
Storage temperature range
Tstg
Viewing angle (off normal axis)
2ϕ
hor. (typ.)
ver. (typ.)
– 40 … + 85
–40…+70 °C
– 40 … +100
± 55
± 65
± 55
± 65
DC Supply Voltage
Input Voltage Relative to GND (all inputs)
Solder temperature
1.59 mm (0.063“) below seating plane, t < 5.0 s
Unit
PD443X
Operating temperature range
Values
PD353X
Symbol
PD243X
Parameter
°C
± 40
± 65
deg
deg.
-0.5 to + 7.0
Vdc
-0.5 to VCC +0.5
Vdc
Ts
260
°C
Values
Unit
Wavelength at peak emission
IF = 50 mA
(typ.)
Character Height
PDx437
Symbol
PDx435
Parameter
PDx436
Characteristics
(TA = 25 °C)
high
red
efficiency
red
green
λpeak
630
660
565
nm
h
0.145
3.7
0.145
3.7
0.145
3.7
inch
mm
µcd/LED
Time averaged luminous intensity1)
(min.)
90
30
90
LED to LED intensity matching
(max.)
1.8:1.0
1.8:1.0
1.8:1.0
Device to Device (one bin)
(max.)
1.5:1.0
1.5:1.0
1.5:1.0
Bin to Bin (adjacent bins)
(max.)
1.9:1.0
1.9:1.0
1.9:1.0
1)
Peak luminous intensity values can be calculated by multiplying these values by 7.
2006-01-23
3
PD243X, PD353X, PD443X
PD243X Z
OSRAM
YYWW
EIA Date Code
Luminous
Intensity
V
Code
2.54 (0.100) typ.
0.46 (0.018) x 0.31 (0.012) typ.
1.27 (0.050)
5.08 (0.200)
Dimensions in mm (inch)
Pin 1 Indicator
4.06 (0.160) ±0.51 (0.020)
PD243X
15.24 (0.600)
At Seating Plane
and centered
on package
1.78 (0.070) typ. ±0.1 (0.004)
25.4 (1.000) max.
6.35 (0.250) 3.56 (0.140)
5.08 (0.200)
17.78 (0.700)
3.18 (0.125)
Pin 1
Location
Tolerance: 0.51 (0.020)
IDOD5016
Dimensions in mm (inch)
2.54 (0.100) typ.
0.46 (0.018) x 0.31 (0.012) typ.
11.43 (0.450)
7.24 (0.285)
Pin 1 Identifier and ESD Warning
EIA Date Code
Part No.
Luminous
Intensity
PD353X Z
Code
OSRAM
YYWW
V
4.06 (0.160) ±0.51 (0.020)
PD353X
15.24 (0.600)
At Seating Plane
and centered
on package
6.35 (0.250)
35.56 (1.400) max.
8.89 (0.350) typ.
5.08 (0.200) typ.
6.86 (0.270) typ.
18.29 (0.720) max.
4.45 (0.175)
Tolerance: 0.25 (0.010) unless max.
IDOD5017
2006-01-23
4
PD243X, PD353X, PD443X
Dimensions in mm (inch)
PD443X Z
OSRAM
EIA Date Code
Luminous
Intensity
Code
YYWW
V
2.54 (0.100) typ.
0.46 (0.018) x 0.31 (0.012) typ. ±0.05 (0.002)
15.24 (0.600)
7.24 (0.285)
Pin 1 Indicator
Part No.
4.06 (0.160) ±0.51 (0.020)
PD443X
15.24 (0.600) typ.
At seating plane
and centered
on package
7.62 (0.300)
38.1 (1.500) max.
9.53 (0.375) typ.
1.27 (0.050)
20.83 (0.820) max.
11.43 (0.450) ±0.25 (0.010)
6.86 (0.270) typ.
Tolerance: 0.51 (0.020)
IDOD5018
Top View
20
Digit 3
11
Digit 2
Digit 1
1
Digit 0
10
20
11
Digit 3
Digit 2
Digit 1
1
20
Digit 0
10
11
Digit 3
Digit 2
Digit 1
1
Digit 0
10
IDPA5109
2006-01-23
5
PD243X, PD353X, PD443X
Timing Characteristics—Data “Write” Cycle
Timing Characteristics—Data “Read” Cycle
2.0 V
0.8 V *
CE0, CE1
TCES
TCEH
TAS
TAH
2.0 V
0.8 V *
A0, A1
TDS
TCES
TCEH
TAS
TAH
2.0 V
0.8 V *
A0–A3
2.0 V
0.8 V *
D0–D6
2.0 V
0.8 V *
CE0, CE1
TRS
TDH
TRI
TDD
2.0 V
0.8 V *
RD
TRH
WR
WR
2.0 V
0.8 V *
2.0 V
0.8 V *
DATA OUT
D0–D6
TDH
TWS
2.0 V
0.8 V *
TWH
RD
2.0 V
0.8 V *
TW
TR
TRACC
TACC
Notes:
1. Wait 1.0 µs between any Reads or Writes after writing a Control
Word with a Clear (D7=1). Wait 1.0 µs between any Reads or
Writes after Clearing a Control Word with a Clear (D7=0). All
other Reads and Writes can be back to back.
2. All input voltages are VIL=0.8 V, VIH=2.0 V.
3. These waveforms are not edge triggered.
4. Data out voltages are measured with 100 pF on the data bus
and the ability to source = –40 mA and sink=1.6 mA The rise and
fall times are 60 ns. VOL=0.4 V, VOH=2.4 V.
Switching Specifications (VCC=4.5 V)
Switching Specifications (VCC=4.5 V)
Write Cycle Timing
Parameter
Description
TCLR(1)
Read Cycle Timing
Specification Minimum
Parameter
Description
–40°C
25°C
85°C
Units
µs
TAS
Address Setup
0
0
0
ns
1.0
µs
TCES
Chip Enable
0
0
0
ns
10
10
ns
TWS
Write Enable Setup
20
30
40
ns
0
0
0
ns
TDD
Data Delay Time
100
150
175
ns
Read Enable Setup
10
10
10
ns
TR
Read Pulse
150
175
200
ns
TDS
Data Setup
20
30
50
ns
TAH
Address Hold
0
0
0
ns
TW
Write Pulse
60
70
90
ns
TDH
Data Hold
0
0
0
ns
TAH
Address Hold
20
30
40
ns
TTRI
30
40
50
ns
TDH
Data Hold
20
30
40
ns
Time to Tristate
(Max. time)
TCEH
Chip Enable Hold
0
0
0
ns
TCEH
Chip Enable Hold
0
0
0
ns
TWH
Write Enable Hold
30
40
50
ns
TACC
Total Access
Time = Setup
Time + Read
Time + Time to
Tristate
200
245
290
ns
TWAIT (1)
Wait Time between
Reads
0
0
0
ns
–40°C
25°C
85°C
Units
Clear RAM
1.0
1.0
1.0
TCLRD(1)
Clear RAM Disable
1.0
1.0
TAS
Address Setup
10
TCES
Chip Enable Setup
TRS
TRH
TACC
Read Enable Hold
Total Access
Time = Setup
Time + Write
Time + Hold Time
2006-01-23
20
90
30
110
40
140
ns
ns
6
Specification Minimum
PD243X, PD353X, PD443X
DC Characteristics at 25°C
Parameter
Limits
Conditions
Min.
Typ.
Max.
Units
VCC
4.5
5.0
5.5
Volts
Nominal
ICC (Blank)
—
2.5
3.5
mA
VCC=5.0 V, A2 = 1, all other inputs low.
ICC 80 LEDs/unit (100% Bright)
PD243X
PD353X
PD443X
—
115
145
150
130
165
170
mA
mA
mA
VCC=5.0 V
VCC=5.0 V
VCC=5.0 V
VIL
—
—
0.8
Volts
VCC=4.5 V to 5.5 V
VIH
2.0
—
—
Volts
VCC=4.5 V to 5.5 V
IIL (except D0 to D7) (1)
25
—
100
µA
VCC=4.5 V to 5.5 V, VIN =0.8 V
VOL
—
—
0.4
Volts
VCC=4.5 V to 5.5 V
VOH
2.4
—
—
Volts
VCC=4.5 V to 5.5 V
IOH
–8.9
—
—
mA
VCC=4.5 V, VOH=2.4 V
IOL
1.6
—
—
mA
VCC=4.5 V, VOL=0.4 V
Data I/O Bus Loading
—
—
100
pF
—
Clock I/O Bus Loading
—
—
240
pF
—
1)
D0 to D7 have no pull-up resistors so current is negligible.
Pin Assignments and Definitions
Pin
Function
Definition
Pin
Function
Definition
1
RD
Active low, will enable a processor to read all
registers in the display.
11
WR
Write. Active low. If the device is selected, a
low on the write input loads the data into memory.
2
CLK I/O
If CLK SEL (pin 3) is low, then expect an external clock source into this pin. If CLK SEL is
high, then this pin will be the master or source
into this pin. If CLK SEL is high, then this pin
will be the master or source for all other
devices which have CLK SEL low.
12
D7
Data Bus bit 7 (MSB).
3
CLKSEL
CLOCK SELECT determines the action of pin
2. CLK I/O, see the section on Cascading for
an example.
13
D6
Data Bus bit 6.
4
RST
Reset. Used to synchronize blinking. Will not
clear the display. The reset pulse should be
less than 1 ms
14
D5
Data Bus bit 5.
5
CE1
Chip enable (active high).
15
D4
Data Bus bit 4.
6
CE0
Chip enable (active low).
16
D3
Data Bus bit 3.
7
A2
Address input (MSB).
17
D2
Data Bus bit 2.
8
A1
Address input.
18
D1
Data Bus bit 1.
9
A0
Address input (LSB).
19
D0
Data Bus bit 0 (LSB).
10
GND
Ground.
20
VCC
Positive power pin.
2006-01-23
7
PD243X, PD353X, PD443X
Functional Description
The block diagram includes 5 major blocks and internal registers
(indicated by dotted lines).
Display Memory consists of a 5 x 8 bit RAM block. Each of the
four 8-bit words holds 7-bits of ASCII data (bits D0–D6) and an
attribute select bit (Bit D6). The fifth 8-bit memory word is used
as a control word register. A detailed description of the control
register and its functions can be found in the Control Word section. Each 8-bit word is addressable and can be read from or written to.
The Control Logic dictates all of the features of the display
device and is discussed in the Control Word section of this data
sheet.
The Character Generator converts the 7-bit ASCII data into the
proper dot pattern for the 128 characters shown in the character
set chart.
The Clock Source can originate either from the internal oscillator
clock or from an external source—usually from the output of
another display in a multiple module array.
The Display Multiplexer controls all display output to the digit
drivers so no additional logic is required for a display system.
The Column Drivers are connected directly to the display.
The Display has four digits. Each of the four digits is com-prised of
35 LEDs in a 5 x 7 dot array which makes up the alphanumeric
characters.
The intensity of the display can be varied by the Control Word in
steps of 0% (Blank), 25%, 50%, and full brightness.
The Reset pin when activated clears the internal counter. A reset is
usually done after power up and is of very short duration-nanoseconds or microseconds. If the reset pin is held low for a longer time
(milliseconds) some or all LEDs in the bottom row may light up. The
appearance of lit LEDs during a “reset” is not an indication of a malfunctioning part. It is advisable to keep the reset pulse as short as
possible to avoid displaying a row of lit LEDs.
Input Buffering
If a cable length of 6 inches or more is used, all inputs to the display
should be buffered with a tri-state non-inverting buffer mounted as
close to the display as conveniently possible. Recommended
buffers are: 74LS245 for the data lines and 74LS244 for the control
lines.
Block Diagram
8
D0-D7
14
Control
Reg
1x8
Display Memory
(RAM) 4 x 8
128 Char
ROM
128 x 5
8
4
15
1
CE0, CE1
A0-A2
RD, WR
Decode
and
Mux
7
5
Output
Control
Logic
Output
Latch
1
CLK SEL
XCLK
RST
3
OSC
Logic
3
20
Column
Drivers
Display
Multiplexer
3
20
Row
Drivers
Display
IDBD5065
Mode Selection
Microprocessor Interface
The interface to the microprocessor is through the address lines.
(A0–A2), the data bus (D0–D7), two chip select lines (CE0, CE1),
and read (RD) and write (WR) lines.
The CE0 should be held low when executing a read, or write operation. CE1 must be held high.
The read and write lines are both active low. During a valid read
the data input lines (D0–D7) become outputs. A valid write will
enable the data as input lines.
CEO
CE1
RD
WR
Operation
0
1
0
0
None
1
X
X
X
None
X
0
X
X
None
X
X
1
1
None
0=Low logic level, 1=High logic level, X=Don’t care
Data Input Commands
CEO
CE1
RD
WR
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
No Change
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
Read Digit 0 Data to Bus
0
1
1
0
1
0
0
0
0
1
0
0
1
0
0
($) Written to Digit 0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
(W) Written to Digit 1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
(f) Written to Digit 2
0
1
1
0
1
1
1
0
0
1
1
0
0
1
1
(3) Written to Digit 3
0
1
1
0
1
0
0
1
X
X
X
X
X
X
X
Char. Written to Digit 0 and
Cursor Enabled
2006-01-23
8
PD243X, PD353X, PD443X
There are five registers within the display. Four of these registers
are used to hold the ASCII/attribute code of the four display characters. The fifth register is the Control Word, which is used to blink,
blank, clear, or dim the entire display, or to change the presentation (attributes) of individual characters.
Control Word
When address bit A2 is taken low, the Control Word is accessed.
The same Control Word appears in all four of the lower address
spaces of the display. Through the Control Word, the display can
be cleared, the lamps can be tested, display brightness can be
selected, and attributes can be set for any characters which have
been loaded with their most significant bit (D7) set high.
Brightness (D0, D1): The state of the lower two bits of the Control
Word are used to set the brightness of the entire display, from 0%
to 100%. The table below shows the correspondence of these bits
to the brightness.
Adressing
The addresses within the display device are shown below. Digit 0
is the rightmost digit of the display, while digit 3 is on the left.
Although there is only one Control Word, it is duplicated at the four
address locations 0–3. Data can be read from any of these locations. When one of these locations is written to, all of them will
change together.
Address
Contents
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
X
X
X
X
0
0
Blank
0
0
X
X
X
X
0
1
25% brightness
A2
A1
A0
0
X
X
Control Word
0
0
X
X
X
X
1
0
50% brightness
1
0
0
Digit 0 (rightmost)
0
0
X
X
X
X
1
1
Full brightness
1
0
1
Digit 1
X = don't care
1
1
0
Digit 2
1
1
1
Digit 3 (leftmost)
Attributes (D2–D4): Bits D2, D3, and D4 control the visual
attributes (i.e., blinking) of those display digits which have been
written with bit D7 set high. In order to use any of the four
attributes, the Cursor Enable bit (D4 in the Control Word) must be
set. When the Cursor Enable bit is set, and bit D7 in a character
location is set, the character will take on one of the following display attributes.
Bit D7 of any of the display digit locations is used to allow an attribute to be assigned to that digit. The attributes are discussed in
the next section. If Bit D7 is set to a one, that character will be displayed using the attribute. If bit D7 is cleared, the character will display normally.
Control Word Format
D7
D6
D5
D4
Clear
Lamp
Test
Blink
Attribute
Enable
D3
D2
Attributes
D1
D0
Brightness
D1
0
0
D3 D2 Attributes
1
0 0 Display cursor instead
1
of character
0 1 Blink character
1 0 Display blinking cursor
instead of character
1 1 Alternate character
with cursor
D0
0
1
0
1
Brightness
0% (blank)
25%
50%
100%
D4 Attribute Enable
0 Disable above attributes
1 Enable above attributes
D5 Blink
0 Blink attribute disabled
1 Blink entire display
D6 Lamp Test
0 Standard operation
1 Display all dots at 50% brightness
D7 Clear
0 Standard operation
1 Clear entire display
IDCW5163
2006-01-23
9
PD243X, PD353X, PD443X
D7
D6
D5
D4
D3
D2
D1
D0
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
X
X
B
B
Disable highlight attribute
0
0
1
X
X
X
B
B
Blinking display
0
0
0
1
0
0
B
B
Display cursor*
instead of
character
0
0
0
1
0
1
B
B
Blink single
character
0
0
0
1
1
0
B
B
Display blinking cursor*
instead of character
0
0
0
1
1
1
B
B
Lamp Test (D6): When the Lamp Test bit is set, all dots in the
entire display are lit at half brightness. When this bit is cleared, the
display returns to the characters that were showing before the
lamp test.
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
1
0
X
X
X
X
X
Lamp test
Clear Data (D7): When D7 is set (D7=1) in the Control Word, all (display) memory bits are reset to zero and the display goes blank.
Alternate character with cursor*
*“Cursor”= all dots in a single character space lit to half brightness
X = Don't care
B = Depends on the selected brightness.
D7
D6
D5
D4
D3
D2
D1
D0
Operation
1
0
X
X
X
X
X
X
Clear
A second control word must be written into the chip with D7 reset
(D7=0) to set up attributes and brightness levels.
Attributes are non-destructive. If a character with bit D7 set is
replaced by a cursor (Control Word bit D4 is set, and D3=D2=0)
the character will remain in memory and can be revealed again by
clearing D4 in the Control Word.
Blink (D5): The entire display can be caused to blink at a rate of
approximately 2.0 Hz by setting bit D5 in the Control Word. This blinking is independent of the state of D7 in all character locations.
To synchronize the blink rate in a bank of these devices, it is necessary to tie all devices' clocks and resets together as described in
a later section of this data sheet.
The SMC- 4740 oscillator is designed to drive up to 16 displays
with input loading of 15 pF each.
The general requirements for cascading 16 displays are:
1.Determine the correct address for each display.
2.Tie CE0 to ground and use CE1 from an address.
3.Select one of the displays to provide the clock for the
other displays.
4.Tie CLKSEL to ground on other displays.
5.Use RST to synchronize the blinking between the displays.
Cascading Diagram
RST
RD
WR
VCC
WR
RD
RST CLK CLK
I/O SEL
Programmable Display
D0-D7 A0-A2
CE0
WR
14 more displays
in between
CE1
RST CLK CLK
I/O SEL
Programmable Display
RD
D0-D7 A0-A2
CE0
CE1
Data I/O
Address
A4
A5
Address
Decoder
Address Decode Chip 1 to 14
A6
IDCD5032
2006-01-23
10
PD243X, PD353X, PD443X
How to Load Information Into the Display
Information loaded into the display can be either ASCII data or
Control Word data. The following procedure (see also Typical
Loading Sequence) will demonstrate a typical loading sequence
and the resulting visual display. The word STOP is used in all of
the following examples.
Set Brightness
Step 1
Set the brightness level of the entire display to
your preference (example: 100%)
Load Four Characters
Step 2
Load an “S” in the left hand digit.
Step 3
Load a “T” in the next digit.
Step 4
Load an “O” in the next digit.
Step 5
Load a “P” in the right hand digit.
If you loaded the information correctly, the display
now should show the word “STOP.”
Blink a Single Character
Step 6
Into the digit, second from the right, load the hex
code “CF,” which is the code for an “O” with the
D7 bit added as a control bit.
Add Another Blinking Character
Into the left hand digit, load the hex code “D3”
which gives an “S” with the D7 bit added as a
control bit. The display should show “STOP”
with flashing “O” and a flashing “S.”
Alternate Character/Cursor Enable
Load enable alternate character/cursor into the
control word register. The display now should
show “STOP” with the “O” and the “S” alternating
between the letter and cursor (all dots lit).
Initiate Four Character Blinking
(Regardless of Control Bit setting)
Load enable display blinking. The display now
should show the entire word “STOP” blinking.
Step 8
Step 9
Step 10
Note:
The “O” is the only digit which has the control bit
(D7) added to normal ASCII data.
Load enable blinking character into the control
word register. The display should show “STOP”
with a flashing “O”.
Step 7
Typical Loading Sequence
CEO
CE1
RD
WR
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1.
L
H
H
L
L
X
X
0
0
0
0
0
0
1
1
2.
L
H
H
L
H
H
H
0
1
0
1
0
0
1
1
S
3.
L
H
H
L
H
H
L
0
1
0
1
0
1
0
0
ST
4.
L
H
H
L
H
L
H
0
1
0
0
1
1
1
1
STO
5.
L
H
H
L
H
L
L
0
1
0
1
0
0
0
0
STOP
6.
L
H
H
L
H
L
H
1
1
0
0
1
1
1
1
STOP
7.
L
H
H
L
L
X
X
0
0
0
1
0
1
1
1
STO*P
8.
L
H
H
L
H
H
H
1
1
0
1
0
0
1
1
S*TO*P
9.
L
H
H
L
L
X
X
0
0
0
1
1
1
1
1
S†TO†P
10.
L
H
H
L
L
X
X
0
0
1
0
0
0
1
1
S*T*O*P*
* Blinking character
† Character alternating with cursor (all dots lit)
2006-01-23
11
Display
PD243X, PD353X, PD443X
Electrical and Mechanical Considerations
The CMOS IC of the display is designed to provide resistance to
both Electrostatic Discharge Damage and Latch Up due to voltage
or current surges. Several precautions are strongly recommended
to avoid overstressing these built-in safeguards.
Power Down Sequence
1.Float all active signals by tri-stating the inputs to the display.
2.Turn off the power to the display.
Soldering Considerations
These displays can be hand soldered with SN63 solder using a
grounded iron set to 260°C.
Wave soldering is also possible following these conditions: Preheat that does not exceed 93°C on the solder side of the PC board
or a package surface temperature of 85°C. Water soluble organic
acid flux (except carboxylic acid) or rosin-based RMA flux without
alcohol can be used.
Wave temperature is 245°C ±5°C with a dwell between 1.5 sec to
3.0 sec. Exposure to the wave should not exceed temperatures
above 260°C, for 5 sec at 1.59 mm (0.063") below the seating
plane. The packages should not be immersed in the wave.
ESD Protection
Display users should be careful to handle the devices consistent
with Standard ESD protection procedures. Operators should wear
appropriate wrist, ankle or feet ground straps and avoid clothing
that collects static charges. Work surfaces, tools and transport carriers that come into contact with unshielded devices or assemblies
should also be appropriately grounded.
Latch up Protection
Latch up is a condition that occurs in CMOS ICs after the input
protection diodes have been broken down. These diodes can be
reversed through several means:
VIN < GND, VIN > VCC + 0.5 V, or through excessive currents forced
on the inputs. When these situations exist, the IC may develop the
response of an SCR and begin conducting as much as one amp
through the VCC pin. This destructive condition will persist (latched)
until device failure or the device is turned off.
Voltage Transient Suppression
It has become common practice to provide 0.01 µF bypass capacitors liberally in digital systems. Like other CMOS circuitry, the
Intelligent Display controller chip has very low power consumption
and the usual 0.01 µF would be adequate were it not for the
LEDs. To prevent power supply transients, capacitors with low
inductance and high capacitance at high frequencies are
required. This suggests a solid tantalum or ceramic disc for high
frequency bypass. For multiple display module systems distribute
the bypass capacitors evenly, keeping capacitors as close to the
power pins as possible. Use a 0.01 µF capacitor for each display
module and a 22 µF for every third display module.
The Voltage Transient Suppression Techniques and buffer interfaces for longer cable runs help considerably to prevent latch conditions from occurring. Additionally, the following Power Up and
Power Down sequence should be observed.
Power up Sequence
1. Float all active signals by tri-stating inputs to displays.
2. Apply VCC and GND to the display.
3. Apply active signals to the displays by enabling all input
signals per application.
Notes:
1. A2 must be held high for ASCII data.
2. Bit D7=1 enables attributes for the assigned digit.
Character Set
D0
D1
D2
D3
D6 D5 D4 HEX
ASCII
CODE
0 0 0
0
0 0 1
1
0 1 0
2
0 1 1
3
1 0 0
4
1 0 1
5
1 1 0
6
1 1 1
7
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
IDCS5087
2006-01-23
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PD243X, PD353X, PD443X
Revision History: 2006-01-23
Previous Version: 2004-12-09
Page
Subjects (major changes since last revision)
Date of change
all
Lead free device
2006-01-23
Attention please!
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved. Due to technical requirements components may contain
dangerous substances. For information on the types in question please contact our Sales Organization.
If printed or downloaded, please find the latest version in the Internet.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing
material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose! Critical
components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.
1)
A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure
of that life-support device or system, or to affect its safety or the effectiveness of that device or system.
2)
Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human
life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.
2006-01-23
13
PD243X, PD353X, PD443X
Post Solder Cleaning Procedures
The least offensive cleaning solution is hot D.l. water (60 °C) for
less than 15 minutes. Addition of mild saponifiers is acceptable.
Do not use commercial dishwasher detergents.
For faster cleaning, solvents may be used. Carefully choose the
solvents as some may chemically attack the package. Maximum
exposure should not exceed two minutes at elevated temperatures. Acceptable solvents are: TF (trichlorotrifluoroethane), TA,
111 Trichloroethane, and unheated acetone. (1)
Optical Considerations
The character heights of these displays allows readability up to
eight feet. Proper filter selection allows the user to build a display
that can be used over this distance.
Filters allow the user to enhance the contrast ratio between a lit
LED and the character background. This will maximize discrimination of different characters as perceived by the display user. The
only limitation is cost. So first consider the ambient lighting environment to maximize the cost benefit ratio for using filters.
Incandescent (with almost no green) or fluorescent (with almost no
red) lights do not have the flat spectral response of sunlight. Plastic band-pass filters are inexpensive and effective in optimizing
contrast ratios. The PD2435/3535/4435 is high efficiency red display and should be matched with a long wavelength pass filter in
the 570 nm to 590 nm range. The PD2436/3536/4436 is a standard red display and should be matched with a long wavelength
pass filter in the 600 nm to 620 nm range. The PD2437/3537/4437
should be matched with a yellow-green band-pass filter that peaks
at 565 nm. For displays of multiple colors, neutral density grey filters offer the best compromise.
Additional contrast enhancement can be gained through shading
the displays. Plastic band-pass filters with built-in louvers offer the
“next step up” in contrast improvement. Plastic filters can be further improved with anti-reflective coatings to reduce glare. The
trade-off is “fuzzy” characters. Mounting the filters close to the display reduces this effect. Care should be taken not to overheat the
plastic filters by allowing for proper air flow.
Note:
1)
Acceptable commercial solvents are: Basic TF Arklone P.
Genesolv D, Genesolv DA, BlacoTron TF and Blaco-Tron TA.
Do not use solvents containing alcohol, methanol, methylene chloride, ethanol, TP35, TCM, TMC, TMS+, TE, and TES. Since many
commercial mixtures exist, you should contact your preferred solvent vendor for chemical composition information. Some major solvent manufacturers are: Allied Chemical Corporation, Specialty
Chemical Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL;
Dow Chemical, Midland, Ml; E.l. DuPont de Nemours & Co., Wilmington, DE.
For further information refer to Appnotes 18 and 19.
An alternative to soldering and cleaning the display modules is to
use sockets. Naturally, 20 pin DIP sockets 15.24 mm (0.600")
wide with 2.54 mm (0.100") centers work well for single displays.
Multiple display assemblies are best handled by longer SIP sockets or DIP sockets when available for uniform package alignment.
Socket manufacturers include: Aries Electronics, Inc., Frenchtown, NJ; Garry Manufacturing, New Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec Electronic Hardware,
New Albany, IN.
Optimal filter enhancements for any condition can be gained
through the use of circular polarized, anti-reflective, band-pass filters. The circular polarizing further enhances contrast by reducing
the light that travels through the filter and reflects back off the display to less than 1%. Proper intensity selection of the displays will
allow 10,000 foot candle sunlight viewability.
Several filter manufacturers supply quality filter materials. Some of
them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite, Wilmington, DE; 3M Company, Visual Products Division, St.
Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,
MA; Marks Polarized Corporation, Deer Park, NY; Hoya Optics,
Inc., Fremont, CA.
One last note on mounting filters: recessing display and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several Bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic
Corp., Burlingame, CA; Photo Chemical Products of California,
Santa Monica, CA; I.E.E.Atlas, Van Nuys, CA.
See Appnote 23.
For further information refer to Appnote 22.
Published by
OSRAM Opto Semiconductors GmbH
Wernerwerkstrasse 2, D-93049 Regensburg
www.osram-os.com
© All Rights Reserved.
2006-01-23
14
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