LMS7002M
FPRF MIMO Transceiver IC
With Integrated Microcontroller
•
SUMMARY FEATURES
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•
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Field Programmable Radio Frequency (FPRF) chip
Dual transceiver ideal for MIMO
User programmable on the fly
Continuous coverage of the 100 kHz - 3.8 GHz RF frequency
range
Digital interface to baseband with on chip integrated 12 bit
D/A and A/D converters
Programmable RF modulation bandwidth up to
160 MHz using analog interface
Programmable RF modulation bandwidth up to
96 MHz using digital interface
Supports both TDD and full duplex FDD
LimeLight™ digital IQ interface – JEDEC JESD207 TDD and
FDD compliant
Transceiver Signal Processor block employs advanced
techniques for enhanced performance
Single chip supports 2x2 MIMO. Multiple chips can be used
to implement higher order MIMO
On-chip RF calibration circuitry
Fully differential baseband signals, analog IQ
Few external components
Low voltage operation, 1.25, 1.4 and 1.8V. Integrated LDOs
to run on a single 1.8V supply voltage
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On chip integrated microcontroller for simplified calibration,
tuning and control
Integrated clock PLL for flexible clock generation and
distribution
User definable analog and digital filters for customised
filtering
RF and base band Received Signal Strength Indicator (RSSI)
On chip integrated temperature sensor
261 pin aQFN 11.5x11.5 mm package
Power down option
Serial port interface
Low power consumption, typical 880mW in full 2x2 MIMO
mode (550mW in SISO mode) using external LDOs
Multiple bypass modes for greater flexibility
APPLICATIONS
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Broad band wireless communications
GSM, CDMA2000, TD-SCDMA, WCDMA/HSPA, LTE
IEEE® xxx.xxx radios
WiFi operating in the Whitespace frequencies
Software Defined Radio (SDR)
Cognitive Radio
Unmanned Aerial Vehicle (UAV)
Other Whitespace applications
Figure 1: Functional block diagram
Document version: 3.1r00
LMS7002M – FPRF MIMO Transceiver IC
The LMS7002M provides an RF loop back option which enables the TX
RF signal to be fed back into the baseband for calibration and test
purposes. The RF loop back signal is amplified by the loopback
amplifier in order to increase the dynamic range of the loop.
GENERAL DESCRIPTION
LMS7002M is a fully integrated, multi-band, multi-standard RF
transceiver that is highly programmable. It combines Low Noise
Amplifiers (RXLNA), TX Power Amplifier Drivers (TXPAD)
receiver/transmitter (RX/TX) mixers, RX/TX filters, synthesizers, RX
gain control, TX power control, the analog-to-digital and digital-toanalog convertors (ADC/DACs) and has been designed to require very
few external components.
The top level architecture of LMS7002M transceiver is shown in Figure
1. The chip contains two transmit and two receive chains for achieving a
Multiple In Multiple Out (MIMO) platform. Both transmitters share one
PLL and both receivers share another. Transmit and receive chains are
all implemented as zero Intermediate Frequency (zero IF or ZIF)
architectures providing up to 160MHz RF modulation bandwidths
(equivalent to 80MHz baseband IQ bandwidth). For the purpose of
simplifying this document, the explanation for the functionality and
performance of the chip is based on one transmit and one receive
circuitry, given that the other two work in exact the same manner.
On the transmit side, In-phase and Quadrature IQ DAC data samples,
from the base band processor, are provided to the LMS7002M via the
LimeLight™ digital IQ interface. LimeLight™ implements the JESD207
standard IQ interface protocol as well as de facto IQ multiplexed
standard. JESD207 is Double Data Rate (DDR) by definition. In IQ
multiplexed mode LimeLight™ also supports Single Data Rate (SDR).
The IQ samples are then pre-processed by the digital Transceiver
Signal Processor (TSP) for minimum analog / RF distortion and applied
to the on chip transmit DACs. The DACs generate analog IQ signals
which are provided for further processing to the analog/RF section.
Transmit low pass filters (TXLPF) remove the images generated by
zero hold effect of the DACs, as well as the DAC out-of-band noise. The
analog IQ signals are then mixed with the transmit PLL (TXPLL) output
to produce a modulated RF signal. This RF signal is then amplified by
one of two separate / selectable power amplifier drivers and two opendrain differential outputs are provided as RF output for each MIMO
path.
There are two additional loop back options implemented, one is an
analog base band (BB) loop back and another is a digital loop back
(DLB) as shown in Figure 1. The analog loop back is intended for
testing while the DLB can be used to verify the LMS7002M connectivity
to base band, FPGA, DSP or any other digital circuitry.
On the receive side, three separate inputs are provided each with a
dedicated LNA optimised for narrow or wide band operation. Each port
RF signal is first amplified by a programmable low noise amplifier
(RXLNA). The RF signal is then mixed with the receive PLL (RXPLL)
output to directly down convert to baseband. AGC steps can be
implemented by a BB trans-impedance amplifier (RXTIA) prior to the
programmable bandwidth low pass channel select / anti alias filters
(RXLPF). The received IQ signal is further amplified by a programmable
gain amplifier RXPGA. DC offset is applied at the input of RXTIA to
prevent saturation and to preserve the receive ADC’s dynamic range.
The resulting analog receive IQ signals are converted into the digital
domain with on-chip receive ADCs. Following the ADCs, the signal
conditioning is performed by the digital Transceiver Signal Processor
(TSP) and the resulting signals are then provided to the BB via the
LimeLight™ digital IQ interface.
The analog receive signals can also be provided off chip at RXOUTI
and RXOUTQ pins by closing the RXOUT switch. In this case it is
possible to power down the on chip ADCs/TSP and use external parts
which can be very useful for more resource demanding applications or
where higher signal resolution is required. A similar option is also
available on the TX side where the analog signal can be processed by
external components. The on chip DACs/TSP can be powered down
and analog inputs can be provided at TXINI and TXINQ pins.
There is on chip integrated temperature sensor which base band
modem can read via the SPI and trigger re-calibration of the chip if
significant chip/ambient temperature change is observed.
Parameter
Min.
Typ.
Max.
Unit
Operating Temperature Range
-40
25
85
°C
Storage Temperature Range
-65
30
0.1
25
125
3800
3800
48
96
160
24.8
°C
Operating Frequency Range
RF Modulation Bandwidth
Frequency Resolution
MHz
MHz
Hz
Condition/Comment
Extended by TSP NCOs
Through digital interface (MIMO)
Through digital interface (SISO)
Through analog interface
Using 52 MHz PLL reference clock
Analog Supply Voltage, High (VDDAH)
Analog Supply Voltage, Medium
(VDDAM)
Analog Supply Voltage, Low (VDDAL)
1.71
1.8
1.89
V
1.33
1.4
1.47
V
1.2
1.25
1.3
V
Used for TXPAD
Generated using integrated low-dropout regulators
(LDOs)
Generated using integrated LDOs
Digital Core Supply Voltage
1.1
1.2
1.3
V
Generated using integrated LDOs
Digital Peripheral (IO) Supply Voltage
1.7
2.5
3.6
V
TX Supply Current
350
mA
RX Supply Current
420
mA
At -7 dBm output power, 2x2 MIMO, including the DACs
and TSP
For 2x2 MIMO, including the ADCs and TSP
dBm
Continuous Wave
Maximum RF Output Power
PLL Reference Clock
0
10
52
MHz
Reference and Other Spurs Level
-100
dBm
Measured at TX RF output or RX RF input
IQ Imbalance Image
Interpolation/Decimation digital filters
stop band suppression
-70
dBc
After calibration
108
dB
Table 1: General specifications
LMS7002M
2
LMS7002M – FPRF MIMO Transceiver IC
Parameter
RF channel frequency range
Min.
30
0.1
Typ.
Max.
3800
3800
Unit
Condition/Comment
MHz
400
Ohms
Extended by TSP NCOs
Differential, programmable
40
Ohms
Differential, for maximum OIP3
Transmit Differential I and Q Input
Current
625
uA
Differential
Common mode
Transmit Gain Control Range
70
dB
TXTSP and TXPAD combined
Transmit Gain Control Step
1
dB
TX Local Oscillator (LO) Leakage
-60
Transmit Analog Input Impedance
Transmit Load Impedance at the Output
Pins
dBc
Calibrated
RXLNAL Frequency Range
0.1
2000
MHz
Narrow band tunable, set by external matching circuit
RXLNAH Frequency Range
30
3800
MHz
Narrow band tunable, set by external matching circuit
RXLNAW Frequency Range
30
3800
MHz
Broad band tunable, set by external matching circuit
at 0.95GHz
at 2GHz
at 3.8GHz
Total receiver gain ~50 dB or more, Noise Figure
fTXNCO.
The same spectrum of Figure 51.b drives digital RSSI block. In fact
RSSI measures the level of two tone signal (3) and (3a) where (3a) is
due to RX IQ imbalance. However tones are correlated. In other words,
minimizing (3), tone (3a) will go down for the same amount. RSSI
output will be composite power level of those two tones and is valid
measure. If we minimize RSSI output we are minimizing TX IQ
imbalance disregarding the presence of two (correlated) tones.
Algorithm is then simple. First alter on chip analog IQ phase correction
parameters if available to minimize RSSI output. After that alter TX Gain
correction and TX Phase correction parameters of TXTSP digital block
to further minimise RSSI output. Resulting spectrum is shown in Figure
51.c.
The test setup described above uses minimum filtering to clearly show
unwanted tones we need to cancel. The spectrum of Figure 50 shows
RX output while LMS7002M works in RF loopback mode. Tones and
the reasons for their existence are as below.
LMS7002M
fTXLO - fRXLO
18
LMS7002M – FPRF MIMO Transceiver IC
(2)
Decimation filter
TDD/FDD MODE ENHANCMENT OPTION
(2a)
In both TDD and FDD mode the LMS7002M is capable of running from
a single PLL, allowing one on chip PLL to be powered down. In TDD
mode, a single PLL output drives both TX and RX mixers. In FDD
mode, a single PLL drives both mixers as well, while UL/DL frequency
separation is implemented in the digital domain using the NCO and
complex mixer parts of the TSP block. The maximum frequency shift
range which can be achieved in the digital domain is as below:
(3)
(1)
(3a)
(4)
(1a)
(a)
DC
fTXLO fPLL 0.6 * fDAC / 2
fRXLO fPLL 0.6 * fADC / 2
(2)
Decimation filter
,
where fTXLO and fRXLO are effective TX and RX LO frequencies, fPLL is the
shared PLL output frequency while fDAC and fADC are data converter
sampling rates. Note that the Nyquist frequency of the NCOs is scaled
by a factor of 0.6 to make space for TXLPF and RXLPF to operate.
(2a)
(3)
(1)
(3a)
Running the LMS7002M in single PLL mode has the following
advantages:
(4)
(1a)
(b)
•
DC
•
(2)
Decimation filter
•
(2a)
•
(3)
(1)
Current consumption is significantly reduced since one PLL is
powered down.
Fast TXRX switching time in TDD mode is achievable
since the PLL does not need to relock.
There is no TXVCORXVCO polling issue since a single
PLL is used.
Using the digital domain for LO frequency shifts enables
implementation of very fast frequency hopping systems.
(3a)
(4)
IMPROVING FRACTIONAL-N CLOSE TO INTEGER
RF SYNTHESISER SPURS PERFORMANCE
DC
Due to PFD/CHP ‘dead zone’ i.e. nonlinearity around zero, fractional-N
synthesisers are prone to generate unwanted spurs when set close to
integer frequency. These spurs are unfortunately in the loop pass band
and cannot be filtered. One of the solutions is to set constant charge
pump current offset to shift PFD/CHP away from zero i.e. operating
them into more linear region. However, this CHP offset value depends
on how far PLL output frequency is away from the nearest integer
frequency and has to be tuned accordingly.
(1a)
(c)
Figure 51: TX IQ imbalance calibration. Spectral tones:
(a) before digital filtering
(b) after digital filtering
(c) after calibration
Digital blocks can help this case. Set charge pump offset current to
some middle value and keep it constant disregarding how far close to
integer frequency is away from integer frequency. Offset PLL wanted
frequency away enough from integer frequency in order not to have
close to integer spurs issue. This introduces PLL output frequency error
which can be corrected by corresponding NCO available in the digital
TSP block.
LMS7002M
19
LMS7002M – FPRF MIMO Transceiver IC
PACKAGE OUTLINE AND PIN DESCRIPTION
0.666 mm
1.332 mm
11.500 mm
4
260
B2
B
C
1
C1
258
C3
11
G1
1.332 mm
16
J1
23
N1
9
J5
14
K4
11.500 mm
240
F12
234
F14
AC
204
F24
198
D28
199
E27
200
F26
194
D30
196
F28
18
M6
178
M30
171
R29
71
AK6
70
AL5
69
AM4
77
AJ9
76
AK8
75
AL7
74
AM6
73
AN5
4
5
81
AL9
79
AN7
6
82
AK10
80
AM8
90
AJ13
88
AK12
86
AL11
85
AM10
84
AN9
78
AP6
AP
83
AJ11
94
AJ15
98
AJ19
93
AK14
100
AK20
92
AL13
97
AL19
91
AM12
89
AN11
102
AJ21
96
AM18
8
105
AK22
101
AL21
99
AM20
95
AN17
118
AJ27
113
AK26
106
AL23
103
AM22
119
AK28
110
AM26
108
AN25
111
AN27
109
AP26
AA
Y
152
AB34
AD
AE
143
AF34
AH
134
AJ33
129
AK32
AJ
133
AK34
AK
127
AM34
AM
128
AL33
AL
AN
123
AP32
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
6.989 mm
10.323 mm
10.989 mm
Figure 52: 261L aQFN package (top view)
20
AF
AG
122
AN31
117
AP30
AB
AC
135
AH32
125
AL31
116
AN29
154
AA33
139
AG33
121
AM30
V
W
144
AE33
130
AJ31
120
AL29
162
V34
159
W33
140
AF32
126
AK30
115
AM28
T
149
AC33
136
AG31
124
AJ29
114
AL27
107
AM24
104
AN23
87
AP10
7
112
AJ25
U
146
AD32
137
AF30
72
AJ7
163
U33
150
AB32
131
AH30
64
AJ5
R
156
Y32
141
AE31
P
168
R33
161
V32
142
AD30
132
AG29
N
170
P34
166
T32
147
AC31
138
AE29
L
174
N33
153
AA31
K
M
172
P32
148
AB30
59
AF6
65
AK4
3
177
L33
158
W31
145
AC29
J
179
K34
176
M32
155
Y30
61
AH4
68
AN3
2
181
K32
160
V30
151
AA29
H
182
J33
164
U31
157
W29
53
AD6
F
G
169
R31
165
U29
60
AG5
66
AL3
AN
E
185
H32
167
T30
261L aQFN
11.5 x11.5 mm
D
188
F32
180
L31
54
AE5
62
AJ3
67
AM2
192
D32
187
G31
183
K30
46
AB6
55
AF4
63
AK2
C
191
E31
190
F30
40
Y6
50
AD4
57
AH2
58
AJ1
AL
LMS7002M
193
C31
195
E29
48
AC5
56
AG3
AG
1
208
F22
202
D26
203
E25
42
AA5
51
AE3
52
AF2
AM
214
F20
206
D24
207
E23
197
C29
10
K6
35
V6
44
AB4
47
AD2
49
AE1
AK
220
F18
210
D22
212
E21
201
C27
184
J31
28
T6
38
Y4
45
AC3
AH
228
F16
218
E19
205
C25
186
H30
30
U5
41
AA3
43
AB2
AF
216
D20
225
E17
B
209
C23
26
R5
34
V4
37
Y2
39
AA1
AD
221
D18
213
C21
189
G29
36
W3
AB
227
D16
230
E15
219
C19
A
211
B22
175
N31
31
U3
33
V2
Y
AJ
248
F10
232
D14
237
E13
224
C17
217
B20
173
P30
29
T4
32
U1
W
AE
253
F8
238
D12
243
E11
229
C15
215
A21
222
B18
24
P4
T
AA
244
D10
249
E9
235
C13
226
B16
15
L5
20
M4
27
R3
V
239
C11
223
A17
231
B14
22
N3
R
U
245
C9
236
B12
6
H6
25
P2
P
0.666 mm
13
J3
21
M2
M
N
5
G5
233
A13
241
B10
250
D8
259
F6
8
G3
19
L3
L
251
C7
254
D6
4
F4
17
K2
K
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
242
A9
257
E5
12
H2
H
8
246
B8
261
D4
7
F2
F
7
247
A7
255
C5
3
E3
E
J
6
256
B4
2
D2
D
G
5
252
A5
AP
10.989 mm
3
6.989 mm
2
10.323 mm
1
A
LMS7002M – FPRF MIMO Transceiver IC
Pin No
Pin ID
1
2
3
4
5
6
7
8
9
10
11
12
13
C1
D2
E3
F4
G5
H6
F2
G3
J5
K6
G1
H2
J3
UNUSED
UNUSED
UNUSED
UNUSED
VDD12_TXBUF
VDD18_TXBUF
UNUSED
VDD18_VCO_SXT
VDD12O_VCO_SXT
VDD12_VCO_SXT
UNUSED
GND_VCO_SXT
VDD_CP_SXT
analog supply
analog supply
analog supply
analog supply
analog supply
analog gnd
analog supply
1.25V supply – TX XOSC buffer
1.8V supply – TX XOSC buffer
1.8V supply – TX SX VCO
1.25V supply – TX SX VCO
1.25V supply – TX SX VCO
GND – TX SX VCO
1.25V supply – TX SX Charge pump
14
15
16
17
18
19
20
21
22
23
K4
L5
J1
K2
M6
L3
M4
M2
N3
N1
GND_CP_SXT
VDD_DIV_SXT
UNUSED
VDDO_DIV_SXT
UNUSED
GND_DIV_SXT
DVDD_SXT
UNUSED
DGND_SXT
VDD18_LDO_TX
analog gnd
analog supply
analog supply
analog gnd
digital supply
digital gnd
analog supply
GND – TX SX Charge pump
1.25V supply – TX SX frequency divider
1.25V supply – TX SX frequency divider
GND – TX SX frequency divider
1.25V supply – digital supply for TX SX
GND – digital supply for TX SX
1.8V supply – TX LDO
24
25
26
27
28
29
30
P4
P2
R5
R3
T6
T4
U5
VDD_TBB
tbbqn_pad_1
tbbin_pad_1
tbbqp_pad_1
tbbin_pad_2
tbbip_pad_1
adcin_in_1
analog supply
in
in
in
in
in
in
1.25V supply – TX baseband
TX change input pad to externally drive the TX BB Channel 1
TX change input pad to externally drive the TX BB Channel 1
TX change input pad to externally drive the TX BB Channel 1
TX change input pad to externally drive the TX BB Channel 2
TX change input pad to externally drive the TX BB Channel 1
ADC input pads – To use external filtering Channel 1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
U3
U1
V2
V4
V6
W3
Y2
Y4
AA1
Y6
AA3
AA5
AB2
AB4
AC3
AB6
AD2
tbbqp_pad_2
tbbqn_pad_2
tbbip_pad_2
adcin_ip_1
adcin_in_2
adcin_qn_1
adcin_qp_1
adcin_qn_2
adcin_ip_2
rbbip_pad_1
adcin_qp_2
rbbqn_pad_1
rbbin_pad_1
rbbqp_pad_1
rbbin_pad_2
rbbqn_pad_2
rbbip_pad_2
in
in
in
in
in
in
in
in
in
out
TX change input pad to externally drive the TX BB Channel 2
TX change input pad to externally drive the TX BB Channel 2
TX change input pad to externally drive the TX BB Channel 2
ADC input pads – To use external filtering Channel 1
ADC input pads – To use external filtering Channel 2
ADC 21nput pads – To use external filtering Channel 1
ADC input pads – To use external filtering Channel 1
ADC input pads – To use external filtering Channel 2
ADC input pads – To use external filtering Channel 2
RX BB output – To use external filtering Channel 1
ADC input pads – To use external filtering Channel 2
RX BB output – To use external filtering Channel 1
RX BB output – To use external filtering Channel 1
RX BB output – To use external filtering Channel 1
RX BB output – To use external filtering Channel 2
RX BB output – To use external filtering Channel 2
RX BB output – To use external filtering Channel 2
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AC5
AE1
AD4
AE3
AF2
AD6
AE5
AF4
AG3
AH2
AJ1
AF6
AG5
AH4
AJ3
AK2
AJ5
rbbqp_pad_2
UNUSED
VDD14_RBB
VDD18_TIA_RFE
VDD14_TIA_RFE
VDD12_TIA_RFE
UNUSED
VDD18_LDO_RX
UNUSED
UNUSED
UNUSED
VDD14_LNA_RFE
VDD12_LNA_RFE
UNUSED
UNUSED
UNUSED
UNUSED
out
analog supply
analog supply
analog supply
analog supply
analog supply
analog supply
analog supply
-
RX BB output – To use external filtering Channel 2
1.4V supply- RX baseband
1.8V supply- RXFE TIA
1.4V supply- RXFE TIA
1.25V supply- RXFE TIA
1.8V supply- RX LDO
1.4V supply- RXFE LNA
1.25V supply- RXFE LNA
-
65
66
AK4
AL3
UNUSED
UNUSED
-
-
67
68
69
AM2
AN3
AM4
UNUSED
rfgp_w_RFE_2
rfgn_w_RFE_2
in
in
LNA input gate Wideband LNA – Gate : Channel 2
LNA input gate Wideband LNA – Gate : Channel 2
Pin Name
Type
in
out
out
out
out
out
out
Description
Table 12 Pin descriptions
LMS7002M
21
Notes
LMS7002M – FPRF MIMO Transceiver IC
Pin No
Pin ID
70
71
72
73
74
75
76
77
78
79
80
81
82
AL5
AK6
AJ7
AN5
AM6
AL7
AK8
AJ9
AP6
AN7
AM8
AL9
AK10
UNUSED
UNUSED
rfsn_l_RFE_2
rfgp_l_RFE_2
UNUSED
UNUSED
UNUSED
rfsp_l_RFE_2
rfgn_l_RFE_2
rfgp_h_RFE_2
rfgn_h_RFE_2
UNUSED
UNUSED
in/out
in
in/out
in
in
in
-
LNA Lowband LNA – Source: Channel 2
LNA input gate Lowband LNA – Gate : Channel 2
LNA Lowband LNA – Source : Channel 2
LNA input gate Lowband LNA – Gate : Channel 2
LNA input gate Highband LNA – Gate : Channel 2
LNA input gate Highband LNA – Gate : Channel 2
-
83
84
85
86
87
88
89
90
91
92
AJ11
AN9
AM10
AL11
AP10
AK12
AN11
AJ13
AM12
AL13
UNUSED
rfgp_w_RFE_1
UNUSED
UNUSED
rfgn_w_RFE_1
rfsn_l_RFE_1
rfgp_l_RFE_1
UNUSED
rfgn_l_RFE_1
rfsp_l_RFE_1
in
in
in/out
in
in
in/out
LNA input gate Wideband LNA – Gate : Channel 1
LNA input gate Wideband LNA – Gate : Channel 1
LNA Lowband LNA – Source : Channel 1
LNA input gate Lowband LNA – Gate : Channel 1
LNA input gate Lowband LNA – Gate : Channel 1
LNA Lowband LNA – Source : Channel 1
93
94
95
96
97
98
99
AK14
AJ15
AN17
AM18
AL19
AJ19
AM20
rfgp_h_RFE_1
rfgn_h_RFE_1
VDD_MXLOBUF_RFE
VDD18_SXR
VDD_CP_SXR
GND_CP_SXR
VDD_DIV_SXR
in
in
analog supply
analog supply
analog supply
analog gnd
analog supply
LNA input gate Highband LNA – Gate : Channel 1
LNA input gate Highband LNA – Gate : Channel 1
1.25V supply: RX LO buffers
1.8V supply: RX SX
1.25V supply: RX SX Charge pump
GND: RX SX Charge pump
1.25V supply: RX SX frequency divider
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
AK20
AL21
AJ21
AM22
AN23
AK22
AL23
AM24
AN25
AP26
AM26
AN27
AJ25
AK26
AL27
AM28
AN29
GND_DIV_SXR
DVDD_SXR
UNUSED
DGND_SXR
VDD12_VCO_SXR
VDD18_VCO_SXR
GND_VCO_SXR
xoscin_rx
GND_RXBUF
VDD12_RXBUF
VDD18_RXBUF
UNUSED
VDD_AFE
UNUSED
UNUSED
UNUSED
UNUSED
analog gnd
digital supply
digital gnd
analog supply
analog supply
analog gnd
in
analog gnd
analog supply
analog supply
analog supply
-
GND: RX SX frequency divider
1.25V digital supply: RX SX f
GND: RX SX
1.25V supply: RX SX
1.8V supply: RX SX
GND: RX SX VCO
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
AP30
AJ27
AK28
AL29
AM30
AN31
AP32
AJ29
AL31
AK30
AM34
AL33
AK32
AJ31
AH30
AG29
AK34
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
-
-
DIGPRVDD2
DIGPRGND1
UNUSED
DVDD
pad gnd
-
Digital Pad Ring power supply for post-driver
Digital Pad Ring ground for pre-driver
-
134
135
AJ33
AH32
UNUSED
UNUSED
-
-
136
137
138
AG31
AF30
AE29
DIQ1_D0
DIQ1_D1
IO_cmos1225
IO_cmos1225
DIQ bus, bit 0. LML Port 1
DIQ bus, bit 1. LML Port 1
DIGPRVDD1
DVDD
Digital Pad Ring power supply for pre-driver
Pin Name
Type
Description
GND – RX XOSC buffer
1.25V supply – RX XOSC buffer
1.8V supply – RX XOSC buffer
1.25V supply – ADC/DAC
-
Table 13: Pin descriptions (continued)
LMS7002M
22
Notes
LMS7002M – FPRF MIMO Transceiver IC
Pin No
Pin ID
139
140
141
142
143
144
145
146
147
148
149
150
151
AG33
AF32
AE31
AD30
AF34
AE33
AC29
AD32
AC31
AB30
AC33
AB32
AA29
UNUSED
-
-
DIGPRGND2
DIQ1_D3
DIQ1_D4
DIQ1_D2
DIQ1_D6
DIQ1_D5
pad gnd
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
Digital Pad Ring ground for post-driver
DIQ bus, bit 3. LML Port 1
DIQ bus, bit 4. LML Port 1
DIQ bus, bit 2. LML Port 1
DIQ bus, bit 6. LML Port 1
DIQ bus, bit 5. LML Port 1
DIQ1_D7
DIQ1_D8
DIQ1_D10
DIQ1_D9
DIQ1_D11
DIGPRVDD1
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
DVDD
DIQ bus, bit 7. LML Port 1
DIQ bus, bit 8. LML Port 1
DIQ bus, bit 10. LML Port 1
DIQ bus, bit 9. LML Port 1
DIQ bus, bit 11. LML Port 1
Digital Pad Ring power supply for pre-driver
152
153
154
155
156
157
158
159
160
161
AB34
AA31
AA33
Y30
Y32
W29
W31
W33
V30
V32
162
V34
MCLK1
DIGPRGND1
FCLK1
DIGPRGND2
ENABLE_IQSEL1
DIGPRGND1
DIGPRPOC
DIGPRVDD2
LOGIC_RESET
TXNRX1
RXEN
out_cmos1225
DGND
in_cmos1225
pad gnd
IO_cmos1225
pad gnd
POC
DVDD
analog supply/gnd
in_cmos1225
in_cmos1225
Clock from RFIC to BBIC in JESD207 mode. LML Port 1
Digital Pad Ring ground for pre-driver
Clock from BBIC to RFIC in JESD207 mode. LML Port 1
Digital Pad Ring ground for post-driver
IQ flag in RXTXIQ mode; enable flag in JESD207 mode. LML Port 1
Digital Pad Ring ground for pre-driver
POC circuit
Digital Pad Ring power supply for post-driver
Not used
IQ data protocol control in JESD207 mode. LML Port 1
RX hard power off
163
U33
CORE_LDO_EN
analog supply/gnd
External enable control signal for the internal LDO’s.
164
165
166
U31
U29
T32
TXNRX2
TXEN
DIGPRVDD2, DIGPRPOC
in_cmos1225
in_cmos1225
DVDD
IQ data protocol control in JESD207 mode. LML Port 2
TX hard power off
Digital Pad Ring power supply for post-driver and POC
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
T30
R33
R31
P34
R29
P32
P30
N33
N31
M32
L33
M30
K34
L31
K32
J33
K30
DIGPRGND1, DIGPRGND2
ENABLE_ IQSEL2
DIGPRVDD1
MCLK2
FCLK2
DIQ2_D11
DIQ2_D10
DIQ2_D9
DIQ2_D8
DIQ2_D7
DIGPRVDD1
pad gnd
IO_cmos1225
DVDD
out_cmos1225
in_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
DVDD
Digital Pad Ring ground for pre-driver and post-driver
IQ flag in RXTXIQ mode; enable flag in JESD207 mode. LML Port 2
Digital Pad Ring power supply for pre-driver
Clock from RFIC to BBIC in JESD207 mode. LML Port 2
Clock from BBIC to RFIC in JESD207 mode. LML Port 2
DIQ bus, bit 11. LML Port 2
DIQ bus, bit 10. LML Port 2
DIQ bus, bit 9. LML Port 2
DIQ bus, bit 8. LML Port 2
DIQ bus, bit 7. LML Port 2
Digital Pad Ring power supply for pre-driver
DIQ2_D6
DIQ2_D5
DIQ2_D4
DIQ2_D3
DIGPRGND1
IO_cmos1225
IO_cmos1225
IO_cmos1225
IO_cmos1225
DGND
DIQ bus, bit 6. LML Port 2
DIQ bus, bit 5. LML Port 2
DIQ bus, bit 4. LML Port 2
DIQ bus, bit 3. LML Port 2
Digital Pad Ring ground for pre-driver
DIQ2_D2
IO_cmos1225
DIQ bus, bit 2. LML Port 2
184
185
186
187
188
189
J31
H32
H30
G31
F32
G29
DIQ2_D1
DIGPRVDD2
IO_cmos1225
DVDD
DIQ bus, bit 1. LML Port 2
Digital Pad Ring supply for post-driver
DIQ2_D0
DIGPRGND2
UNUSED
UNUSED
IO_cmos1225
pad gnd
-
190
F30
SDIO
IO_cmos1225
191
192
193
194
195
196
197
198
199
200
E31
D32
C31
D30
E29
F28
C29
D28
E27
F26
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
SDO
SCLK
SEN
RESET
UNUSED
out_cmos1225
in_cmos1225
in_cmos1225
in_cmos1225
-
DIQ bus, bit 0. LML Port 2
Digital Pad Ring ground for post-driver
Serial port data input-output in 3 wire mode, Serial port data input in
4 wire mode, CMOS
Serial port data output, CMOS
Serial port clock, positive edge sensitive, CMOS
Serial port enable, active low, CMOS
Hardware reset, active low, CMOS level
-
201
202
203
204
C27
D26
E25
F24
SCL
SDA
GND_SPI_BUF
VDD_SPI_BUF
IO_cmos1225
IO_cmos1225
digital gnd
digital supply
uControler
uControler
GND – SPI buffer
1.25V supply – SPI buffer
Pin Name
Type
Description
Table 14: Pin descriptions (continued)
LMS7002M
23
Notes
Should be fixed to analog supply if
internal LDO’s are used.
Should be fixed to analog gnd if
internal LDO’s are NOT used.
LMS7002M – FPRF MIMO Transceiver IC
Pin No
Pin ID
205
206
207
208
209
210
211
212
213
214
215
216
217
C25
D24
E23
F22
C23
D22
B22
E21
C21
F20
A21
D20
B20
VDD12_DIG
VDD18_DIG
UNUSED
tstdo
GND_DIG
tstdo
tstao
VDD18_VCO_CGEN
VDD14_VCO_CGEN
VDD_CP_CGEN
UNUSED
GND_DIV_CGEN
GND_CP_CGEN
digital supply
digital supply
out_cmos1225
digital gnd
out_cmos1225
out_cmos1225
analog supply
analog supply
analog supply
analog gnd
analog gnd
output 1.2V supply for digital LDO
1.8V supply for digital LDO
digital output test pin
GND for the digital LDO
digital output test pin
analog test pin
1.8V supply – VCO CLKGEN
1.4V supply – VCO CLKGEN
1.25V supply – Charge Pump – CLKGEN
GND –frequency divider – CLKGEN
GND –Charge Pump – CLKGEN
218
219
220
221
222
223
224
225
226
227
E19
C19
F18
D18
B18
A17
C17
E17
B16
D16
VDD_DIV_CGEN
UNUSED
vr_rext
UNUSED
DGND_CGEN
DVDD_CGEN
UNUSED
VDD18_BIAS
VDD_TPAD_TRF
VDD18_TRF
analog supply
in
digital gnd
digital supply
analog supply
analog supply
analog supply
1.25V supply – frequency divider – CLKGEN
external 10 kOhm accurate reference resistor
GND – CLKGEN
1.25V supply- Digital supply for CLK GEN
1.8V supply – Bias
1.25V supply – TX PAD
1.8V supply – TX RF
228
229
230
231
232
233
234
F16
C15
E15
B14
D14
A13
F14
UNUSED
UNUSED
UNUSED
pa2on_2
UNUSED
pa2op_2
UNUSED
out
out
-
PA driver output RF pad PAD2, Channel 2
PA driver output RF pad PAD2, Channel 2
-
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
C13
B12
E13
D12
C11
F12
B10
A9
E11
D10
C9
B8
A7
F10
E9
D8
C7
UNUSED
pa1op_2
UNUSED
UNUSED
pa1on_2
UNUSED
pa2on_1
pa2op_1
UNUSED
UNUSED
UNUSED
pa1op_1
pa1on_1
UNUSED
UNUSED
UNUSED
out
out
out
out
out
out
-
PA driver output RF pad PAD1, Channel 2
PA driver output RF pad PAD1, Channel 2
PA driver output RF pad PAD2, Channel 1
PA driver output RF pad PAD2, Channel 1
PA driver output RF pad PAD1, Channel 1
PA driver output RF pad PAD1, Channel 1
-
252
253
254
255
256
257
258
259
260
261
A5
F8
D6
C5
B4
E5
C3
F6
B2
D4
GND_TLOBUF_TRF
UNUSED
VDD_TLOBUF_TRF
VDDO_TLOBUF_TRF
UNUSED
UNUSED
xoscin_tx
UNUSED
GND_TXBUF
UNUSED
UNUSED
analog gnd
analog supply
analog supply
in
analog gnd
-
Ground for TX LO buffers
1.25V supply – TX LO BUFFER
Pin Name
Type
Description
TX XOSC buffer input
GND supply – TX XOSC buffer
-
Table 15: Pin descriptions (continued)
LMS7002M
24
Notes
LMS7002M – FPRF MIMO Transceiver IC
TYPICAL APPLICATION
RF Section Example
A typical application circuit of the LMS7002M is given in Figure 53. Note that only the RF part of a single MIMO TRX chain is shown. More details
can be found in the LMS7002M evaluation board schematics.
Figure 53: Typical RF application circuit
LMS7002M
25
LMS7002M – FPRF MIMO Transceiver IC
Digital Interface Configuration Example
Figure 54 shows one useful example of clock generation and distribution as well as interfacing LMS7002M to digital BB modem. Note that interface
control signals such as ENABLE, TXNRX, IQSEL are not shown for clarity. As can be seen, CLKPLL block generates 491.52MHz (integer multiple
of 61.44MHz) clock. CLKPLL output is divided by programmable divider (division set to 4 in this example) to construct 122.88MHz clock driving
DACs, TXTSP and TX part of LimeLight™. Similarly, CLKPLL output is divided by fixed division of 4 to construct 122.88MHz clock driving ADCs,
RXTSP and RX part of LimeLight™. Interpolation and decimation are both set to 2. Hence, the configuration provides 245.76MS/s double data rate
(DDR) interface to BB modem. This translates into the overall system performance as below:
•
•
•
•
•
•
TX/RX IF bandwidth: 20MHz
TX/RX RF bandwidth: 40MHz
Digital interpolation image suppression: 60dB
DACs analog image suppression: 72dB
ADCs analog alias suppression: 43dB assuming no off chip filtering
Digital decimation alias suppression: 60dB
122.88MHz
TXFCLK
DDR
TX FIFO/DEMUX
12
122.88MHz
DDR
2 HB1
12
2
61.44MS/s
SDR
TXFCLK
12
TXD[11:0] 245.76MS/s
WRITECLK
245.76MS/s
TXD[11:0]
12
READCLK
TX Interface
TX Interface
HB1
2 HB1
12
2 HB1
61.44MS/s
12
12
12
12
DAC AI
DAC AQ
DAC BI
DAC BQ
To TX Front End
Interpolation
12
122.88MS/s
/2 Automatically
Enabled/Set
TXMCLK
Ignored
TXMCLK
Ignored
122.88MHz
122.88MHz
CLKGEN
/4
491.52MHz
Automatically
RXD[11:0]
RX Interface
BB Side
12
RXD[11:0] 245.76MS/s
12
DDR
RX Interface
61.44MS/s
12
12
12
12
/4 Fixed
HB1 2
HB1 2
HB1 2
HB1 2
Decimation
LMS7002M Side
Figure 54: Digital interface setup
LMS7002M
26
122.88MS/s
12
12
12
12
ADC AI
ADC AQ
ADC BI
ADC BQ
From RX Front End
245.76MS/s
WRITECLK
RXFCLK
Ignored
RX FIFO/MUX
RXFCLK
Ignored
61.44MS/s
SDR
/2 Enabled/Set
122.88MHz
122.88MHz
491.52MHz
READCLK
RXMCLK
Used to sample
RXD[11:0]
RXMCLK 122.88MHz
DDR
CLKPLL
LMS7002M – FPRF MIMO Transceiver IC
ORDERING INFORMATION
Model
LMS7002M
LMS7002M-REEL
LMS7002M-EVB
Temperature Range
-40oC to +85oC
-40oC to +85oC
Package Description
261 pin aQFN
261 pin aQFN
Evaluation board
REVISION HISTORY
The following table shows the revision history of this document:
Date
05/11/2013
02/07/2014
10/09/2014
28/10/2014
06/03/2015
13/04/2015
27/07/2015
Version
2.0.0
2.1.0
2.2.0
2.3.0
2.4.0
2.5.0
2.6.0
06/09/2015
2.7.0
10/09/2015
03/05/2017
2.8.0
3.1.00
Description of Revisions
Major update
Performance parameters corrections based on measurement data
Performance parameters corrections based on measurement data
Updated table 5, 8 and 9
Correction in LimeLight™ interface description
Updated pin description
More details on analog low pass filters added. Amplitude responses updated.
LimeLight™ figure captions corrected.
Clock PLL forward divider equations updated.
Interpolation/Decimation pass band equation generalized.
“INITIALIZATION AND CALIBRATION” section moved and updated.
“IMPROVING FRACTIONAL-N CLOSE TO INTEGER RF PLL SPURS PERFORMANCE” section added.
Digital interface configuration example added.
Few pin names/description corrected.
RF bandwidth through digital interface updated.
In Table 1, RF Modulation Bandwidth provided instead of Baseband Bandwidth.
Some clarifications based on customers feedback added. Text modified based on new features/enhancements
offered by mask=1 silicon.
NOTICE OF DISCLAMER
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Lime Microsystems products. To the
maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Lime Microsystems hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRRANTIES OF
MERCHANTABILITY, NON-INFRIGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Lime Microsystems shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to,
arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a
third party) even if such damage or loss was reasonably foreseeable or Lime Microsystems had been advised of the possibility of the same. Lime
Microsystems assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not
reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions
of the Limited Warranties. Lime Microsystems products are not designed or intended to be fail-safe or for use in any application requiring fail-safe
performance; you assume sole risk and liability for use of Lime Microsystems products in Critical Applications.
Lime Microsystems
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United Kingdom
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