RTL8380M-CG
MULTI-LAYER MANAGED 18*10/100/
RTL8382M-CG
MULTI-LAYER MANAGED 28*10/100/
RTL8382L-CG
UN-MANAGED 26*10/100/1000M-PORT SWITCH CONTROLLERS
DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 0.7
20 February. 2013
Track ID:
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8380M/RTL8382M/RTL8382L
Datasheet
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing the
Realtek Ethernet Switch Controllers.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
0.1
0.2
0.3
0.4
Release Date
2012/05/12
2012/08/08
2012/09/18
2012/10/18
Summary
Initial draft.
Updated.
Revised the pin description error for MEM_TYPE[1:0] on table 14, 30 and 44.
Add 11.4 AC characteristics；
0.5
2013/01/24
0.6
0.7
2013/02/20
2013/05/02
Update RTL8382L pin assignment；
Add uart1 interface description;
Add GPIO[14:11] and GPO10 description;
Modify the ddr2 and spi flash timing Characteristics；
Add ddr3 timing Characteristics；
Modify the description for CLK_M_EE[1:0];
Modify the AC Characteristic of QSGMII VTX-DIFFp-p and VRX-DIFFp-p;
Modify the operating range of the DVDDL, AVDDL, SVDDL, AVDDL_PLL,
PLLVDDL and VDDIO.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
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Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS...............................................................................................................................................3
3.1.
3.2.
3.3.
3.4.
4.
BLOCK DIAGRAMS.........................................................................................................................................................7
4.1.
4.2.
4.3.
5.
RTL8380M: MANAGED 16*1000M UTP+2*1000BASE-X SWITCH ............................................................................3
RTL8382M: MANAGED 28*1000M SWITCH VIA RTL8218B PHY .............................................................................4
RTL8382M: MANAGED 20*1000M UTP+4*1000M COMBO SWITCH ........................................................................5
RTL8382M/RTL8382L: MANAGED/UNMANAGED 24*1000M UTP+2*1000BASE-X SWITCH ..................................6
RTL8380M BLOCK DIAGRAM .....................................................................................................................................7
RTL8382M BLOCK DIAGRAM .....................................................................................................................................8
RTL8382L BLOCK DIAGRAM ......................................................................................................................................9
PIN ASSIGNMENTS AND DESCRIPTION (RTL8380M)..........................................................................................10
5.1.
PIN ASSIGNMENTS FIGURE (RTL8380M) ..................................................................................................................10
5.2.
PACKAGE IDENTIFICATION .........................................................................................................................................11
5.3.
PIN ASSIGNMENTS TABLE CODES (RTL8380M)........................................................................................................11
5.4.
PIN ASSIGNMENTS TABLE (RTL8380M)....................................................................................................................11
5.5.
PIN DESCRIPTIONS (RTL8380M)...............................................................................................................................16
5.5.1. 1000M Ethernet PHY MDI Interface Pins............................................................................................................16
5.5.2. SGMII Interface Pins............................................................................................................................................17
5.5.3. RSGMII Interface Pins .........................................................................................................................................18
5.5.4. QSGMII Interface Pins.........................................................................................................................................18
5.5.5. 1000Base-X/100Base-FX Interface Pins ..............................................................................................................18
5.5.6. DDR1/2 SDRAM Interface Pins ...........................................................................................................................19
5.5.7. DDR3 SDRAM Interface Pins ..............................................................................................................................19
5.5.8. Master Mode-SPI Flash Interface Pins ................................................................................................................20
5.5.9. UART Interface Pins.............................................................................................................................................20
5.5.10.
LED Interface Pins ..........................................................................................................................................21
5.5.11.
GPIO Interface Pins ........................................................................................................................................21
5.5.12.
EJTAG Interface Pins ......................................................................................................................................21
5.5.13.
Configuration Strapping Pins..........................................................................................................................22
5.5.14.
Miscellaneous Interface Pins...........................................................................................................................23
5.5.15.
Power and GND Pins ......................................................................................................................................24
6.
PIN ASSIGNMENTS AND DESCRIPTION (RTL8382M)..........................................................................................25
6.1.
PIN ASSIGNMENTS FIGURE (RTL8382M) ..................................................................................................................25
6.2.
PACKAGE IDENTIFICATION .........................................................................................................................................25
6.3.
PIN ASSIGNMENTS TABLE CODES (RTL8382M)........................................................................................................26
6.4.
PIN ASSIGNMENTS TABLE (RTL8382M)....................................................................................................................26
6.5.
PIN DESCRIPTION (RTL8382M).................................................................................................................................30
6.5.1. 1000M Ethernet PHY MDI Interface Pins............................................................................................................30
6.5.2. SGMII Interface Pins............................................................................................................................................32
6.5.3. RSGMII Interface Pins .........................................................................................................................................32
6.5.4. QSGMII Interface Pins.........................................................................................................................................32
6.5.5. 1000Base-X/100Base-FX Interface Pins ..............................................................................................................33
6.5.6. DDR1/2 SDRAM Interface Pins ...........................................................................................................................33
6.5.7. DDR3 SDRAM Interface Pins ..............................................................................................................................34
6.5.8. Master Mode-SPI Flash Interface Pins ................................................................................................................35
6.5.9. UART Interface Pins.............................................................................................................................................35
6.5.10.
LED Interface Pins ..........................................................................................................................................35
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6.5.11.
6.5.12.
6.5.13.
6.5.14.
6.5.15.
7.
GPIO Interface Pins ........................................................................................................................................35
EJTAG Interface Pins ......................................................................................................................................36
Configuration Strapping Pins..........................................................................................................................36
Miscellaneous Interface Pins...........................................................................................................................37
Power and GND Pins ......................................................................................................................................38
PIN ASSIGNMENTS AND DESCRIPTION (RTL8382L)...........................................................................................39
7.1.
PIN ASSIGNMENTS FIGURE (RTL8382L) ...................................................................................................................39
7.2.
PACKAGE IDENTIFICATION .........................................................................................................................................40
7.3.
PIN ASSIGNMENTS TABLE CODES (RTL8382L).........................................................................................................40
7.4.
PIN ASSIGNMENTS TABLE (RTL8382L).....................................................................................................................40
7.5.
PIN DESCRIPTIONS (RTL8382L) ................................................................................................................................44
7.5.1. 1000M Ethernet PHY MDI Interface Pins............................................................................................................44
7.5.2. SGMII Interface Pins............................................................................................................................................46
7.5.3. QSGMII Interface Pins.........................................................................................................................................46
7.5.4. 1000Base-X/100Base-FX Interface Pins ..............................................................................................................46
7.5.5. Master Mode-SPI Flash Interface Pins ................................................................................................................47
7.5.6. UART Interface Pins.............................................................................................................................................47
7.5.7. LED Interface Pins ...............................................................................................................................................47
7.5.8. GPIO Interface Pins .............................................................................................................................................48
7.5.9. Configuration Strapping Pins...............................................................................................................................48
7.5.10.
Miscellaneous Interface Pins...........................................................................................................................49
7.5.11.
Power and GND Pins ......................................................................................................................................50
8.
SWITCH FUNCTION DESCRIPTION .........................................................................................................................51
8.1.
HARDWARE RESET AND SOFTWARE RESET ................................................................................................................51
8.1.1. Hardware Reset ....................................................................................................................................................51
8.1.2. Software Reset ......................................................................................................................................................51
8.2.
CRYSTAL....................................................................................................................................................................51
8.3.
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................51
8.4.
LAYER 2 LEARNING AND FORWARDING .....................................................................................................................52
8.4.1. Forwarding...........................................................................................................................................................52
8.4.2. Learning ...............................................................................................................................................................52
8.4.3. DA/SA Block .........................................................................................................................................................52
8.5.
PORT ISOLATION ........................................................................................................................................................53
8.6.
IEEE 802.3X FLOW CONTROL ...................................................................................................................................54
8.7.
HALF DUPLEX BACKPRESSURE ..................................................................................................................................55
8.7.1. Collision-Based Backpressure (Jam Mode) .........................................................................................................55
8.7.2. Carrier-Based Backpressure (I.e., Defer Mode) ..................................................................................................55
8.8.
LAYER 2 MULTICAST AND IP MULTICAST .................................................................................................................56
8.9.
IEEE 802.1D/1W/1S (STP/RSTP/MSTP)...................................................................................................................56
8.10.
IEEE 802.1P AND IEEE 802.1Q (VLAN) ..................................................................................................................57
8.11.
IEEE 802.1X (NETWORK ACCESS CONTROL)............................................................................................................58
8.12.
RESERVED MULTICAST ADDRESS HANDLING ............................................................................................................59
8.13.
LAYER 2 TRAFFIC SUPPRESSION (STORM CONTROL) .................................................................................................60
8.14.
PIE (PACKET INSPECTION ENGINE)............................................................................................................................60
8.14.1.
Ingress ACL .....................................................................................................................................................60
8.15.
INPUT BANDWIDTH CONTROL AND ACL TRAFFIC METER .........................................................................................61
8.15.1.
Input Bandwidth Control .................................................................................................................................61
8.15.2.
ACL Traffic Meter............................................................................................................................................61
8.16.
IEEE 802.3AD LINK AGGREGATION PROTOCOL ........................................................................................................61
8.17.
IEEE 802.1AD VLAN STACKING...............................................................................................................................62
8.18.
QUALITY OF SERVICE (QOS)......................................................................................................................................63
8.19.
PACKET SCHEDULING (WRR AND WFQ)...................................................................................................................64
8.20.
PACKET DROP ALGORITHM (TD)...............................................................................................................................65
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8.21.
EGRESS PACKET REMARKING ....................................................................................................................................65
8.22.
INGRESS AND EGRESS PORT MIRROR .........................................................................................................................65
8.22.1.
Remote Mirror (RAPAN) .................................................................................................................................66
8.23.
MANAGEMENT INFORMATION BASE (MIB) ...............................................................................................................67
8.24.
NIC AND CPU TAG FORWARDING .............................................................................................................................67
8.25.
INDIRECT TABLE ACCESS ...........................................................................................................................................68
8.26.
EXTERNAL PHY REGISTER ACCESS ...........................................................................................................................68
8.27.
SWITCH INTERRUPT INDICATION ................................................................................................................................68
9.
CPU FUNCTION DESCRIPTION .................................................................................................................................68
9.1.
9.2.
9.3.
10.
INTERFACE DESCRIPTIONS ......................................................................................................................................70
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
10.9.
10.10.
10.11.
10.12.
10.13.
11.
MIPS-4KEC...............................................................................................................................................................68
SPI FLASH..................................................................................................................................................................69
SDRAM INTERFACE CONFIGURATION (RTL8380M/RTL8382M ONLY)..................................................................69
QSGMII ....................................................................................................................................................................70
RSGMII.....................................................................................................................................................................70
SGMII .......................................................................................................................................................................71
DDR1 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................72
DDR2 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................73
DDR3 SDRAM (RTL8380M/RTL8382M ONLY).....................................................................................................74
SPI FLASH INTERFACE ...............................................................................................................................................74
UART........................................................................................................................................................................75
EJTAG ......................................................................................................................................................................75
I2C MASTER FOR EEPROM ......................................................................................................................................76
I2C SLAVE INTERFACE ...............................................................................................................................................76
SPI SLAVE INTERFACE ...............................................................................................................................................77
SERIAL LED...............................................................................................................................................................78
ELECTRICAL AC/DC CHARACTERISTICS.............................................................................................................80
11.1.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................80
11.2.
OPERATING RANGE ....................................................................................................................................................80
11.3.
DC CHARACTERISTICS ...............................................................................................................................................81
11.4.
AC CHARACTERISTICS ...............................................................................................................................................81
11.4.1.
QSGMII Differential Transmitter Characteristics...........................................................................................81
11.4.2.
QSGMII Differential Receiver Characteristics................................................................................................82
11.4.3.
RSGMII Differential Transmitter Characteristics ...........................................................................................84
11.4.4.
RSGMII Differential Receiver Characteristics ................................................................................................85
11.4.5.
SGMII Differential Transmitter Characteristics..............................................................................................86
11.4.6.
SGMII Differential Receiver Characteristics ..................................................................................................87
11.4.7.
DDR2 Characteristics .....................................................................................................................................88
11.4.8.
DDR3 Characteristics .....................................................................................................................................89
11.4.9.
SPI Interface Characteristics...........................................................................................................................90
11.4.10.
SMI (MDC/MDIO) Interface Characteristics..................................................................................................91
12.
PACKAGE INFORMATION..........................................................................................................................................92
12.1.
13.
LQFP216-E-PAD (24*24MM) ...................................................................................................................................92
ORDERING INFORMATION........................................................................................................................................94
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Datasheet
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE (RTL8380M)......................................................................................................................11
TABLE 2. 1000M ETHERNET PHY MDI INTERFACE PINS ............................................................................................................16
TABLE 3. SGMII INTERFACE PINS ...............................................................................................................................................17
TABLE 4. RSGMII INTERFACE PINS ............................................................................................................................................18
TABLE 5. QSGMII INTERFACE PINS ............................................................................................................................................18
TABLE 6. 1000BASE-X/100BASE-FX INTERFACE PINS ...............................................................................................................18
TABLE 7. DDR1/2 SDRAM INTERFACE PINS ..............................................................................................................................19
TABLE 8. DDR3 SDRAM INTERFACE PINS .................................................................................................................................19
TABLE 9. MASTER MODE-SPI FLASH INTERFACE PINS ...............................................................................................................20
TABLE 10. UART INTERFACE PINS ...............................................................................................................................................20
TABLE 11. LED INTERFACE PINS ..................................................................................................................................................21
TABLE 12. GPIO INTERFACE PINS ................................................................................................................................................21
TABLE 13. EJTAG INTERFACE PINS ..............................................................................................................................................21
TABLE 14. CONFIGURATION STRAPPING PINS ...............................................................................................................................22
TABLE 15. MISCELLANEOUS INTERFACE PINS...............................................................................................................................23
TABLE 16. POWER AND GND PINS ................................................................................................................................................24
TABLE 17. PIN ASSIGNMENTS TABLE (RTL8382M) .....................................................................................................................26
TABLE 18. 1000M ETHERNET PHY MDI INTERFACE PINS ...........................................................................................................30
TABLE 19. SGMII INTERFACE PINS...............................................................................................................................................32
TABLE 20. RSGMII INTERFACE PINS ............................................................................................................................................32
TABLE 21. QSGMII INTERFACE PINS ............................................................................................................................................32
TABLE 22. 1000BASE-X/100BASE-FX INTERFACE PINS ...............................................................................................................33
TABLE 23. DDR1/2 SDRAM INTERFACE PINS .............................................................................................................................33
TABLE 24. DDR3 SDRAM INTERFACE PINS ................................................................................................................................34
TABLE 25. MASTER MODE-SPI FLASH INTERFACE PINS ...............................................................................................................35
TABLE 26. UART INTERFACE PINS ...............................................................................................................................................35
TABLE 27. LED INTERFACE PINS ..................................................................................................................................................35
TABLE 28. GPIO INTERFACE PINS ................................................................................................................................................35
TABLE 29. EJTAG INTERFACE PINS ..............................................................................................................................................36
TABLE 30. CONFIGURATION STRAPPING PINS ...............................................................................................................................36
TABLE 31. MISCELLANEOUS INTERFACE PINS...............................................................................................................................37
TABLE 32. POWER AND GND PINS ................................................................................................................................................38
TABLE 33. PIN ASSIGNMENTS TABLE (RTL8382L) ......................................................................................................................40
TABLE 34. 1000M ETHERNET PHY MDI INTERFACE PINS ...........................................................................................................44
TABLE 35. SGMII INTERFACE PINS...............................................................................................................................................46
TABLE 37. QSGMII INTERFACE PINS ............................................................................................................................................46
TABLE 38. 1000BASE-X/100BASE-FX INTERFACE PINS ...............................................................................................................46
TABLE 39. MASTER MODE-SPI FLASH INTERFACE PINS ...............................................................................................................47
TABLE 40. UART INTERFACE PINS ...............................................................................................................................................47
TABLE 41. LED INTERFACE PINS ..................................................................................................................................................47
TABLE 42. GPIO INTERFACE PINS ................................................................................................................................................48
TABLE 43. CONFIGURATION STRAPPING PINS ...............................................................................................................................48
TABLE 44. MISCELLANEOUS INTERFACE PINS...............................................................................................................................49
TABLE 45. POWER AND GND PINS ................................................................................................................................................50
TABLE 46. SPANNING TREE AND RAPID SPANNING TREE ACTION ................................................................................................57
TABLE 47. FORWARDING OF HOST N .............................................................................................................................................59
TABLE 48. RESERVED MULTICAST ADDRESS DEFAULT ACTIONS .................................................................................................59
TABLE 49. UART CONTROL INTERFACE PINS...............................................................................................................................75
TABLE 50. EJTAG INTERFACE PINS ..............................................................................................................................................75
TABLE 51. SPI SLAVE INTERFACE .................................................................................................................................................77
TABLE 52. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................80
TABLE 53. RECOMMENDED OPERATING RANGE ...........................................................................................................................80
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TABLE 54. DC CHARACTERISTICS (IO_POWER=3.3V) .................................................................................................................81
TABLE 55. QSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS .........................................................................................81
TABLE 56. QSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ...............................................................................................82
TABLE 57. RSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS .........................................................................................84
TABLE 58. RSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ...............................................................................................85
TABLE 59. SGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS ............................................................................................86
TABLE 60. SGMII DIFFERENTIAL RECEIVER CHARACTERISTICS .................................................................................................87
TABLE 61. DDR2 SDRAM TIMING CHARACTERISTICS ................................................................................................................88
TABLE 62. DDR3 SDRAM TIMING CHARACTERISTICS ................................................................................................................89
TABLE 63. SPI INTERFACE TIMING CHARACTERISTICS .................................................................................................................90
TABLE 64. SMI (MDC/MDIO) TIMING CHARACTERISTICS ..........................................................................................................91
TABLE 65. ORDERING INFORMATION ............................................................................................................................................94
List of Figures
FIGURE 1. MANAGED 16*1000M UTP+2*1000BASE-X SWITCH ..................................................................................................3
FIGURE 2. MANAGED/UNMANAGED 28*1000M SWITCH VIA RTL8218B PHY.............................................................................4
FIGURE 3. MANAGED/UNMANAGED 20*1000M UTP+4*1000M COMBO SWITCH ........................................................................5
FIGURE 4. MANAGED/UNMANAGED 24*1000M UTP+2*1000BASE-X SWITCH ...........................................................................6
FIGURE 5. RTL8380M BLOCK DIAGRAM ......................................................................................................................................7
FIGURE 6. RTL8382M BLOCK DIAGRAM ......................................................................................................................................8
FIGURE 7. RTL8382L BLOCK DIAGRAM .......................................................................................................................................9
FIGURE 8. PIN ASSIGNMENTS (RTL8380M) ................................................................................................................................10
FIGURE 9. PIN ASSIGNMENTS (RTL8382M) ................................................................................................................................25
FIGURE 10. PIN ASSIGNMENTS (RTL8382L).................................................................................................................................39
FIGURE 11. DA/SA BLOCK ...........................................................................................................................................................52
FIGURE 12. PORT ISOLATION EXAMPLE ........................................................................................................................................53
FIGURE 13. TX PAUSE FRAME FORMAT ........................................................................................................................................54
FIGURE 14. FLOW CONTROL STATE MACHINE ..............................................................................................................................54
FIGURE 15. SIGNAL TIMING FOR COLLISION-BASED BACKPRESSURE ...........................................................................................55
FIGURE 16. SPANNING TREE AND RAPID SPANNING TREE PORT STATES ......................................................................................56
FIGURE 17. IEEE 802.1AD FRAME FORMAT ..................................................................................................................................62
FIGURE 18. PRIORITY SELECTION TABLE WEIGHT RULES EXAMPLE 1..........................................................................................63
FIGURE 19. PER-PORT QUEUE MANAGEMENT...............................................................................................................................64
FIGURE 20. RSPAN ENCAPSULATION ...........................................................................................................................................66
FIGURE 21. RSPAN ILLUSTRATION ..............................................................................................................................................66
FIGURE 22. NIC ARCHITECTURE ...................................................................................................................................................67
FIGURE 23. QSGMII INTERCONNECTION ......................................................................................................................................70
FIGURE 24. RSGMII INTERCONNECTION ......................................................................................................................................70
FIGURE 25. SGMII SIGNAL ...........................................................................................................................................................71
FIGURE 26. DDR1 SDRAM CONFIGURATION ..............................................................................................................................72
FIGURE 27. DDR2 SDRAM CONFIGURATION ..............................................................................................................................73
FIGURE 28. DDR3 SDRAM CONFIGURATION ..............................................................................................................................74
FIGURE 29. SPI FLASH CONFIGURATION .......................................................................................................................................74
FIGURE 30. EJTAG USING A 5-PIN JTAG INTERFACE TO ACCESS DATA BLOCK..........................................................................75
FIGURE 31. 8-BIT EEPROM SEQUENTIAL READ ..........................................................................................................................76
FIGURE 32. I2C SLAVE INTERFACE ACCESS DATA SEQUENCE ......................................................................................................76
FIGURE 33. SERIAL LED CONNECTION .........................................................................................................................................78
FIGURE 34. QSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM ..............................................................................................82
FIGURE 35. QSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM ....................................................................................................83
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FIGURE 36. RSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM ..............................................................................................84
FIGURE 37. RSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM .....................................................................................................85
FIGURE 38. SGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM .................................................................................................86
FIGURE 39. SGMII DIFFERENTIAL RECEIVER EYE DIAGRAM .......................................................................................................87
FIGURE 40. DDR2 TIMING CHARACTERISTICS ..............................................................................................................................88
FIGURE 41. DDR3 TIMING CHARACTERISTICS ..............................................................................................................................89
FIGURE 42. SPI INTERFACE TIMING ..............................................................................................................................................90
FIGURE 43. SMI (MDC/MDIO) TIMING .......................................................................................................................................91
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1.
General Description
The RTL8380M-CG, RTL8382M-CG, and RTL8382L-CG are new generation Gigabit switches
supporting Energy Efficient Ethernet (EEE). The RTL8380M is an 18-port 10/100/1000M switch
controller, and the RTL8382M is 28-port while RTL8382L is an 26-port 10/100/1000 switch controllers.
All of them have an 8-port 10/100/1000M Ethernet PHY embedded.
The RTL8380M/RTL8382M/RTL8382L are provided via a 55nm CMOS process in an LQFP-216 EPAD package. The Memory interface of the RTL8380M/RTL8382M support DDR1/DDR2/DDR3 and
SPI Flash. The RTL8382L supports only SPI Flash.
The following table list the main differences between RTL8380M/RTL8382M/RTL8382L:
Features
Port Capcacity
Management
Mode
DDR1/2/3
SPI Flash
EEPROM config
Internal CPU
RTL8380M
RTL8382M
RTL8382L
16G*UTP + 2*1000Base‐X
24G*UTP + 4GCombo
24G*UTP + 2*1000Base‐X
Managed Mode Only
Yes
Yes
Yes
Yes
Managed Mode Only
Yes
Yes
Yes
Yes
Unmanagement Mode Only
No
Yes
Yes
Yes
The RTL8380M support two pairs of serially connected QSGMII interface ports to connect to one Octal
Gigabit PHY (RTL8218B). It also supports two interfaces of SGMII or 1000Base-X.
The RTL8382M/RTL8382L support four pairs of serially connected QSGMII interface ports to connect
to two Octal Gigabit PHYs (RTL8218B). The RTL8382M also supports one serially connected QSGMII
interface port to connect to 1 Quad Gigabit PHY (RTL8214FC).
The RTL8380M/RTL8382M/RTL8382L have an embedded 500MHz MIPS-4KEc CPU that supports a
32MByte (max.) SPI flash (Only the RTL8380M/RTL8382M support DDR1/DDR2/DDR3). Two
16C550 compatible UARTs are integrated for low speed serial data, and one E-JTAG is supported for onchip debugging.
There are 8K entries in the 4-way hash L2 table for MAC address learning and searching. The
RTL8380M/RTL8382M/RTL8382L supports two hash algorithms. An independent 512-entry Multicast
table supports Layer 2 and IP multicast functions.
The RTL8380M/RTL8382M/RTL8382L has a 4K-entry VLAN table for 802.1Q port-based, protocoland-port-based, 802.1Q-based, IP-subnet-based, and ACL Rules-based VLAN operation to separate
logical connectivity from physical connectivity. Support is provided for IVL (Independent VLAN
Learning), SVL (Shared VLAN Learning), and IVL/SVL (both Independent and Shared VLAN Learning)
for flexible network topology architecture. The RTL8380M/RTL8382M/RTL8382L supports a 1.5Kentry Access Control List (ACL) that parses various protocol packet types and performs configurable
actions, e.g., Permit/Drop, redirect, and traffic policing.
The RTL8380M/RTL8382M/RTL8382L supports per-port ingress/egress bandwidth control and perqueue egress bandwidth control. It has 8 physical queues in each port. The RTL8380M/RTL832M/
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
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RTL8380M/RTL8382M/RTL8382L
Datasheet
RTL8382L provides three types of packet scheduling; SP (Strict Priority), WFQ (Weighted Fair Queuing),
and WRR (Weighted Round Robin). Each queue provides a leaky-bucket to shape the incoming traffic
into the average rate behavior.
Port-based 802.1X and MAC-based 802.1X authentication prevent unauthorized users from accessing
internal servers. The RTL8380M/RTL8382M/RTL8382L supports port isolation to enhance port security.
The RTL8380M/RTL8382M/RTL8382L also supports a 4-set port mirror configuration to mirror ingress
and egress traffic. For network management purposes, complete MIB counter support reflects the switch
status in real time. Support is provided for link aggregation to increase link redundancy, and increase
linear bandwidth.
The RTL8380M/RTL8382M/RTL8382L adopts advanced technologies such as Realtek Cable Test
(RTCT), Automatic loop detection and prevention (RLPP/RLDP), Attack Prevention, and MAC Address
Learning Constraints.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
2
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
2.
Features
32 Translation Look-aside Buffer
(TLB) entries
Two UART interfaces to control the
internal CPU via a Command Line
Interface (CLI)
Hardware Interface
RTL8380M
18-port Gigabit wire speed
forwarding capability
Supports 8-port 10/100/1000M
Ethernet PHY
Supports 2-pairs of QSGMII to
connect to external 8-port
10/100/1000M Ethernet PHYs
Supports one RSGMII or two pairs of
SGMII/1000Base-X
RTL8382M /RTL8382L
RTL8382M provide 28-port Gigabit
wire speed forwarding capability
RTL8382L provide 26-port Gigabit
wire speed forwarding capability
Supports 8-port 10/100/1000M
Ethernet PHY
Supports 4-pairs of QSGMII to
connect to external 8-port
10/100/1000M Ethernet PHYs
RTL8382M supports an extra 1 pair
of QSGMII or 2 pairs of
RSGMII/SGMII/1000Base-X
RTL8382L supports 2 pairs of
SGMII/1000Base-X
DRAM and Flash Interface
RTL8380M/RTL8382M supports one
8-bit 128MByte DDR1/DDR2 or one
8-bit 256MByte DDR3 for internal
CPU
Supports one 32MByte SPI flash
interface
Embedded MIPS-4KEc with MMU
MIPS32 instruction set and 5-stage
pipeline
500MHz CPU clock rate
16KByte I-Cache and 16KByte DCache
Built-in 128KByte SRAM
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Supports EJTAG interface
I2C and slave SPI interface for external
master interface to access internal
registers
L2 VLAN Function
Supports IVL, SVL, and IVL/SVL
Supports IEEE 802.1Q VLAN
4K-entry VLAN Table
Port-based VLAN
Port-and-protocol-based VLAN
ACL-based VLAN
Supports up to 64 spanning tree
instances for MSTP (IEEE 802.1s),
RSTP, and STP
Supports flexible Q-in-Q and VLAN Tag
function
L2 MAC Function
4.1 Mbit SRAM Packet Buffer
Packet length of 10KBytes
8K-entry L2 MAC table with 4-way
hashing algorithm
Independent 512-entry L2/IP Multicast
table for multicast function
2-hash algorithm selection for L2 table
searching/learning
Aging timer range from 0.2s to
1600000s
Supports IGMPv1/2/3 and MLDv1/2
snooping
3
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Supports Reserved Multicast Addresses
processing
256 log counters to enhance MIB count
functionality
Limited learned L2 MAC entry on each
port and each VLAN
Supports multiple action
Supports L3 Unicast Routing, 512 next
hop MAC Support
L2 Miscellaneous Functions
Supports Port Mirroring
Supports 4-sets of port mirrors
Flow-based mirror function
RSPAN function for remote mirroring
Supports Link Aggregation (IEEE
802.3ad) for 8 groups of link aggregators
with up to 8 ports per-group
Port isolation function to enhance port
security
Software supports IEEE 802.1x,
Supports broadcast, multicast, unknownmulticast, and unknown-unicast packet
suppression control
Attack Prevention
Land attack
Blat attack
TCP control flag attack
Ping attack
Packet length attack
Supports Automatic loop detection and
isolation (RLPP/RLDP)
Access Control List (ACL) Function
QoS Functions
8 physical queues per port
Strict Priority (SP) and Weighted Fair
Queue (WFQ), Weighted Round Robin
(WRR) packet scheduling
QoS remarking for 802.1p and DSCP
(includes IPv4/IPv6)
Supports average packet rate control
leaky-bucket per queue, in 16Kbps steps
up to 1Gbps maximum
Ingress port bandwidth control, in
16Kbps steps up to 1Gbps maximum
Egress port bandwidth control, in
16Kbps steps up to 1Gbps maximum
EAV, 1588v2
Cable Diagnostics (RTCT)
IEEE 802.3az Energy Efficient Ethernet
(EEE)
MIB Functions
1.5K-entry ACL table
Ethernet-like MIB (RFC 3635)
L2/L3/L4 format (e.g., DMAC, SMAC,
and Ether-Type)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
IPv6 Parsing
Bridge MIB (RFC 1493)
Per-flow traffic policing
Bridge MIB Extension (RFC 2674)
16-entry VID range checking
8-entry IPv4 or 2-entry IPv6 range
checking
256 leaky-buckets for flow traffic
policing; in 16Kbps steps up to 1Gbps
maximum
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Others
55nm CMOS process
3.3V/1.0V dual power input
LQFP216 E-PAD package
3
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
3.
System Applications
3.1. RTL8380M: Managed 16*1000M UTP+2*1000Base-X
Switch
Figure 1. Managed 16*1000M UTP+2*1000Base-X Switch
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
3
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
3.2. RTL8382M: Managed 28*1000M Switch via RTL8218B
PHY
DDR1/DDR2/DDR3*
Flash
Managed
28*1000M port Switch
RTL8382M (28*1000M Switch)
LQFP216-EPAD
RTL8218B
RTL8218B
RTL8214FC
Copper
/fiber
auto-det
LED
Interface
Figure 2. Managed 28*1000M Switch via RTL8218B PHY
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
4
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
3.3. RTL8382M: Managed 20*1000M UTP+4*1000M Combo
Switch
Figure 3. Managed 20*1000M UTP+4*1000M Combo Switch
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
5
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
3.4. RTL8382M/RTL8382L: Managed/Unmanaged 24*1000M
UTP+2*1000Base-X Switch
Figure 4. Managed/Unmanaged 24*1000M UTP+2*1000Base-X Switch
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
6
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
4.
Block Diagrams
4.1. RTL8380M Block Diagram
Scan or
Serial LED
GPIO
DDR1/DDR2/ SPI Flash/
DDR3
I2C EEPROM
UART0 UART1 EJTAG
MIPS-4KEc
32bits@500M
Hz
LED
Controller
GPIO
Controller
EEPROM
/I2C/SPI
Register
Controller
RSGMII/SGMII/ SGMII/
1000Base-X/ 1000Base-X/
100Base-FX 100Base-FX
Serdes2
Serdes3
GMAC16
GMAC17
Memory
Controller
2*UART
Controller
128KB
SRAM
Interrupt
Controller
GMAC18
and NIC
Packet Buffer (4.1 Mbit SRAM)
Flow Control
Traffic Classification
L2 and Forwarding Table
802.3ad
Qos Manager
Storm Control
VLAN Table
Scheduler(SP/WRR/WFQ)
EEE
802.1x and STP
ACL Table
VLAN Tag/Untag
Attack Prevention
Input Bandwidth Control
Q-in-Q Table
Output Bandwidth Control
MAC 0
MAC 1
MAC 2
MAC 3
MAC 4
MAC 5
MAC 6
MAC 7
PHY0~7 (Gigabit)
8*GE
MAC 8-11
MAC 12-15
Serdes 0
Serdes 1
2*QSGMII
Figure 5. RTL8380M Block Diagram
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
7
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
4.2. RTL8382M Block Diagram
Figure 6. RTL8382M Block Diagram
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
8
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
4.3. RTL8382L Block Diagram
Figure 7. RTL8382L Block Diagram
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
9
Track ID:
Rev. 0.7
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
DVDDL
DVDDH
JTAG_TCK
JTAG_TMS
JTAG_TDO/EEPROMTYPE
JTAG_TDI
JTAG_TRST#
DVDDL
DVDDL
DVDDH
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MVDDH
DDR12_WE#/DDR3_WE#
DVDDL
DDR12_RAS#/DDR3_CAS#
DDR12_CAS#/DDR3_RAS#
DDR12_A11/DDR3_A10/LED_MODE[0]
DDR12_A13/DDR3_A11/LED_MODE[1]
DDR3_A14/SPI_ADDR_SEL
DDR12_A8/DDR3_A1/SDS_PDOWN_EN
DDR12_A6/DDR3_A8/SEL_XTAL_CLK
DDR12_A4/DDR3_A6/PWRBLINK[1]
DDR12_A2/DDR3_A4/PWRBLINK[0]
DDR12_A0/DDR3_A12/DIS_EEE
DDR12_CS#/DDR3_BA1
DDR12_ODT/DDR3_CKE
DDR12_D5/DDR3_D5
DDR12_D2/DDR3_D7
DDR12_D0/DDR3_D1
DDR12_D7/DDR3_D3
VREF
DDR12_DQS/DDR3_DM
DDR12_CLK/DDR3_CLK
DDR12_CLK#/DDR3_CLK#
DVDDL
DDR3_DQS#
DDR12_DM/DDR3_DQS
DDR12_D6/DDR3_D0
DDR12_D1/DDR3_D4
DDR12_D3/DDR3_D2
DDR12_D4/DDR3_D6
MVDDH
DVDDH
SPI_CLK
SPI_SO/SIO1
SPI_SI/SIO0
SPI_CS#0
DVDDL
UART0_RX
UART0_TX/REG_IF_SEL
LED_DAT
LED_CLK
MDIO
MDC
SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
SSPI_SO/DIS_PHYAUTO_UP
SSPI_CS#
DVDDH
RESET#
GPIO0
GPIO1
GPIO2
GPIO3
DVDDL
RTL8380M/RTL8382M/RTL8382L
Datasheet
5.
Pin Assignments and Description (RTL8380M)
5.1. Pin Assignments Figure (RTL8380M)
Figure 8. Pin Assignments (RTL8380M)
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
10
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
5.2. Package Identification
Green package is indicated by a ‘G’ in ‘GXXXX’ (Figure 8).
5.3. Pin Assignments Table Codes (RTL8380M)
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
(Typical Value = 75KΩ)
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75KΩ)
IPD: Input Pin With Pull-Down Resistor;
(Typical Value = 75KΩ)
OPD: Output Pin With Pull-Down Resistor;
(Typical Value = 75KΩ)
5.4. Pin Assignments Table (RTL8380M)
Name
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
Table 1.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Assignments Table (RTL8380M)
Type
Name
AI/O
P3MDICP
AI/O
P3MDICN
AP
P3MDIDP
AI/O
P3MDIDN
AI/O
AVDDH
AI/O
AGND
AI/O
MDIREF
AP
AVDDL
AI/O
RTT1
AI/O
RTT2
AI/O
AVDDH
AI/O
DVDDL
AP
DVDDH
AP
JTAG_TCK
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
11
Pin No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Type
AI/O
AI/O
AI/O
AI/O
AP
AG
AO
AP
AI/O
AI/O
AP
DP
DP
I/OPU
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
JTAG_TMS
JTAG_TDO/EEPROMTYPE
JTAG_TDI
JTAG_TRST#
DVDDL
DVDDL
DVDDH
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN
P5MDIDP
P5MDIDN
PLLVDDL
ATESTCK1
P6MDIAP
P6MDIAN
P6MDIBP
P6MDIBN
AVDDL
P6MDICP
P6MDICN
P6MDIDP
P6MDIDN
AVDDH
P7MDIAP
Pin No.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Type
I/OPU
I/OPD
I/OPD
I/OPU
DP
DP
DP
AP
AI/O
AI/O
AI/O
AI/O
AP
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AO
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
P7MDIAN
P7MDIBP
P7MDIBN
AVDDL
P7MDICP
P7MDICN
P7MDIDP
P7MDIDN
AVDDH
DVDDL
CKOUT0
SVDDL
S0TXP
S0TXN
S0RXP
S0RXN
SVDDL
S1TXN
S1TXP
S1RXN
S1RXP
SVDDH
CKOUT2
SVDDL
S2TXP
S2TXN
S2RXP
S2RXN
SVDDL
S3TXN
S3TXP
S3RXN
S3RXP
SVDDL
AVDDH_PLL
XO
XI
AVDDL_PLL
DVDDL
DVDDL
GPIO3
13
Pin No.
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
Type
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
DP
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
AP
AO
AI
AP
P
P
I/OPD
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
GPIO2
GPIO1
GPIO0
RESET#
DVDDH
SSPI_CS#
SSPI_SO/
DIS_PHYAUTO_UP
SSPI_SI/I2C_DAT
SSPI_CLK/I2C_CLK
MDC
MDIO
LED_CLK
LED_DAT
UART0_TX/REG_IF_SEL
UART0_RX
DVDDL
SPI_CS#0
SPI_SI/SIO0
SPI_SO/SIO1
SPI_CLK
DVDDH
MVDDH
DDR12_D4/DDR3_D6
DDR12_D3/DDR3_D2
DDR12_D1/DDR3_D4
DDR12_D6/DDR3_D0
DDR12_DM/DDR3_DQS
DDR3_DQS#
DVDDL
DDR12_CLK#/DDR3_CLK#
DDR12_CLK/DDR3_CLK
DDR12_DQS/DDR3_DM
VREF
DDR12_D7/DDR3_D3
DDR12_D0/DDR3_D1
DDR12_D2/DDR3_D7
DDR12_D5/DDR3_D5
DDR2_ODT/DDR3_CKE
DDR12_CS#/DDR3_BA1
DDR12_A0/DDR3_A12/
DIS_EEE
Pin No.
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Type
I/OPD
I/OPD
I/OPD
AI
P
IPU
I/OPD
I/OPU
I/OPU
OPU
I/OPU
OPU
I/OPU
I/OPD
IPD
P
O
I/OPD
I/OPD
OPD
P
P
I/O
I/O
I/O
I/O
I/O
I/O
P
O
O
I/O
P
I/O
I/O
I/O
I/O
O
O
I/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
DDR12_A2/DDR3_A4/
PWRBLINK[0]
DDR12_A4/DDR3_A6/
PWRBLINK[1]
DDR12_A6/DDR3_A8/
SEL_XTAL_CLK
DDR12_A8/DDR3_A1/
SDS_PDOWN_EN
DDR3_A14/
SPI_ADDR_SEL
DDR12_A13/DDR3_A11/
LED/MODE[1]
DDR12_A11/DDR3_A10/
LED/MODE[0]
DDR12_CAS#/DDR3_RAS#
DDR12_RAS#/DDR3_CAS#
DVDDL
DDR12_WE#/DDR3_WE#
MVDDH
MVDDH
DDR12_CKE/DDR3_BA2
DDR12_BA1/DDR3_A9
DDR12_A1/DDR3_A13/
CPU_SLEEP
DDR12_A12/DDR3_A2/
DRAM_INI_EN
DDR3_RST#
DDR12_A9/DDR3_A7/
MEM_TYPE[1]
DDR12_A7/DDR3_A5/
MEM_TYPE[0]
DDR12_A5/DDR3_A0/
CLK_M_EE[1]
DDR12_A3/DDR3_A3/
CLK_M_EE[0]
DDR12_A10/DDR3_BA0/
EN_DECRYPT
DDR2_BA2/DDR3_CS#
DDR12_BA0/DDR3_ODT
DDR3_ZQ#
MVDDH
DVDDL
VX
RESERVED
SVDDL
14
Pin No.
151
Type
I/O
152
I/O
153
I/O
154
I/O
155
I/O
156
I/O
157
I/O
158
159
160
161
162
163
164
165
166
O
O
P
O
P
P
O
O
I/O
167
I/O
168
169
O
I/O
170
I/O
171
I/O
172
I/O
173
I/O
174
175
176
177
178
179
180
181
O
O
I
P
P
A
AO
AP
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
RESERVED
RESERVED
TEST0
TEST1
SVDDH
RESERVED
RESERVED
TEST2
TEST3
SVDDL
DVDDL
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
Pin No.
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
Type
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
P
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL
ATESTCK0
P2MDIAP
P2MDIAN
DGND
15
Pin No.
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
EPAD
Type
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AO
AI/O
AI/O
G
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
5.5. Pin Descriptions (RTL8380M)
5.5.1.
1000M Ethernet PHY MDI Interface Pins
Table 2. 1000M Ethernet PHY MDI Interface Pins
Type Description
Port 0 Media Dependent Interface A~D.
AI/O
For 1000Base-T operation, differential data from the media is transmitted and
AI/O
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
AI/O
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
AI/O
Pin Name
P0MDIAP
Pin No.
194
P0MDIAN
195
P0MDIBP
196
P0MDIBN
197
P0MDICP
199
AI/O
P0MDICN
200
AI/O
P0MDIDP
201
AI/O
P0MDIDN
202
AI/O
P1MDIAP
204
AI/O
P1MDIAN
205
AI/O
P1MDIBP
206
AI/O
P1MDIBN
207
AI/O
P1MDICP
209
AI/O
P1MDICN
210
AI/O
P1MDIDP
211
AI/O
P1MDIDN
212
AI/O
P2MDIAP
215
AI/O
P2MDIAN
216
AI/O
P2MDIBP
1
AI/O
P2MDIBN
2
AI/O
P2MDICP
4
AI/O
P2MDICN
5
AI/O
P2MDIDP
6
AI/O
P2MDIDN
7
AI/O
P3MDIAP
9
AI/O
P3MDIAN
10
AI/O
P3MDIBP
11
AI/O
P3MDIBN
12
AI/O
P3MDICP
15
AI/O
P3MDICN
16
AI/O
P3MDIDP
17
AI/O
P3MDIDN
18
AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
16
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
P4MDIAP
Pin No.
37
Type
AI/O
P4MDIAN
38
AI/O
P4MDIBP
39
AI/O
P4MDIBN
40
AI/O
P4MDICP
43
AI/O
P4MDICN
44
AI/O
P4MDIDP
45
AI/O
P4MDIDN
46
AI/O
P5MDIAP
48
AI/O
P5MDIAN
49
AI/O
P5MDIBP
50
AI/O
P5MDIBN
51
AI/O
P5MDICP
53
AI/O
P5MDICN
54
AI/O
P5MDIDP
55
AI/O
P5MDIDN
56
AI/O
P6MDIAP
59
AI/O
P6MDIAN
60
AI/O
P6MDIBP
61
AI/O
P6MDIBN
62
AI/O
P6MDICP
64
AI/O
P6MDICN
65
AI/O
P6MDIDP
66
AI/O
P6MDIDN
67
AI/O
P7MDIAP
69
AI/O
P7MDIAN
70
AI/O
P7MDIBP
71
AI/O
P7MDIBN
72
AI/O
P7MDICP
74
AI/O
P7MDICN
75
AI/O
P7MDIDP
76
AI/O
P7MDIDN
77
AI/O
5.5.2.
Description
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 5 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 6 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 7 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
SGMII Interface Pins
Pin Name
Pin No.
Type
S2RXP
96
AI
S2RXN
97
AI
S2TXP
94
AO
Table 3. SGMII Interface Pins
Description
SGMII Interface Receive Data Differential Input Pair.
SGMII Interface Transmit Data Differential Output Pair.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
17
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
Pin No.
Type
S2TXN
95
AO
S3RXP
102
AI
S3RXN
101
AI
S3TXP
100
AO
S3TXN
99
AO
5.5.3.
Pin No.
96
Type
AI
S2RXN
97
AI
S2TXP
94
AO
S2TXN
95
AO
S3RXP
102
AI
S3RXN
101
AI
S3TXP
100
AO
S3TXN
99
AO
SGMII Interface Transmit Data Differential Output Pair.
Table 4. RSGMII Interface Pins
Description
RSGMII Interface Receive Data Differential Input Pair.
RSGMII Interface Transmit Data Differential Output Pair.
RSGMII Interface Receive Data Differential Input Pair.
RSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Pins
Pin Name
S0RXP
Pin No.
84
Type
AI
S0RXN
85
AI
S0TXP
82
AO
S0TXN
83
AO
S1RXP
90
AI
S1RXN
89
AI
S1TXP
88
AO
S1TXN
87
AO
5.5.5.
SGMII Interface Receive Data Differential Input Pair.
RSGMII Interface Pins
Pin Name
S2RXP
5.5.4.
Description
Table 5. QSGMII Interface Pins
Description
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
1000Base-X/100Base-FX Interface Pins
Table 6. 1000Base-X/100Base-FX Interface Pins
Type
Description
1000Base-X/100Base-FX
Interface Receive Data Differential Input Pair.
AI
Pin Name
S2RXP
Pin No.
96
S2RXN
97
AI
S2TXP
94
AO
1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
18
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
Pin No.
Type
S2TXN
95
AO
S3RXP
102
AI
S3RXN
101
AI
S3TXP
100
AO
S3TXN
99
AO
5.5.6.
Description
1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
DDR1/2 SDRAM Interface Pins
Table 7. DDR1/2 SDRAM Interface Pins
Pin Name
DDR12_D[7:0]
Pin No.
DDR2_BA[2]
DDR12_BA[1:0]
DDR12_WE#
DDR12_CKE
DDR12_RAS#
DDR12_CAS#
DDR12_CS#0
DDR2_ODT
DDR12_DQS
DDR12_CLK
144, 136, 147, 133,
134, 146, 135, 145
156, 167, 157, 173,
169, 154, 170, 153,
171, 152, 172, 151,
166, 150
174
165, 175
161
164
159
158
149
148
142
141
DDR12_CLK#
140
DDR12_A[13:0]
5.5.7.
Type
I/O
Drive (mA) Description
8
DDR SDRAM Data Bus.
I/O
8
DDR SDRAM Address Select.
O
O
O
O
O
O
O
O
I/O
O
8
8
8
8
8
8
8
8
8
8
O
8
DDR SDRAM Bank Address Select.
DDR SDRAM Bank Address Select.
DDR SDRAM Write Enable.
DDR SDRAM Clock Enable.
DDR SDRAM Row Address Strobe.
DDR SDRAM Column Address Strobe.
DDR SDRAM Chip Select 0.
DDR SDRAM On-Die Termination.
DDR SDRAM Data Strobe.
DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.
DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.
DDR3 SDRAM Interface Pins
Table 8. DDR3 SDRAM Interface Pins
Pin Name
DDR3_D[7:0]
DDR3_A[14]
DDR3_A[13:10]
DDR3_A[9]
DDR3_A[8:0]
DDR3_DQS#
Pin No.
146, 133, 147, 135,
144, 134, 145, 136
155
166, 150,156, 157
165
153, 169, 152, 170,
151, 172, 167, 154,
171
138
Type
I/O
Drive (mA) Description
8
DDR SDRAM Data Bus.
O
I/O
O
I/O
8
8
8
8
DDR SDRAM Address Select.
DDR SDRAM Address Select.
DDR SDRAM Address Select.
DDR SDRAM Address Select.
I/O
8
DDR SDRAM Data Strobe.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
19
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
DDR3_DQS
DDR3_CLK#
DDR3_CLK
DDR3_DM
DDR3_CKE
DDR3_BA[2:1]
DDR3_BA[0]
DDR3_RAS#
DDR3_CAS#
DDR3_WE#
DDR3_RST#
DDR3_CS#
DDR3_ODT
DDR3_ZQ#
5.5.8.
Pin No.
137
140
141
142
148
164, 149
173
158
159
161
168
174
175
176
Drive (mA)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Description
DDR SDRAM Data Strobe.
DDR SDRAM Clock.
DDR SDRAM Clock.
DDR SDRAM Data Mask.
DDR SDRAM Clock Enable.
DDR SDRAM Bank Address Select.
DDR SDRAM Bank Address Select.
DDR SDRAM Row Address Strobe.
DDR SDRAM Column Address Strobe.
DDR SDRAM Write Enable.
DDR SDRAM Reset.
DDR SDRAM Chip Select.
DDR SDRAM On-Die Termination.
DDR SDRAM External Reference Ball for Output
Drive Calibration.
This pin is tied to an external 240 Ohm resistor, which
is tied to GND.
Master Mode-SPI Flash Interface Pins
Pin Name
SPI_CLK
SPI_SO/SIO1
Pin No.
130
129
SPI_SI/SIO0
128
SPI_CS#0
127
5.5.9.
Type
I/O
O
O
I/O
O
O
I/O
O
O
O
O
O
O
I
Table 9. Master Mode-SPI Flash Interface Pins
Type
Drive (mA) Description
OPD
12
Serial Clock Output Pin.
I/OPD
12
In Serial Mode: This is a flash chip output pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is MSB first.
I/OPD
12
In Serial Mode: This is a flash chip input pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is LSB first.
O
12
Chip Select Output Pin.
Slave Transmit Enable and active low.
UART Interface Pins
Pin Name
UART0_RX
Pin No.
125
Type
IPD
UART0_TX
UART1_RX
124
116
UART1_TX
117
I/OPD
IPU
I/OPD
Table 10. UART Interface Pins
Drive (mA) Description
4
UART0 Interface Receive Data.
4
4
UART0 Interface Transmit Data.
UART1 Interface Receive Data.
4
UART1 Interface Transmit Data.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
20
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
5.5.10. LED Interface Pins
Pin Name
LED_CLK
Pin No.
122
Type
OPU
LED_DAT
123
I/OPU
Table 11. LED Interface Pins
Drive (mA) Description
12
(1) In Serial LED Mode
Reference output clock for serial LED interface and Data is
latched on the rising of LEDCK.
(2) In SMI-like LED Mode
Reference output clock for I2C-like interface.
12
(1) In Serial LED Mode
Serial bit stream of link status information.
(2) In I2C-like LED Mode
The data written to the LED IC.
5.5.11. GPIO Interface Pins
Table 12. GPIO Interface Pins
Type
Drive (mA) Description
This pin default set as system led.
I/OPD
12
By the configuration, it can be set as General
Purpose Input/Output Pin.
Pin Name
Pin No.
GPIO0
113
GPIO[3:1]
110, 111, 112
I/OPD
12
General Purpose Input/Output Pins.
GPO10
30
I/OPD
4
General Purpose Output Pins.
GPIO11
31
I/OPD
4
General Purpose Input/Output Pins.
GPIO[14:12]
32,28,29
I/OPU
4
General Purpose Input/Output Pins.
5.5.12. EJTAG Interface Pins
Pin Name
JTAG_TMS
JTAG_TCK
JTAG_TRST#
JTAG_TDI
JTAG_TDO
Pin No.
29
28
32
31
30
Type
I/OPU
I/OPU
I/OPU
I/OPD
I/OPD
Table 13. EJTAG Interface Pins
Drive (mA) Description
4
JTAG Test Mode Select.
4
JTAG Test Clock Input.
4
JTAG Test Reset.
4
JTAG Test Data Input.
4
JTAG Test Data Output.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
21
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
5.5.13. Configuration Strapping Pins
Pin Name
EEPROMTYPE
DIS_PHYAUTO_UP
REG_IF_SEL
DIS_EEE
PWRBLINK[1:0]
SEL_XTAL_CLK
SDS_PDOWN_EN
SPI_ADDR_SEL
LED_MODE[1:0]
CPU_SLEEP
DRAM_INI_EN
MEM_TYPE[1:0]
Table 14. Configuration Strapping Pins
Pin No. Description
30
Select EEPROM Address Byte Size.
0b0: 1-byte
0b1: 2-byte
117
Disable Asic auto power up PHY：
0b0: enable asic auto power up phy;
0b1: disable asic auto power up phy.
124
Select Switch Core Register Access Interface.
0b0: I2C
0b1: SPI slave
150
Disable 1000M EEE and 100M EEE Function.
0b0: Enable
0b1: Disable
152, 151 Select LED Power On Blinking Timer.
0b00: Disable
0b01: 800ms
0b10: 1.6s
0b11: 3.2s
153
Select XTAL Input is 25M or 125M.
0b0: 25M
0b1:125M
Note: This option is only for sync Ethernet.
154
Enable SerDes Power Down Mode.
0b0: SerDes 2/3 operate in normal mode
0b1: SerDes 2/3 operate in power down mode
155
Select address mode for SPI flash:
0b0: 3Bytes address;
0b1: 4Bytes address.
156, 157 Select LED Mode.
0b00: Serial LED mode
0b01: Scan Single mode
0b10: Scan Bicolor mode
0b11: Disable LED
166
Enable CPU function；
0b0: CPU is always under reset state;
0b1: CPU is enabled.
167
Enable DRAM Initialization Procedure.
0b0: Enable DRAM Initialization procedure
0b1: Bypass DRAM Initialization procedure
169, 170 Select Memory Type for SOC.
0b00: Select SPI flash + DDR-3
0b01: Select SPI flash + DDR-2
0b10: Select SPI flash + DDR-1
0b11: Select EEPROM
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
22
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
CLK_M_EE[1:0]
Pin No.
171, 172
Description
When MEM_TYPE Select is SPI Flash:
This Strapping Pin Selects the Initial Clock for The Memory Controller.
For DDR2:
0b00: Reserved for test;
0b01: Reserved for test;
0b10: 100MHz
0b11: Reserved for test.
For DDR3:
0b00: Reserved for test;
0b01: Reserved for test;
0b10: 125MHz;
0b11: Reserved for test.
Note: The initial value for this strapping pin must set as the reference
design guide recommend.
EN_DECRYPT
173
When MEM_TYPE Select is EEPROM:
CLK_M_EE[0] is used to select SOC EEPROM address byte size.
0b0: 1-byte address
0b1: 2-byte address
Enable or Disable Decrypt for Flash.
0b0: Disable decrypt
0b1: Enable decrypt
5.5.14. Miscellaneous Interface Pins
Pin Name
MDC
MDIO
SSPI_CLK/I2C_CLK
Pin No.
120
121
119
SSPI_SI/I2C_DAT
118
SSPI_SO
SSPI_CS#
RESET#
117
116
114
XI
XO
MDIREF
106
105
21
RTT1
RTT2
VX
CKOUT0
CKOUT2
23
24
179
80
92
Table 15. Miscellaneous Interface Pins
Type Drive (mA) Description
OPU
12
MII Management Interface Clock Pin.
I/OPU
12
MII Management Interface Data Pin.
I/OPU
4
SPI Serial Clock Input (Slave Mode).
I2C Interface Clock Input (Slave Mode).
I2C Interface Clock Output (Master Mode).
I/OPU
4
SPI Serial Data Input (Slave Mode).
I2C Interface Bi-Directional data (Slave Mode).
I/OPD
4
SPI Serial Data Output (Slave Mode).
OUP
4
SPI Serial Chip Select (Slave Mode).
AI
System Pin Reset Input (Low Active).
To complete the reset function, this pin must be asserted
for at least 10ms. It must be pulled up for normal
operation.
AI
25MHz Crystal Clock Input and Feedback Pin.
AO
25MHz Crystal Clock Output Pin.
AO
MDI Bias Resistor.
Adjust the reference current for all PHYs. This pin must
connect to AGND via a 2.49k ohm resistor.
AI/O
Reserved for Internal Use (Must be Left Floating).
AI/O
Reserved for Internal Use (Must be Left Floating).
A
Low Voltage Power Control Resistor.
AO
8
25MHz Clock Output.
AO
8
25MHz Clock Output.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
23
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
ATESTCK[1:0]
RESERVED
TEST[3:0]
Pin No.
Type
58, 214
AO
180, 182, 183,
187, 188
190, 189, 185,
184
Drive (mA) Description
Reserved for Internal Use (Must be Left Floating).
Reserved pins (Must be Left Floating).
-
Reserved for Testing.
5.5.15. Power and GND Pins
Pin Name
AVDDL
PLLVDDL
AVDDH
DVDDL
DVDDH
SVDDL
AVDDL_PLL
SVDDH
AVDDH_PLL
MVDDH
VREF
AGND
DGND
Table 16. Power and GND Pins
Pin No.
Type
Description
AP
Analog Low Voltage Power.
3, 13, 22, 42, 52, 63,
73, 198, 208
57, 213
AP
Analog PLL Low Voltage Power.
AP
Analog High Voltage Power.
8, 14, 19, 25, 36, 41,
47, 68, 78, 193, 203
P
Digital Low Voltage Power.
26, 33, 34, 79, 108,
109, 126, 139, 160,
178, 192
27, 35, 115, 131
P
Digital High Voltage Power.
AP
SerDes Low Voltage Power.
81, 86, 93, 98, 103,
181, 191
107
AP
PLL Low Voltage Power.
91, 186
AP
SerDes High Voltage Power.
104
AP
PLL High Voltage Power.
132, 162, 163,177
P
SDRAM High Voltage Power.
143
P
SSTL Reference Voltage (MVDDH/2).
20
AG
Analog Ground.
E-PAD
G
Digital Ground.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
24
Track ID:
Rev. 0.7
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
DVDDL
DVDDH
JTAG_TCK
JTAG_TMS
JTAG_TDO/EEPROMTYPE
JTAG_TDI
JTAG_TRST#
DVDDL
DVDDL
DVDDH
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MVDDH
DDR12_WE#/DDR3_WE#
DVDDL
DDR12_RAS#/DDR3_CAS#
DDR12_CAS#/DDR3_RAS#
DDR12_A11/DDR3_A10/LED_MODE[0]
DDR12_A13/DDR3_A11/LED_MODE[1]
DDR3_A14/SPI_ADDR_SEL
DDR12_A8/DDR3_A1/SDS_PDOWN_EN
DDR12_A6/DDR3_A8/SEL_XTAL_CLK
DDR12_A4/DDR3_A6/PWRBLINK[1]
DDR12_A2/DDR3_A4/PWRBLINK[0]
DDR12_A0/DDR3_A12/DIS_EEE
DDR12_CS#/DDR3_BA1
DDR2_ODT/DDR3_CKE
DDR12_D5/DDR3_D5
DDR12_D2/DDR3_D7
DDR12_D0/DDR3_D1
DDR12_D7/DDR3_D3
VREF
DDR12_DQS/DDR3_DM
DDR12_CLK/DDR3_CLK
DDR12_CLK#/DDR3_CLK#
DVDDL
DDR3_DQS#
DDR12_DM/DDR3_DQS
DDR12_D6/DDR3_D0
DDR12_D1/DDR3_D4
DDR12_D3/DDR3_D2
DDR12_D4/DDR3_D6
MVDDH
DVDDH
SPI_CLK
SPI_SO/SIO1
SPI_SI/SIO0
SPI_CS#0
DVDDL
UART0_RX
UART0_TX/REG_IF_SEL
LED_DAT
LED_CLK
MDIO
MDC
SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
SSPI_SO/DIS_PHYAUTO_UP
SSPI_CS#
DVDDH
RESET#
GPIO0
GPIO1
GPIO2
GPIO3
DVDDL
RTL8380M/RTL8382M/RTL8382L
Datasheet
6.
Pin Assignments and Description (RTL8382M)
6.1. Pin Assignments Figure (RTL8382M)
Figure 9. Pin Assignments (RTL8382M)
6.2. Package Identification
Green package is indicated by a ‘G’ in ‘GXXXX’ (Figure 9).
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
25
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
6.3. Pin Assignments Table Codes (RTL8382M)
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
(Typical Value = 75KΩ)
IPD: Input Pin With Pull-Down Resistor;
(Typical Value = 75KΩ)
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75KΩ)
OPD: Output Pin With Pull-Down Resistor;
(Typical Value = 75KΩ)
6.4. Pin Assignments Table (RTL8382M)
Name
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
Table 17. Pin Assignments Table (RTL8382M)
Pin No.
Type
Name
1
AI/O
AVDDH
2
AI/O
AGND
3
AP
MDIREF
4
AI/O
AVDDL
5
AI/O
RTT1
6
AI/O
RTT2
7
AI/O
AVDDH
8
AP
DVDDL
9
AI/O
DVDDH
10
AI/O
JTAG_TCK
11
AI/O
JTAG_TMS
12
AI/O
JTAG_TDO/EEPROMTYPE
13
AP
JTAG_TDI
14
AP
JTAG_TRST#
15
AI/O
DVDDL
16
AI/O
DVDDL
17
AI/O
DVDDH
18
AI/O
AVDDH
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
26
Pin No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Type
AP
AG
AO
AP
AI/O
AI/O
AP
DP
DP
I/OPU
I/OPU
I/OPD
I/OPD
I/OPU
DP
DP
DP
AP
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN
P5MDIDP
P5MDIDN
PLLVDDL
ATESTCK1
P6MDIAP
P6MDIAN
P6MDIBP
P6MDIBN
AVDDL
P6MDICP
P6MDICN
P6MDIDP
P6MDIDN
AVDDH
P7MDIAP
P7MDIAN
P7MDIBP
P7MDIBN
AVDDL
P7MDICP
P7MDICN
P7MDIDP
P7MDIDN
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
Type
AI/O
AI/O
AI/O
AI/O
AP
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AO
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
AVDDH
DVDDL
CKOUT2
SVDDL
S2TXP
S2TXN
S2RXP
S2RXN
SVDDL
S3TXN
S3TXP
S3RXN
S3RXP
SVDDH
CKOUT4
SVDDL
S4TXP
S4TXN
S4RXP
S4RXN
SVDDL
S5TXN
S5TXP
S5RXN
S5RXP
SVDDL
AVDDH_PLL
XO
XI
AVDDL_PLL
DVDDL
DVDDL
GPIO3
Pin No.
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
Type
AP
DP
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
AP
AO
AI
AP
P
P
I/OPD
GPIO2
GPIO1
GPIO0
RESET#
DVDDH
SSPI_CS#
111
112
113
114
115
116
SSPI_SO/
DIS_PHYAUTO_UP
SSPI_SI/I2C_DAT
117
IPU
I/OPD
118
I/OPU
27
I/OPD
I/OPD
I/OPD
AI
P
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
SSPI_CLK/I2C_CLK
MDC
MDIO
LED_CLK
LED_DAT
UART0_TX/REG_IF_SEL
UART0_RX
DVDDL
SPI_CS#0
SPI_SI/SIO0
SPI_SO/SIO1
SPI_CLK
DVDDH
MVDDH
DDR12_D4/DDR3_D6
DDR12_D3/DDR3_D2
DDR12_D1/DDR3_D4
DDR12_D6/DDR3_D0
DDR12_DM/DDR3_DQS
DDR3_DQS#
DVDDL
DDR12_CLK#/DDR3_CLK#
DDR12_CLK/DDR3_CLK
DDR12_DQS/DDR3_DM
VREF
DDR12_D7/DDR3_D3
DDR12_D0/DDR3_D1
DDR12_D2/DDR3_D7
DDR12_D5/DDR3_D5
DDR2_ODT/DDR3_CKE
DDR12_CS#/DDR3_BA1
DDR12_A0/DDR3_A12/
DIS_EEE
DDR12_A2/DDR3_A4/
PWRBLINK[0]
DDR12_A4/DDR3_A6/
PWRBLINK[1]
DDR12_A6/DDR3_A8/
SEL_XTAL_CLK
DDR12_A8/DDR3_A1/
SDS_PDOWN_EN
DDR3_A14/
SPI_ADDR_SEL
Pin No.
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Type
I/OPU
OPU
I/OPU
OPU
I/OPU
I/OPD
IPD
P
O
I/OPD
I/OPD
OPD
P
P
I/O
I/O
I/O
I/O
I/O
I/O
P
O
O
I/O
P
I/O
I/O
I/O
I/O
O
O
I/O
151
I/O
152
I/O
153
I/O
154
I/O
155
I/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
DDR12_A13/DDR3_A11/
LED/MODE[1]
DDR12_A11/DDR3_A10/
LED/MODE[0]
DDR12_CAS#/DDR3_RAS#
DDR12_RAS#/DDR3_CAS#
DVDDL
DDR12_WE#/DDR3_WE#
MVDDH
MVDDH
DDR12_CKE/DDR3_BA2
DDR12_BA1/DDR3_A9
DDR12_A1/DDR3_A13/
CPU_SLEEP
DDR12_A12/DDR3_A2/
DRAM_INI_EN
DDR3_RST#
DDR12_A9/DDR3_A7/
MEM_TYPE[1]
DDR12_A7/DDR3_A5/
MEM_TYPE[0]
DDR12_A5/DDR3_A0/
CLK_M_EE[1]
DDR12_A3/DDR3_A3/
CLK_M_EE[0]
DDR12_A10/DDR3_BA0/
EN_DECRYPT
DDR2_BA2/DDR3_CS#
DDR12_BA0/DDR3_ODT
DDR3_ZQ#
MVDDH
DVDDL
VX
CKOUT0
SVDDL
S0TXP
S0TXN
S0RXP
S0RXN
SVDDH
S1TXN
S1TXP
S1RXN
S1RXP
28
Pin No.
156
Type
I/O
157
I/O
158
159
160
161
162
163
164
165
166
O
O
P
O
P
P
O
O
I/O
167
I/O
168
169
O
I/O
170
I/O
171
I/O
172
I/O
173
I/O
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
O
O
I
P
P
A
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
SVDDL
DVDDL
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
Pin No.
191
192
193
194
195
196
197
198
199
200
201
202
203
204
Type
AP
P
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL
ATESTCK0
P2MDIAP
P2MDIAN
DGND
29
Pin No.
205
206
207
208
209
210
211
212
213
214
215
216
EPAD
Type
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AO
AI/O
AI/O
G
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
6.5. Pin Description (RTL8382M)
6.5.1.
1000M Ethernet PHY MDI Interface Pins
Table 18. 1000M Ethernet PHY MDI Interface Pins
Type Description
Port 0 Media Dependent Interface A~D.
AI/O
For 1000Base-T operation, differential data from the media is transmitted and
AI/O
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
AI/O
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
AI/O
Pin Name
P0MDIAP
Pin No.
194
P0MDIAN
195
P0MDIBP
196
P0MDIBN
197
P0MDICP
199
AI/O
P0MDICN
200
AI/O
P0MDIDP
201
AI/O
P0MDIDN
202
AI/O
P1MDIAP
204
AI/O
P1MDIAN
205
AI/O
P1MDIBP
206
AI/O
P1MDIBN
207
AI/O
P1MDICP
209
AI/O
P1MDICN
210
AI/O
P1MDIDP
211
AI/O
P1MDIDN
212
AI/O
P2MDIAP
215
AI/O
P2MDIAN
216
AI/O
P2MDIBP
1
AI/O
P2MDIBN
2
AI/O
P2MDICP
4
AI/O
P2MDICN
5
AI/O
P2MDIDP
6
AI/O
P2MDIDN
7
AI/O
P3MDIAP
9
AI/O
P3MDIAN
10
AI/O
P3MDIBP
11
AI/O
P3MDIBN
12
AI/O
P3MDICP
15
AI/O
P3MDICN
16
AI/O
P3MDIDP
17
AI/O
P3MDIDN
18
AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
30
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
P4MDIAP
Pin No.
37
Type
AI/O
P4MDIAN
38
AI/O
P4MDIBP
39
AI/O
P4MDIBN
40
AI/O
P4MDICP
43
AI/O
P4MDICN
44
AI/O
P4MDIDP
45
AI/O
P4MDIDN
46
AI/O
P5MDIAP
48
AI/O
P5MDIAN
49
AI/O
P5MDIBP
50
AI/O
P5MDIBN
51
AI/O
P5MDICP
53
AI/O
P5MDICN
54
AI/O
P5MDIDP
55
AI/O
P5MDIDN
56
AI/O
P6MDIAP
59
AI/O
P6MDIAN
60
AI/O
P6MDIBP
61
AI/O
P6MDIBN
62
AI/O
P6MDICP
64
AI/O
P6MDICN
65
AI/O
P6MDIDP
66
AI/O
P6MDIDN
67
AI/O
P7MDIAP
69
AI/O
P7MDIAN
70
AI/O
P7MDIBP
71
AI/O
P7MDIBN
72
AI/O
P7MDICP
74
AI/O
P7MDICN
75
AI/O
P7MDIDP
76
AI/O
P7MDIDN
77
AI/O
Description
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 5 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 6 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 7 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
31
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
6.5.2.
SGMII Interface Pins
Pin Name
S4RXP
Pin No.
96
Type
AI
S4RXN
97
AI
S4TXP
94
AO
S4TXN
95
AO
S5RXP
102
AI
S5RXN
101
AI
S5TXP
100
AO
S5TXN
99
AO
6.5.3.
SGMII Interface Transmit Data Differential Output Pair.
SGMII Interface Receive Data Differential Input Pair.
SGMII Interface Transmit Data Differential Output Pair.
RSGMII Interface Pins
Pin Name
S4RXP
Pin No.
96
Type
AI
S4RXN
97
AI
S4TXP
94
AO
S4TXN
95
AO
S5RXP
102
AI
S5RXN
101
AI
S5TXP
100
AO
S5TXN
99
AO
6.5.4.
Table 19. SGMII Interface Pins
Description
SGMII Interface Receive Data Differential Input Pair.
Table 20. RSGMII Interface Pins
Description
RSGMII Interface Receive Data Differential Input Pair.
RSGMII Interface Transmit Data Differential Output Pair.
RSGMII Interface Receive Data Differential Input Pair.
RSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Pins
Pin Name
S0RXP
Pin No.
184
Type
AI
S0RXN
185
AI
S0TXP
182
AO
S0TXN
183
AO
S1RXP
190
AI
S1RXN
189
AI
S1TXP
188
AO
S1TXN
187
AO
S2RXP
84
AI
S2RXN
85
AI
Table 21. QSGMII Interface Pins
Description
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
32
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
S2TXP
Pin No.
82
Type
AO
S2TXN
83
AO
S3RXP
90
AI
S3RXN
89
AI
S3TXP
88
AO
S3TXN
87
AO
S4RXP
96
AI
S4RXN
97
AI
S4TXP
94
AO
S4TXN
95
AO
6.5.5.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
1000Base-X/100Base-FX Interface Pins
Table 22. 1000Base-X/100Base-FX Interface Pins
Type
Description
1000Base-X/100Base-FX
Interface Receive Data Differential Input Pair.
AI
Pin Name
S4RXP
Pin No.
96
S4RXN
97
AI
S4TXP
94
AO
S4TXN
95
AO
S5RXP
102
AI
S5RXN
101
AI
S5TXP
100
AO
S5TXN
99
AO
6.5.6.
Description
QSGMII Interface Transmit Data Differential Output Pair.
1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
DDR1/2 SDRAM Interface Pins
Table 23. DDR1/2 SDRAM Interface Pins
Pin Name
DDR12_D[7:0]
DDR12_A[13:0]
DDR2_BA[2]
DDR12_BA[1:0]
DDR12_WE#
DDR12_CKE
DDR12_RAS#
DDR12_CAS#
DDR12_CS#0
Pin No.
144, 136, 147, 133,
134, 146, 135, 145
156, 167, 157, 173,
169, 154, 170, 153,
171, 152, 172, 151,
166, 150
174
165, 175
161
164
159
158
149
Type
I/O
Drive (mA) Description
8
DDR SDRAM Data Bus.
I/O
8
DDR SDRAM Address Select.
O
O
O
O
O
O
O
8
8
8
8
8
8
8
DDR SDRAM Bank Address Select.
DDR SDRAM Bank Address Select.
DDR SDRAM Write Enable.
DDR SDRAM Clock Enable.
DDR SDRAM Row Address Strobe.
DDR SDRAM Column Address Strobe.
DDR SDRAM Chip Select 0.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
33
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
DDR2_ODT
DDR12_DQS
DDR12_CLK
Pin No.
148
142
141
Type
O
I/O
O
Drive (mA)
8
8
8
DDR12_CLK#
140
O
8
6.5.7.
Description
DDR SDRAM On-Die Termination.
DDR SDRAM Data Strobe.
DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.
DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.
DDR3 SDRAM Interface Pins
Table 24. DDR3 SDRAM Interface Pins
Pin Name
DDR3_D[7:0]
DDR3_A[14]
DDR3_A[13:10]
DDR3_A[9]
DDR3_A[8:0]
DDR3_DQS#
DDR3_DQS
DDR3_CLK#
DDR3_CLK
DDR3_DM
DDR3_CKE
DDR3_BA[2:1]
DDR3_BA[0]
DDR3_RAS#
DDR3_CAS#
DDR3_WE#
DDR3_RST#
DDR3_CS#
DDR3_ODT
DDR3_ZQ#
Pin No.
146, 133, 147, 135,
144, 134, 145, 136
155
166, 150,156, 157
165
153, 169, 152, 170,
151, 172, 167, 154,
171
138
137
140
141
142
148
164, 149
173
158
159
161
168
174
175
176
Type
I/O
Drive (mA) Description
8
DDR SDRAM Data Bus.
O
I/O
O
I/O
8
8
8
8
DDR SDRAM Address Select.
DDR SDRAM Address Select.
DDR SDRAM Address Select.
DDR SDRAM Address Select.
I/O
I/O
O
O
I/O
O
O
I/O
O
O
O
O
O
O
I
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
DDR SDRAM Data Strobe.
DDR SDRAM Data Strobe.
DDR SDRAM Clock.
DDR SDRAM Clock.
DDR SDRAM Data Mask.
DDR SDRAM Clock Enable.
DDR SDRAM Bank Address Select.
DDR SDRAM Bank Address Select.
DDR SDRAM Row Address Strobe.
DDR SDRAM Column Address Strobe.
DDR SDRAM Write Enable.
DDR SDRAM Reset.
DDR SDRAM Chip Select.
DDR SDRAM On-Die Termination.
DDR SDRAM External Reference Ball for Output
Drive Calibration.
This ball is tied to an external 240 Ohm resistor, which
is tied to GND.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
34
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
6.5.8.
Master Mode-SPI Flash Interface Pins
Pin Name
SPI_CLK
SPI_SO/SIO1
Pin No.
130
129
SPI_SI/SIO0
128
SPI_CS#0
127
6.5.9.
Table 25. Master Mode-SPI Flash Interface Pins
Type
Drive (mA) Description
OPD
12
Serial Clock Output Pin.
I/OPD
12
In Serial Mode: This is a flash chip output pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is MSB first.
I/OPD
12
In Serial Mode: This is a flash chip input pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is LSB first.
O
12
Chip Select Output Pin.
Slave Transmit Enable and active low.
UART Interface Pins
Pin Name
UART0_RX
Pin No.
125
Type
IPD
UART0_TX
UART1_RX
UART1_TX
124
116
117
I/OPD
IPU
I/OPD
Table 26. UART Interface Pins
Drive (mA) Description
4
UART0 Interface Receive Data.
4
4
4
UART0 Interface Transmit Data.
UART1 Interface Receive Data.
UART1 Interface Transmit Data.
6.5.10. LED Interface Pins
Pin Name
LED_CLK
Pin No.
122
Type
OPU
LED_DAT
123
I/OPU
Table 27. LED Interface Pins
Drive (mA) Description
12
(1) In Serial LED Mode
Reference output clock for serial LED interface and Data is
latched on the rising of LEDCK.
(2) In SMI-like LED Mode
Reference output clock for I2C-like interface.
12
(1) In Serial LED Mode
Serial bit stream of link status information.
(2) In I2C-like LED Mode
The data written to the LED IC.
6.5.11. GPIO Interface Pins
Pin Name
Pin No.
GPIO0
113
GPIO[3:1]
110, 111, 112
Table 28. GPIO Interface Pins
Type
Drive (mA) Description
This pin default set as system led.
I/OPD
12
By the configuration, it can be set as General
Purpose Input/Output Pin.
I/OPD
12
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
General Purpose Input/Output Pins.
35
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
Pin No.
Type
Drive (mA)
Description
GPO10
30
I/OPD
4
General Purpose Output Pins.
GPIO11
31
I/OPD
4
General Purpose Input/Output Pins.
GPIO[14:12]
32,28,29
I/OPU
4
General Purpose Input/Output Pins.
6.5.12. EJTAG Interface Pins
Pin Name
JTAG_TMS
JTAG_TCK
JTAG_TRST#
JTAG_TDI
JTAG_TDO
Pin No.
29
28
32
31
30
Type
I/OPU
I/OPU
I/OPU
I/OPD
I/OPD
Table 29. EJTAG Interface Pins
Drive (mA) Description
4
JTAG Test Mode Select.
4
JTAG Test Clock Input.
4
JTAG Test Reset.
4
JTAG Test Data Input.
4
JTAG Test Data Output.
6.5.13. Configuration Strapping Pins
Pin Name
EEPROMTYPE
DIS_PHYAUTO_UP
REG_IF_SEL
DIS_EEE
PWRBLINK[1:0]
SEL_XTAL_CLK
SDS_PDOWN_EN
SPI_ADDR_SEL
LED_MODE[1:0]
Table 30. Configuration Strapping Pins
Pin No. Description
30
Select EEPROM Address Byte Size.
0b0: 1-byte
0b1: 2-byte
117
Disable Asic auto power up PHY：
0b0: enable asic auto power up phy;
0b1: disable asic auto power up phy.
124
Select Switch Core Register Access Interface.
0b0: I2C
0b1: SPI slave
150
Disable 1000M EEE and 100M EEE Function.
0b0: Enable
0b1: Disable
152, 151 Select LED Power On Blinking Timer.
0b00: Disable
0b01: 800ms
0b10: 1.6s
0b11: 3.2s
153
Select XTAL Input is 25M or 125M.
0b0: 25M
0b1:125M
Note: This option is only for sync Ethernet.
154
Enable SerDes Power Down Mode.
0b0: SerDes4/5 operate in normal mode
0b1: SerDes4/5 operate in power down mode
155
Select address mode for SPI flash:
0b0: 3Bytes address;
0b1: 4Bytes address.
156, 157 Select LED Mode.
0b00: Serial LED mode
0b01: Scan Single mode
0b10: Scan Bicolor mode
0b11: Disable LED
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
36
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
CPU_SLEEP
DRAM_INI_EN
MEM_TYPE[1:0]
CLK_M_EE[1:0]
Pin No. Description
166
Enable CPU function；
0b0: CPU is always under reset state;
0b1: CPU is enabled.
167
Enable DRAM Initialization Procedure.
0b0: Enable DRAM Initialization procedure
0b1: Bypass DRAM Initialization procedure
169, 170 Select Memory Type for SOC.
0b00: Select SPI flash + DDR-3
0b01: Select SPI flash + DDR-2
0b10: Select SPI flash + DDR-1
0b11: Select EEPROM
171, 172 When MEM_TYPE Select is SPI Flash:
This Strapping Pin Selects the Initial Clock for The Memory Controller.
For DDR2:
0b00: Reserved for test;
0b01: Reserved for test;
0b10: 100MHz
0b11: Reserved for test.
For DDR3:
0b00: Reserved for test;
0b01: Reserved for test;
0b10: 125MHz;
0b11: Reserved for test.
Note: The initial value for this strapping pin must set as the reference
design guide recommend.
EN_DECRYPT
173
When MEM_TYPE Select is EEPROM:
CLK_M_EE[0] is used to select SOC EEPROM address byte size.
0b0: 1-byte address
0b1: 2-byte address
Enable or Disable Decrypt for Flash.
0b0: Disable decrypt
0b1: Enable decrypt
6.5.14. Miscellaneous Interface Pins
Pin Name
MDC
MDIO
SSPI_CLK/I2C_CLK
Pin No.
120
121
119
SSPI_SI/I2C_DAT
118
SSPI_SO
SSPI_CS#
RESET#
117
116
114
XI
XO
106
105
Table 31. Miscellaneous Interface Pins
Type Drive (mA) Description
OPU
12
MII Management Interface Clock Pin.
I/OPU
12
MII Management Interface Data Pin.
I/OPU
4
SPI Serial Clock Input (Slave Mode).
I2C Interface Clock Input (Slave Mode).
I2C Interface Clock Output (Master Mode).
I/OPU
4
SPI Serial Data Input (Slave Mode).
I2C Interface Bi-Directional data (Slave Mode).
I/OPD
4
SPI Serial Data Output (Slave Mode).
OUP
4
SPI Serial Chip Select (Slave Mode).
AI
System Pin Reset Input (Low Active).
To complete the reset function, this pin must be asserted
for at least 10ms. It must be pulled up for normal
operation.
AI
25MHz Crystal Clock Input and Feedback Pin.
AO
25MHz Crystal Clock Output Pin.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
37
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
MDIREF
Pin No.
21
Type
AO
RTT1
RTT2
VX
CKOUT0
CKOUT2
CKOUT4
ATESTCK[1:0]
23
24
179
180
80
92
58, 214
AI/O
AI/O
A
AO
AO
AO
AO
Drive (mA) Description
MDI Bias Resistor.
Adjust the reference current for all PHYs. This pin must
connect to AGND via a 2.49k ohm resistor.
Reserved for Internal Use (Must be Left Floating).
Reserved for Internal Use (Must be Left Floating).
Low Voltage Power Control Resistor.
8
25MHz Clock Output.
8
25MHz Clock Output.
8
25MHz Clock Output.
Reserved for Internal Use (Must be Left Floating).
6.5.15. Power and GND Pins
Pin Name
AVDDL
PLLVDDL
AVDDH
DVDDL
DVDDH
SVDDL
AVDDL_PLL
SVDDH
AVDDH_PLL
MVDDH
VREF
AGND
DGND
Table 32. Power and GND Pins
Pin No.
Type
Description
AP
Analog Low Voltage Power.
3, 13, 22, 42, 52, 63,
73, 198, 208
57, 213
AP
Analog PLL Low Voltage Power.
AP
Analog High Voltage Power.
8, 14, 19, 25, 36, 41,
47, 68, 78, 193, 203
P
Digital Low Voltage Power.
26, 33, 34, 79, 108,
109, 126, 139, 160,
178, 192
27, 35, 115, 131
P
Digital High Voltage Power.
AP
SerDes Low Voltage Power.
81, 86, 93, 98, 103,
181, 191
107
AP
PLL Low Voltage Power.
91, 186
AP
SerDes High Voltage Power.
104
AP
PLL High Voltage Power.
132, 162, 163,177
P
SDRAM High Voltage Power.
143
P
SSTL Reference Voltage (MVDDH/2).
20
AG
Analog Ground.
E-PAD
G
Digital Ground.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
38
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
7.
Pin Assignments and Description (RTL8382L)
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDDIO
RESERVED
DVDDL
RESERVED
RESERVED
LED_MODE[0]
LED_MODE[1]
SPI_ADDR_SEL
SDS_PDOWN_EN
SEL_XTAL_CLK
PWRBLINK[1]
PWRBLINK[0]
DIS_EEE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DVDDL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VDDIO
DVDDH
SPI_CLK
SPI_SO/SIO1
SPI_SI/SIO0
SPI_CS#0
DVDDL
UART0_RX
UART0_TX/REG_IF_SEL
LED_DAT
LED_CLK
MDIO
MDC
SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
SSPI_SO/DIS_PHYAUTO_UP
SSPI_CS#
DVDDH
RESET#
GPIO0
GPIO1
GPIO2
GPIO3
DVDDL
7.1. Pin Assignments Figure (RTL8382L)
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
RTL8382L
LLLLLLL
TXXXX TAIWAN
DVDDL
AVDDL_PLL
XI
XO
AVDDH_PLL
SVDDL
S5RXP
S5RXN
S5TXP
S5TXN
SVDDL
S4RXN
S4RXP
S4TXN
S4TXP
SVDDL
CKOUT4
SVDDH
S3RXP
S3RXN
S3TXP
S3TXN
SVDDL
S2RXN
S2RXP
S2TXN
S2TXP
SVDDL
CKOUT2
DVDDL
AVDDH
P7MDIDN
P7MDIDP
P7MDICN
P7MDICP
AVDDL
P7MDIBN
P7MDIBP
P7MDIAN
P7MDIAP
AVDDH
P6MDIDN
P6MDIDP
P6MDICN
P6MDICP
AVDDL
P6MDIBN
P6MDIBP
P6MDIAN
P6MDIAP
ATESTCK1
PLLVDDL
P5MDIDN
P5MDIDP
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
DVDDL
DVDDH
RESERVED
RESERVED
EEPROMTYPE
RESERVED
RESERVED
DVDDL
DVDDL
DVDDH
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
VDDIO
RESERVED
RESERVED
CPU_SLEEP
RESERVED
RESERVED
MEM_TYPE[1]
MEM_TYPE[0]
CLK_M_EE[1]
CLK_M_EE[0]
EN_DECRYPT
RESERVED
RESERVED
RESERVED
VDDIO
DVDDL
VX
CKOUT0
SVDDL
S0TXP
S0TXN
S0RXP
S0RXN
SVDDH
S1TXN
S1TXP
S1RXN
S1RXP
SVDDL
DVDDL
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL
ATESTCK0
P2MDIAP
P2MDIAN
Figure 10. Pin Assignments (RTL8382L)
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
39
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
7.2. Package Identification
Green package is indicated by a ‘G’ in ‘GXXXX’ (Figure 10).
7.3. Pin Assignments Table Codes (RTL8382L)
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
(Typical Value = 75KΩ)
IPD: Input Pin With Pull-Down Resistor;
(Typical Value = 75KΩ)
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75KΩ)
OPD: Output Pin With Pull-Down Resistor;
(Typical Value = 75KΩ)
7.4. Pin Assignments Table (RTL8382L)
Name
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
P3MDICP
Table 33. Pin Assignments Table (RTL8382L)
Pin No.
Type
Name
1
AI/O
P3MDICN
2
AI/O
P3MDIDP
3
AP
P3MDIDN
4
AI/O
AVDDH
5
AI/O
AGND
6
AI/O
MDIREF
7
AI/O
AVDDL
8
AP
RTT1
9
AI/O
RTT2
10
AI/O
AVDDH
11
AI/O
DVDDL
12
AI/O
DVDDH
13
AP
RESERVED
14
AP
RESERVED
15
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
40
Pin No.
16
17
18
19
20
21
22
23
24
25
26
27
28
Type
AI/O
AI/O
AI/O
AP
AG
AO
AP
AI/O
AI/O
AP
DP
DP
-
29
-
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
EEPROMTYPE
Pin No.
30
Type
IPD
RESERVED
31
-
RESERVED
32
-
DVDDL
DVDDL
DVDDH
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN
P5MDIDP
P5MDIDN
PLLVDDL
ATESTCK1
P6MDIAP
P6MDIAN
P6MDIBP
P6MDIBN
AVDDL
P6MDICP
P6MDICN
P6MDIDP
P6MDIDN
AVDDH
P7MDIAP
P7MDIAN
P7MDIBP
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
DP
DP
DP
AP
AI/O
AI/O
AI/O
AI/O
AP
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AO
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
P7MDIBN
AVDDL
P7MDICP
P7MDICN
P7MDIDP
P7MDIDN
AVDDH
DVDDL
CKOUT2
SVDDL
S2TXP
S2TXN
S2RXP
S2RXN
SVDDL
S3TXN
S3TXP
S3RXN
S3RXP
SVDDH
CKOUT4
SVDDL
S4TXP
S4TXN
S4RXP
S4RXN
SVDDL
S5TXN
S5TXP
S5RXN
S5RXP
SVDDL
AVDDH_PLL
XO
XI
AVDDL_PLL
DVDDL
DVDDL
GPIO3
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
I/OPD
GPIO2
111
I/OPD
GPIO1
112
I/OPD
GPIO0
113
I/OPD
41
Track ID:
Type
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
DP
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
AP
AO
AI
AP
P
P
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
RESET#
DVDDH
SSPI_CS#
Pin No.
114
115
116
Type
AI
P
Name
SPI_ADDR_SEL
LED/MODE[1]
SSPI_SO/DIS_PHYAUTO_UP
117
IPU
I/OPD
SSPI_SI/I2C_DAT
118
I/OPU
SSPI_CLK/I2C_CLK
119
I/OPU
MDC
120
MDIO
121
OPU
I/OPU
LED_CLK
122
LED_DAT
123
OPU
I/OPU
UART0_TX/REG_IF_SEL
124
I/OPD
UART0_RX
125
IPD
DVDDL
SPI_CS#0
SPI_SI/SIO0
126
127
128
P
O
I/OPD
SPI_SO/SIO1
129
I/OPD
SPI_CLK
130
OPD
DVDDH
VDDIO
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DVDDL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DIS_EEE
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
P
P
I/O
I/O
I/O
I/O
I/O
I/O
P
O
O
I/O
P
I/O
I/O
I/O
I/O
O
O
I
PWRBLINK[0]
151
I
PWRBLINK[1]
152
I
SEL_XTAL_CLK
153
I
SDS_PDOWN_EN
154
I
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Pin No.
155
156
Type
I
I
LED/MODE[0]
157
I
RESERVED
RESERVED
DVDDL
RESERVED
VDDIO
VDDIO
RESERVED
RESERVED
CPU_SLEEP
158
159
160
161
162
163
164
165
166
P
P
P
I/OPD
RESERVED
RESERVED
MEM_TYPE[1]
167
168
169
I/OPD
MEM_TYPE[0]
170
I/OPD
CLK_M_EE[1]
171
I/OPD
CLK_M_EE[0]
172
I/OPD
EN_DECRYPT
173
I/OPD
RESERVED
RESERVED
RESERVED
VDDIO
DVDDL
VX
CKOUT0
SVDDL
S0TXP
S0TXN
S0RXP
S0RXN
SVDDH
S1TXN
S1TXP
S1RXN
S1RXP
SVDDL
DVDDL
AVDDH
P0MDIAP
P0MDIAN
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
P
P
A
AO
AP
AO
AO
AI
AI
AP
AO
AO
AI
AI
AP
P
AP
AI/O
AI/O
42
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RTL8380M/RTL8382M/RTL8382L
Datasheet
Name
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
Pin No.
196
197
198
199
200
201
202
203
204
205
206
Type
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
Name
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
PLLVDDL
ATESTCK0
P2MDIAP
P2MDIAN
DGND
43
Pin No.
207
208
209
210
211
212
213
214
215
216
EPAD
Track ID:
Type
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AO
AI/O
AI/O
G
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
7.5. Pin Descriptions (RTL8382L)
7.5.1.
1000M Ethernet PHY MDI Interface Pins
Table 34. 1000M Ethernet PHY MDI Interface Pins
Type Description
Port 0 Media Dependent Interface A~D.
AI/O
For 1000Base-T operation, differential data from the media is transmitted and
AI/O
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
AI/O
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
AI/O
Pin Name
P0MDIAP
Pin No.
194
P0MDIAN
195
P0MDIBP
196
P0MDIBN
197
P0MDICP
199
AI/O
P0MDICN
200
AI/O
P0MDIDP
201
AI/O
P0MDIDN
202
AI/O
P1MDIAP
204
AI/O
P1MDIAN
205
AI/O
P1MDIBP
206
AI/O
P1MDIBN
207
AI/O
P1MDICP
209
AI/O
P1MDICN
210
AI/O
P1MDIDP
211
AI/O
P1MDIDN
212
AI/O
P2MDIAP
215
AI/O
P2MDIAN
216
AI/O
P2MDIBP
1
AI/O
P2MDIBN
2
AI/O
P2MDICP
4
AI/O
P2MDICN
5
AI/O
P2MDIDP
6
AI/O
P2MDIDN
7
AI/O
P3MDIAP
9
AI/O
P3MDIAN
10
AI/O
P3MDIBP
11
AI/O
P3MDIBN
12
AI/O
P3MDICP
15
AI/O
P3MDICN
16
AI/O
P3MDIDP
17
AI/O
P3MDIDN
18
AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
44
Track ID:
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Datasheet
Pin Name
P4MDIAP
Pin No.
37
Type
AI/O
P4MDIAN
38
AI/O
P4MDIBP
39
AI/O
P4MDIBN
40
AI/O
P4MDICP
43
AI/O
P4MDICN
44
AI/O
P4MDIDP
45
AI/O
P4MDIDN
46
AI/O
P5MDIAP
48
AI/O
P5MDIAN
49
AI/O
P5MDIBP
50
AI/O
P5MDIBN
51
AI/O
P5MDICP
53
AI/O
P5MDICN
54
AI/O
P5MDIDP
55
AI/O
P5MDIDN
56
AI/O
P6MDIAP
59
AI/O
P6MDIAN
60
AI/O
P6MDIBP
61
AI/O
P6MDIBN
62
AI/O
P6MDICP
64
AI/O
P6MDICN
65
AI/O
P6MDIDP
66
AI/O
P6MDIDN
67
AI/O
P7MDIAP
69
AI/O
P7MDIAN
70
AI/O
P7MDIBP
71
AI/O
P7MDIBN
72
AI/O
P7MDICP
74
AI/O
P7MDICN
75
AI/O
P7MDIDP
76
AI/O
P7MDIDN
77
AI/O
Description
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 5 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 6 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
Port 7 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100 ohm termination resistor.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
45
Track ID:
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RTL8380M/RTL8382M/RTL8382L
Datasheet
7.5.2.
SGMII Interface Pins
Pin Name
Pin No.
Type
S4RXP
96
AI
S4RXN
97
AI
S4TXP
94
AO
S4TXN
95
AO
S5RXP
102
AI
S5RXN
101
AI
S5TXP
100
AO
S5TXN
99
AO
7.5.3.
SGMII Interface Transmit Data Differential Output Pair.
SGMII Interface Receive Data Differential Input Pair.
SGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Pins
Pin Name
Pin No.
Type
S0RXP
184
AI
S0RXN
185
AI
S0TXP
182
AO
S0TXN
183
AO
S1RXP
190
AI
S1RXN
189
AI
S1TXP
188
AO
S1TXN
187
AO
S2RXP
84
AI
S2RXN
85
AI
S2TXP
82
AO
S2TXN
83
AO
S3RXP
90
AI
S3RXN
89
AI
S3TXP
88
AO
S3TXN
87
AO
7.5.4.
Table 35. SGMII Interface Pins
Description
SGMII Interface Receive Data Differential Input Pair.
Table 36. QSGMII Interface Pins
Description
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
QSGMII Interface Receive Data Differential Input Pair.
QSGMII Interface Transmit Data Differential Output Pair.
1000Base-X/100Base-FX Interface Pins
Pin Name
Pin No.
S4RXP
96
S4RXN
97
Table 37. 1000Base-X/100Base-FX Interface Pins
Type
Description
1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
AI
AI
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
46
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
Pin No.
Type
S4TXP
94
AO
S4TXN
95
AO
S5RXP
102
AI
S5RXN
101
AI
S5TXP
100
AO
S5TXN
99
AO
7.5.5.
Pin No.
130
129
SPI_SI/SIO0
128
SPI_CS#0
127
1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
Table 38. Master Mode-SPI Flash Interface Pins
Type
Drive (mA) Description
OPD
12
Serial Clock Output Pin.
I/OPD
12
In Serial Mode: This is a flash chip output pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is MSB first.
I/OPD
12
In Serial Mode: This is a flash chip input pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is LSB first.
O
12
Chip Select Output Pin.
Slave Transmit Enable and active low.
UART Interface Pins
Pin Name
UART0_RX
Pin No.
125
Type
IPD
UART0_TX
UART1_RX
124
116
UART1_TX
117
I/OPD
IPU
I/OPD
7.5.7.
1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
Master Mode-SPI Flash Interface Pins
Pin Name
SPI_CLK
SPI_SO/SIO1
7.5.6.
Description
1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
Table 39. UART Interface Pins
Drive (mA) Description
4
UART0 Interface Receive Data.
4
4
UART0 Interface Transmit Data.
UART1 Interface Receive Data.
4
UART1 Interface Transmit Data.
LED Interface Pins
Pin Name
LED_CLK
Pin No.
122
Type
OPU
LED_DAT
123
I/OPU
Table 40. LED Interface Pins
Drive (mA) Description
12
(1) In Serial LED Mode
Reference output clock for serial LED interface and Data is
latched on the rising of LEDCK.
(2) In SMI-like LED Mode
Reference output clock for I2C-like interface.
12
(1) In Serial LED Mode
Serial bit stream of link status information.
(2) In I2C-like LED Mode
The data written to the LED IC.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
47
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
7.5.8.
GPIO Interface Pins
Pin Name
Pin No.
GPIO0
113
GPIO[3:1]
110, 111, 112
7.5.9.
Table 41. GPIO Interface Pins
Type
Drive (mA) Description
This pin default set as system led.
I/OPD
12
By the configuration, it can be set as General
Purpose Input/Output Pin.
I/OPD
12
General Purpose Input/Output Pins.
Configuration Strapping Pins
Pin Name
EEPROMTYPE
REG_IF_SEL
DIS_PHYAUTO_UP
DIS_EEE
PWRBLINK[1:0]
SEL_XTAL_CLK
SDS_PDOWN_EN
SPI_ADDR_SEL
LED_MODE[1:0]
CPU_SLEEP
MEM_TYPE[1:0]
Table 42. Configuration Strapping Pins
Pin No. Description
30
Select EEPROM Address Byte Size.
0b0: 1-byte
0b1: 2-byte
124
Select Switch Core Register Access Interface.
0b0: I2C
0b1: SPI slave
117
Disable Asic auto power up PHY：
0b0: enable asic auto power up phy;
0b1: disable asic auto power up phy.
150
Disable 1000M EEE and 100M EEE Function.
0b0: Enable
0b1: Disable
152, 151 Select LED Power On Blinking Timer.
0b00: Disable
0b01: 800ms
0b10: 1.6s
0b11: 3.2s
153
Select XTAL Input is 25M or 125M.
0b0: 25M
0b1:125M
Note: This option is only for sync Ethernet.
154
Enable SerDes Power Down Mode.
0b0: SerDes4/5 operate in normal mode
0b1: SerDes4/5 operate in power down mode
155
Select address mode for SPI flash:
0b0: 3Bytes address;
0b1: 4Bytes address.
156, 157 Select LED Mode.
0b00: Serial LED mode
0b01: Scan Single mode
0b10: Scan Bicolor mode
0b11: Disable LED
166
Enable CPU function；
0b0: CPU is always under reset state;
0b1: CPU is enabled.
169, 170 Select Memory Type for SOC.
0b00: Select SPI flash
0b01: Reserved
0b10: Select SPI flash
0b11: Select EEPROM
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
48
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
CLK_M_EE[1:0]
Pin No.
171, 172
Description
When MEM_TYPE Select is SPI Flash:
This Strapping Pin Selects the Initial Clock for The Memory Controller.
0b00: Reserved for test;
0b01: Reserved for test;
0b10: 100MHz
0b11: Reserved for test.
Note: The initial value for this strapping pin must set as the reference
design guide recommend.
EN_DECRYPT
173
When MEM_TYPE Select is EEPROM:
CLK_M_EE[0] is used to select SOC EEPROM address byte size.
0b0: 1-byte address
0b1: 2-byte address
Enable or Disable Decrypt for Flash.
0b0: Disable decrypt
0b1: Enable decrypt
7.5.10. Miscellaneous Interface Pins
Pin Name
MDC
MDIO
SSPI_CLK/I2C_CLK
Pin No.
120
121
119
SSPI_SI/I2C_DAT
118
SSPI_SO
SSPI_CS#
RESET#
117
116
114
XI
XO
MDIREF
106
105
21
RTT1
RTT2
VX
CKOUT0
CKOUT2
CKOUT4
ATESTCK[1:0]
23
24
179
180
80
92
58, 214
Table 43. Miscellaneous Interface Pins
Type Drive (mA) Description
OPU
12
MII Management Interface Clock Pin.
I/OPU
12
MII Management Interface Data Pin.
I/OPU
4
SPI Serial Clock Input (Slave Mode).
I2C Interface Clock Input (Slave Mode).
I2C Interface Clock Output (Master Mode).
I/OPU
4
SPI Serial Data Input (Slave Mode).
I2C Interface Bi-Directional data (Slave Mode).
I/OPD
4
SPI Serial Data Output (Slave Mode).
OUP
4
SPI Serial Chip Select (Slave Mode).
AI
System Pin Reset Input (Low Active).
To complete the reset function, this pin must be asserted
for at least 10ms. It must be pulled up for normal
operation.
AI
25MHz Crystal Clock Input and Feedback Pin.
AO
25MHz Crystal Clock Output Pin.
AO
MDI Bias Resistor.
Adjust the reference current for all PHYs. This pin must
connect to AGND via a 2.49k ohm resistor.
AI/O
Reserved for Internal Use (Must be Left Floating).
AI/O
Reserved for Internal Use (Must be Left Floating).
A
Low Voltage Power Control Resistor.
AO
8
25MHz Clock Output.
AO
8
25MHz Clock Output.
AO
8
25MHz Clock Output.
AO
Reserved for Internal Use (Must be Left Floating).
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
49
Track ID:
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RTL8380M/RTL8382M/RTL8382L
Datasheet
Pin Name
RESERVED
Pin No.
Type
28, 29, 31,
32,133, 134,
135, 136, 137,
138, 140, 141,
142, 143, 144,
145, 146, 147,
148, 149, 158,
159, 161, 164,
165, 167, 168,
174, 175, 176
Drive (mA) Description
Not Connected (Must be Left Floating).
7.5.11. Power and GND Pins
Pin Name
AVDDL
PLLVDDL
AVDDH
DVDDL
DVDDH
SVDDL
AVDDL_PLL
SVDDH
AVDDH_PLL
VDDIO
AGND
DGND
Table 44. Power and GND Pins
Pin No.
Type
Description
AP
Analog Low Voltage Power.
3, 13, 22, 42, 52, 63,
73, 198, 208
57, 213
AP
Analog PLL Low Voltage Power.
AP
Analog High Voltage Power.
8, 14, 19, 25, 36, 41,
47, 68, 78, 193, 203
P
Digital Low Voltage Power.
26, 33, 34, 79, 108,
109, 126, 139, 160,
178, 192
27, 35, 115, 131
P
Digital High Voltage Power.
AP
SerDes Low Voltage Power.
81, 86, 93, 98, 103,
181, 191
107
AP
PLL Low Voltage Power.
91, 186
AP
SerDes High Voltage Power.
104
AP
PLL High Voltage Power.
132, 162, 163,177
P
Strapping pin IO Voltage Power.
20
AG
Analog Ground.
E-PAD
G
Digital Ground.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
50
Track ID:
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RTL8380M/RTL8382M/RTL8382L
Datasheet
8.
Switch Function Description
8.1. Hardware Reset and Software Reset
8.1.1.
Hardware Reset
A hardware reset forces the RTL8380M/RTL8382M/RTL8382L to start the initial power-on sequence.
First hardware will strap pins to give all default values when the ‘RESET’ signal terminates. Next the
complete SRAM BIST (Built-In Self Test) process is run. Finally the packet buffer descriptors are
initialized and internal registers and external CPU will access them.
8.1.2.
Software Reset
The RTL8380M/RTL8382M/RTL8382L supports software
Switch NIC reset. Reset sources ar
•
CPU&Memory Reset: Resets MIPS 4KEc +
•
Switch NIC Reset: Resets the NIC interface between the CPU and Switch
8.2. Crystal
The RTL8380M/RTL8382M/RTL8382L clock input frequenc
a loading capacitor from XI and XO to ground. The
cycle should range from 40%~60%.
8.3. IEEE 802.3az Energy Efficient Ethernet (EEE)
The RTL8380M/RTL8382M/RTL8382L supports IEEE 802.3az Energy Efficient Ethernet (EEE) for
100Base-TX in full duplex operation, and supports 10Base-Te for 10Base-T in full/half duplex. The
Energy Efficient Ethernet (EEE) operational mode combines the IEEE 802.3 Media Access Control
(MAC) Sub-layer with a family of Physical Layers defined to support operation in Low Power Idle (LPI)
Mode. When Low Power Idle Mode is enabled, systems on both sides of the link can disable portions of
the functionality and save power during periods of low link utilization.
The RTL8380M/RTL8382M/RTL8382L EEE operational mode supports IEEE 802.3 MAC operation at
100Mbps. For 100Mbps operation, the 100Base-TX PHY is supported. In addition, the
RTL8380M/RTL8382M/RTL8382L supports a 10Mbps PHY with reduced transmit amplitude
requirements in EEE operational mode. This new PHY is fully interoperable with legacy 10Base-T PHYs
over 100m of Class-D (Category 5) or better cabling.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
51
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Datasheet
8.4. Layer 2 Learning and Forwarding
The RTL8380M/RTL8382M/RTL8382L has a 4K-entry VLAN table and provides a 64-entry filtering
database.
The RTL8380M/RTL8382M/RTL8382L supports IVL (Individual VLAN Learning) and SVL (Shared
VLAN learning) mode. The mode used depends on the FID (Filtering Identifier) setting.
8.4.1.
Forwarding
IP multicast data packets involve multicast group table lookup and forwarding operations. If the table
lookup returns a hit, the data packet is forwarded to all member ports and router ports. If the multicast
address is not stored in the address table (i.e., lookup miss), the packet is broadcast to all ports of the
broadcast domain. The VLAN Frame Forwarding Rules are defined as follows:
•
The received broadcast/multicast frame will flood to VLAN member ports only, except for the source
port
•
The received unicast frame will be forwarded to its destination port only if the destination port is in
the same VLAN as the source port. If the destination port belongs to a different VLAN, the frame will
be discarded
8.4.2.
Learning
The RTL8380M/RTL8382M/RTL8382L features a Layer 2 table (8K entries) that uses a 4-way hash
structure to store L2 entries. Each entry can be recorded in three formats, L2 Unicast, L2 Multicast, and
IP Multicast.
The L2 Unicast hash key is {MAC(48bits), FID/VID(12bits)}; the Multicast hash key is {MAC(48bits),
FID/VID(12bits)}; the IP Multicast hash key is {MAC(48bits), FID/VID(12bits)}, {GIP(32bits),
SIP(32bits)} or {0(16bits)+GIP(32bits), FID/VID(12bits)}.
8.4.3.
DA/SA Block
First bit transmitted:
0 = Unicast Destination
1= Multicast Destination
Destination Address
Second bit transmitted:
0= Globally Administered
1= Locally Administered
First byte
Second byte
Third byte
Fourth byte
Fifth byte
Sixth byte
First byte
Second byte
Third byte
Fourth byte
Fifth byte
Sixth byte
Second bit transmitted:
0= Globally Administered
1= Locally Administered
Source Address
First bit transmitted-Routing Information Indicator (RII)
0=Routing Information Not Present (Not Source Routed)
1=Routing Information Present (Source Routed)
Figure 11. DA/SA Block
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While a frame may be sent to either a unicast or a multicast destination, frames are always sent from an
individual station. The first bit of the Destination Address shows unicast or multicast. When used in its
originally intended manner, the first bit of a Source Address should always be 0, indicating an individual
sending station.
The RTL8380M/RTL8382M/RTL8382L features DA blocking, SA blocking, or DA and SA blocking
function through the Address Hash Table setting.
8.5. Port Isolation
The RTL8380M/RTL8382M/RTL8382L supports the Port Isolation feature. We can control whether the
hosts communicate with each other or not by controlling a register value.
If we set the register to cut the connection between hosts, all packets from a host cannot be transmitted to
another host directly. These packets can only be transmitted by passing through the router. This feature is
called ‘Port Isolation’. In Figure 12, Host A and host B connect to the port0 and port3 of the switch,
respectively, and port7 is a router. If we set the port isolation enable bit of port0 and port3 to 1, all
packets between A and B need to pass through the router (in both directions, A to B and B to A).
Figure 12. Port Isolation Example
Each port has its own port mask configuration (19 bits in total for the RTL8380M, 29 bits for
RTL8382M/RTL8382L). These bits and the TX port list will be mixed to a list. We call this mixed list the
final TX port list.
Port isolation port mask settings will affect received packets; however, the Mirroring function is not
affected by the port isolation port mask.
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8.6. IEEE 802.3x Flow Control
The RTL8380M/RTL8382M/RTL8382L supports IEEE 802.3x full duplex flow control. If one port’s
received frame buffer is over the pause threshold, a pause-on frame is sent to indicate to the link partner
to stop the transmission. When the port’s received frame buffer drops below the pause threshold, it sends
a pause-off frame. The TX pause frame format is shown in Figure 13.
Figure 13. TX Pause Frame Format
The flow control mechanism of the RTL8380M/RTL8382M/RTL8382L is implemented on the RX side.
It counts the received pages on the RX side in order to determine on which port it should send out Pause
On/Off packets.
Figure 14. Flow Control State Machine
When RTL8380M/RTL8382M/RTL8382L flow control is enabled, the initial state is ‘Non_Congest’. The
state is monitored continuously. If a pause-on trigger condition occurs, it enters the ‘Congest’ state. When
in the ‘congest’ state, it is also continuously monitored. When a pause-off trigger condition occurs it reenters the ‘Non_Congest’ state. Figure 14 shows the flow control state machine.
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8.7. Half Duplex Backpressure
There are two mechanisms for half duplex backpressure (Backpressure is for input buffer overflow).
8.7.1.
Collision-Based Backpressure (Jam Mode)
If the input buffer is ready to overflow, this mechanism will force a collision. When the link partner
detects this collision, the transmission is rescheduled.
The Reschedule procedure is:
•
When the link partner detects the collision, it waits for a random backoff time. The
RTL8380M/RTL8382M/RTL8382L will handle packets that are in the input packet buffer during this
time
•
RXDV and TXEN will be driven high. The RTL8380M/RTL8382M/RTL8382L will send a 12-byte
Jam signal (pattern is preamble (7bytes) + SFD (1byte) + 0xAA (4bytes)). The
RTL8380M/RTL8382M/RTL8382L will then drive TXEN low
•
When the link partner (which could be another RTL8380M/RTL8382M/RTL8382L) receives the Jam
signal, it will feedback a 4-byte signal (pattern is derived from the CRC of all transmitted bytes)
•
After the RTL8380M/RTL8382M/RTL8382L receives this jamming signal, it drives RXDV low. The
link partner waits for a random backoff time then re-sends the packet. The timing is shown in
Figure 15
Figure 15. Signal Timing for Collision-Based Backpressure
8.7.2.
Carrier-Based Backpressure (I.e., Defer Mode)
If the input buffer is about to overflow, this mechanism will send a fix pattern to defer the other station’s
transmission. The RTL8380M/RTL8382M/RTL8382L will continuously send the defer signal until the
input buffer overflow is resolved.
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8.8. Layer 2 Multicast and IP Multicast
There are two RTL8380M/RTL8382M/RTL8382L IP multicast frame types: IPv4 multicast and IPv6
multicast.
An IPv4 multicast frame must satisfy two conditions:
•
The type must be IPv4
•
DMAC should=01-00-5E-XX-XX-XX
An IPv6 multicast frame must satisfy two conditions:
•
The type must be IPv6
•
DMAC should=0x33-33-XX-XX-XX-XX
The RTL8380M/RTL8382M/RTL8382L definition of a L2 multicast packet is that the packet is not an IP
multicast packet, and the I/G bit of the MAC address is 1.
The RTL8380M/RTL8382M/RTL8382L supports IGMPv1/2/3. IGMP and MLDv1/2 packets can be
trapped to the CPU to allow software to insert an IP multicast entry into the L2 table.
8.9. IEEE 802.1d/1w/1s (STP/RSTP/MSTP)
There are 64 spanning tree instances for the RTL8380M/RTL8382M/RTL8382L. The CPU will create a
different Port State for different spanning tree instances at each port.
The RTL8380M/RTL8382M/RTL8382L will assign a VID for a received packet, and will look up the
VLAN table to check for Multiple Spanning Tree Instances (MSTI).
The RTL8380M/RTL8382M/RTL8382L will follow the ports MSTI state to complete its corresponding
ingress/egress check. The Spanning Tree and Rapid Spanning Tree port states are shown in Figure 16.
Figure 16. Spanning Tree and Rapid Spanning Tree Port States
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When using IEEE 802.1D, the RTL8380M/RTL8382M/RTL8382L supports four status’ for each port:
Disabled
Except for software forwarding, the port will not transmit/receive packets, and will not perform learning.
Blocking/Listening
Except for software forwarding, the port will only receive BPDU spanning tree protocol packets, but will
not transmit any packets, and will not perform learning.
Learning
The port will receive any packet, including BPDU spanning tree protocol packets, and will perform
learning, but will only transmit BPDU spanning tree protocol packets.
Forwarding
The port will transmit/receive all packets, and will perform learning.
There are five Spanning Tree port states, and four Rapid Spanning Tree port states. Their mapping
relations are DiscardingÆBlocking, LearningÆLearning, and ForwardingÆForwarding (see Table 45).
Receive BPDUs
Transmit BPDUs
Learn Address
Forward Frame
Table 45. Spanning Tree and Rapid Spanning Tree Action
Spanning Tree
Rapid Spanning Tree
Disable
Blocking
Listening Learning Forwarding Discard Learning Forwarding
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
No
No
No
No
Yes
No
No
Yes
8.10. IEEE 802.1p and IEEE 802.1Q (VLAN)
The RTL8380M/RTL8382M/RTL8382L supports IEEE 802.1Q tag-based, protocol-and-port-based, portbased, MAC-based, IP-subnet-based, and application-based VLANs. It supports a 4K-entry VLAN table,
supporting C-VID (Customer VLAN ID) and FID (Filtering Identifier) entries. There are 6 fields in the
VLAN table, and their definitions are as below.
•
MBR: Determines whether the packets belong to the same VLAN
•
UNTAG: Determines whether Egress packets have a VLAN tag
•
FID_MSTI: Gets different FIDs (Filtering Identifier) or determines the index of multiple spanning
tree instances from different VLANs
•
L2_HKEY_UBCAST: Determines the hash key (VID or FID) for L2 unicast and broadcast traffic
•
L2_HKEY_MCAST: Determines the hash key (VID or FID) for L2 multicast and IP multicast traffic
•
VLAN_PROFILE: Determines the index of the VLAN profile
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The RTL8380M/RTL8382M/RTL8382L supports eight global VLAN profiles, each VLAN profile has
the following configurations:
•
L2_LRN_EN: Enable L2 SA learning
•
L2_UNKN_MC_FLD_PMSK: Unknown L2 multicast flooding port mask
•
IP4_UNKN_MC_FLD_PMSK: Unknown IPv4 multicast flooding port mask
•
IP6_UNKN_MC_FLD_PMSK: Unknown IPv6 multicast flooding port mask
For un-managed switches, there is a register setting to disable tag-based VLANs and force ‘no check’ for
any VLAN settings. If a packet is tagged in, then it is tagged out. If untagged in, then it is untagged out.
•
The RTL8380M/RTL8382M/RTL8382L supports ingress and egress VLAN filtering functions
•
Ingress VLAN filtering: Packets from an input port that is not in the VLAN member set will be
dropped, trapped, or forwarded depending on register configuration
•
Egress VLAN filtering: Packets to an output port that is not in the VLAN member set will be dropped,
trapped, or forwarded depending on register configuration
8.11. IEEE 802.1X (Network Access Control)
The RTL8380M/RTL8382M/RTL8382L provides a software solution for 802.1X.
When a host connects to a switch, the switch will transfer the host information to an authentication server:
•
If authentication is successful, the switch will set the control bit of this port to ‘TRUE’ (i.e., the host
will be allowed the service)
•
If authentication is not successful, the switch will deny the host access to the network
The CPU port can be regarded as a special port where transmit and receive packets are unrestricted for
802.1X.
The RTL8380M/RTL8382M/RTL8382L supports two types of 802.1X; Port-Based Network Access
Control, and MAC-Based Network Access Control.
•
Port-Based Network Access Control: For each port, there is a bit to check whether this port has passed
authentication or not. A direction control register decides whether this port needs pass-through
authentication for both (IN/OUT) directions or only for receive (IN)
•
MAC-Based Access Control: Provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. There is a
register that enables/disables each logical port MAC-based network access control function. Another
register controls transmit/receive direction authentication for each port (IN/OUT) or only receive
direction (IN)
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Table 46 illustrates the forwarding of host n.
Authentication of Host n
0 (Unauthorized)
0 (Unauthorized)
1 (Authorized)
1 (Authorized)
Table 46. Forwarding of Host n
Direction of Whole Chip
Fwd Frames to Host n
0 (BOTH)
No
1 (IN)
Yes
0 (BOTH)
Yes
1 (IN)
Yes
Fwd Frames from Host n
No
No
Yes
Yes
8.12. Reserved Multicast Address Handling
There are some Reserved Multicast Address (RMA) definitions in the IEEE 802.1 standard. The
RTL8380M/RTL8382M/RTL8382L includes 01-80-C2-00-00-00 to 01-80-C2-00-00-2F RMA support
and provides user defined RMA settings. For each RMA, the actions include: Table lookup, Drop, Trap to
CPU, and always Flood. The action priority is higher than the results of a L2 Table lookup. Default
actions are shown in Table 47.
Table 47. Reserved Multicast Address Default Actions
Name
Address
Bridge Group Address
01-80-C2-00-00-00
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation
01-80-C2-00-00-01
IEEE Std 802.3ad Slow Protocols-Multicast Address
01-80-C2-00-00-02
IEEE Std 802.1X PAE Address
01-80-C2-00-00-03
Reserved for future protocol standards
01-80-C2-00-00-04 to 01-80-C2-00-00-0D,
01-80-C2-00-00-0F
01-80-C2-00-00-0E
LLDP IEEE Std 802.1AB Link Layer Discovery Protocol
Multicast Address
All LANs Bridge Management Group Address
01-80-C2-00-00-10
GMRP
01-80-C2-00-00-20
GVRP
01-80-C2-00-00-21
Reserved for use by Multiple Registration
01-80-C2-00-00-22 to 01-80-C2-00-00-2F
Protocol (MRP) applications
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Forward
Drop
Drop
Forward
Drop
Forward
Drop
Drop
Forward
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8.13. Layer 2 Traffic Suppression (Storm Control)
The per-port L2 storm filtering control mechanism suppresses the flow rate of some specific packets. The
RTL8380M/RTL8382M/RTL8382L supports five control types: Unknown Unicast Storm, Unicast Storm,
Unknown Multicast Storm, Multicast Storm, and Broadcast Storm. Each port has control registers to
enable or disable the storm filtering function. These five traffic type definitions are:
•
Unknown Unicast: If the I/G bit of the packet’s destination address is 0, it is a unicast packet and its
DA look-up in the L2 unicast table failed. I.e., the packet’s destination address is unknown
•
Unicast: The unicast storm filtering control includes unknown and known unicast for
RTL8380M/RTL8382M/RTL8382L
•
Unknown Multicast: If the I/G bit of the packet’s destination address is 1, it is a multicast packet and
its DA look-up in the L2 unicast table failed, i.e., the packet’s destination address is unknown
•
Multicast: The multicast storm filtering control includes unknown and known multicast for
RTL8380M/RTL8382M/RTL8382L
•
Broadcast: DMAC = FF-FF-FF-FF-FF-FF indicates this is a broadcast packet
Unknown Unicast and Unicast use the same traffic counter, and Unknown Multicast and Multicast use the
same traffic counter. The user should set the Unicast and Multicast storm type as unknown or both known
and unknown in the storm filter setting.
The traffic rate for these five types can be set on a per-port basis. The priority sequence of L2 filtering
control is:
1. Input bandwidth control
2. ACL policy
3. Storm-filtering control
8.14. PIE (Packet Inspection Engine)
PIE is a 1.5K-entry search engine that is divided into 12 blocks (block numbers are 0~11). Each block
size is 128-entries. Every entry has 216-bit data, and a 216-bit mask. There is an extra bit to indicate
whether this entry is valid or not. Each block can be disabled for power saving when it is not used. All the
entries are prepared for ingress ACL.
8.14.1. Ingress ACL
The Ingress ACL (Access Control List) perform actions such as packet drop, forwarding, ingress I-VID
Assignment, Ingress O-VID Assignment, filter, log, remarking, meter, mirror etc. When a packet hits one
entry it will execute the corresponding action mapped to this entry. Each PIE memory entry corresponds
to one action entry. The packet can match to multi-actions. When a multi-match occurs (i.e., there are
several ACL entries that match) in one block, it will execute the lowest address entry corresponding
action.
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8.15. Input Bandwidth Control and ACL Traffic Meter
8.15.1. Input Bandwidth Control
The RTL8380M/RTL8382M/RTL8382L has input bandwidth control for each port (excluding the CPU
port). The bandwidth setting range is 16Kbps~1Gbps. The granularity is 16Kbps, and each port has a
16-bit register to control the bandwidth. If the speed of received packets is faster than the bandwidth
setting, it will send a ‘Pause ON’ packet to slow the link partner transmissions when the flow control
function is enabled, and drop packets when the flow control function is disabled. When normal
transmissions become possible and the flow control function is enabled, the switch will send a ‘Pause
OFF’ packet.
8.15.2. ACL Traffic Meter
For Ingress ACL entry, there is an index to point to 256 ACL rate-limited entries. The rate limit is flow
controlled via leaky bucket. The rate range is 16Kbps~1Gbps, the granularity is 16Kbps, and each ratelimited entry has a 16-bit register to control the rate value.
8.16. IEEE 802.3ad Link Aggregation Protocol
To ensure correct frame ordering when changing the hash algorithm, the marker protocol mechanism
must be started. Software will wait for the aggregation port queues to empty, and then send a marker
message to all aggregation ports. After receiving a marker reply packet, software can change the hash
algorithm.
The RTL8380M/RTL8382M/RTL8382L supports 802.3ad (Link Aggregation) for 8 groups of link
aggregators with up to 8 ports per-group (based on DMAC/SMAC/SPA/SIP/DIP/SPORT/DPORT). The
CPU port cannot be aggregated to an aggregation port. As the RTL8380M/RTL8382M/RTL8382L does
not check CPU port aggregation, software should check this to avoid frame transmit errors.
Frame Distribution
Link aggregation group frames are sent to an aggregation port of the link aggregation group according to
a hash algorithm. There are seven parameters (DMAC, SMAC, SPA, SIP, DIP, SPORT, DPROT). To
prevent assigning the same hash value when hash keys simultaneously change to another value, we
stagger the least significant bit of all hash keys.
Mapping a Physical Port to a Logical Port
No matter how many physical aggregation port members are in a link aggregation group, it is regarded as
one logical port. Each link aggregation has an ID (the lowest number of the physical aggregation port
members is used as its ID). Once the ID is chosen, even if the logical port ID’s corresponding physical
port is link down, the ID and setting of the link aggregation group will not change. However, it will
change when this corresponding port is removed or a lower-numbered port is added.
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Hash Algorithm Change
The algorithm will change when the following conditions occur:
•
The link aggregation group member port changes to link-down or link-up
•
The user/LACP (i.e., Link Aggregation Control Protocol) changes the link aggregation group member
port or register setting
8.17. IEEE 802.1ad VLAN Stacking
The RTL8380M/RTL8382M/RTL8382L supports multi-layered VLANs and can have Outer-VLAN and
Inner-VLAN tagging. Standard 802.1ad takes the S-tag (Service VLAN tag) as the relay VID. The
RTL8380M/RTL8382M/RTL8382L uses the Outer-tag as S-tag, and the Inner-tag as C-tag to support
802.1ad applications.
The IEEE 802.1ad frame format is shown in Figure 17.
Figure 17. IEEE 802.1ad Frame Format
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8.18. Quality of Service (QoS)
There are 5 types of Priority Assignment for the RTL8380M/RTL8382M/RTL8382L:
•
Port-based Inner-tag Priority
•
Port-based Outer-tag Priority
•
Inner-tag-based Priority
•
Outer-tag-based Priority
•
DSCP-based Priority
These priority assignments will pass through the whole system priority selection table to decide the
packets internal priority. Afterwards the internal priority will point to the adaptive output queue ID table.
Priority Selection Tables
A received packet may be assigned up to five different priorities. These priorities are coordinated into a
final priority according to the priority selection table Figure 18. Each priority assignment has a control
register. The corresponding bit set to 1, sets the priority from high bit to low bit.
Inner-tag-based priority, Outer-tag-based priority, and DSCP-based priority may be NULL.
The priority arbiter should check whether the item is NULL or not. The NULL item priority corresponds
to the lowest priority arbitration value; the bigger the corresponding priority arbitration value, the higher
the priority assignment.
We can take an example to describe the priority order. The order is Inner-tag-based priority assignment >
DSCP-based priority assignment > Outer-tag based priority assignment > Port-based Inner-tag Priority
assignment = Port-based Outer-tag Priority assignment.
Figure 18. Priority Selection Table Weight Rules Example 1
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Internal Priority to Queue ID Table
Weighted Arbitor
The RTL8380M/RTL8382M/RTL8382L can transfer its internal priority setting (see Figure 19) to the
output queue ID. The RTL8380M/RTL8382M/RTL8382L can configure each port’s output queue level
(including the CPU port). Each port has eight output queues.
Figure 19. Per-Port Queue Management
8.19. Packet Scheduling (WRR and WFQ)
The Packet Scheduler controls the various traffic classes (i.e., controls the packet sending sequence of the
priority queue). The RTL8380M/RTL8382M/RTL8382L scheduling algorithm is divided into Weighted
Fair-Queuing (WFQ) and Weighted Round-Robin (WRR). Note that the Strict Priority queue is the
highest priority of all queues, and overrides WFQ & WRR. A larger strict priority queue ID indicates the
priority is higher.
The Scheduler operates as follows:
•
Weighted Fair-Queuing (WFQ): Byte-count
•
Weighted Round-Robin (WRR): Packet-count
WFQ and WRR cannot exist at the same time. WFQ or WRR can co-exist with Strict Priority Schedule.
Both WFQ and WRR are round robin, from large queue ID to small.
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8.20. Packet Drop Algorithm (TD)
The RTL8380M/RTL8382M/RTL8382L supports Tail Drop (TD).
•
Tail Drop (TD): For a drop threshold value, if a packet meets queue overflow conditions before
entering the output queue, the switch will drop this packet
8.21. Egress Packet Remarking
The RTL8380M/RTL8382M/RTL8382L Remarking can be divided into Inner-tag remarking, Outer-tag
remarking, and DSCP remarking.
•
For Inner-tag remarking, there is an internal priority to inner-tag priority remarking table that is used
to configure the final user inner-tag priority value for per-port egress of a packet
•
For Outer-tag remarking, there is an internal priority to outer-tag priority remarking table that is used
to configure the final Outer-tag priority value for per-port egress of a packet
•
DSCP remarking also has an internal priority to DSCP priority table for per-port egress of a packet
8.22. Ingress and Egress Port Mirror
The RTL8380M/RTL8382M/RTL8382L has four mirror sets (set0~3), and the Mirroring port can
monitor several mirrored ports simultaneously. RX mirror and TX mirror function is supported by setting
a source port mask, destination port mask. The mirror function can be configured across VLANs. The
RTL8380M/RTL8382M/RTL8382L supports a mirror filtering function to filter forwarded traffic. Only
mirrored traffic can egress though a mirroring port.
The RTL8380M/RTL8382M/RTL8382L provide a flexible flow-based mirror function. In a flow-based
mirror, only specified packets will be mirrored through a configured ACL action and fill a corresponding
traffic mirror table entry.
For flow control, the mirroring port will drop the mirrored packets and send PAUSE frames or
backpressure signals to the mirrored port for normal packets. It will resume mirror function when flow
control is back to normal status. The design limitations for mirroring settings are as below.
•
Each mirror entry can only set one mirroring port
•
A mirroring port cannot be a member of a trunk group
•
The mirroring port is not limited by port isolation for mirrored packets
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8.22.1. Remote Mirror (RAPAN)
The RTL8380M/RTL8382M/RTL8382L support Remote Switched Port Analyzer (RSPAN) to analyze a
remote device’s traffic flow. The RTL8380M/RTL8382M/RTL8382L defined RSPAN VLAN tag is
illustrated in Figure 20. Users can configure the RSPAN tag’s TPID/VID/Priority/CFI at each port. The
RTL8380M/RTL8382M/RTL8382L can parse for the RSPAN tag in RX and add or remove RSPAN tags
in TX.
DMAC
SMAC
DMAC
SMAC
RSPAN TPID
Layer2
Header
PAYLOAD
RSPAN Tag
PRIO
Layer 2
Header
CFI
FCS
PAYLOAD
FCS
RSPAN VID
Figure 20. RSPAN Encapsulation
Figure 21 shows an example of an RSPAN application. In Source Switch A, Port0 is configured as a
mirrored port, and Port2 as a mirroring port with setting ‘TX added RSPAN tag’.
In Intermediate Switch B, Port3 and Port5 are added as RSPAN VLAN members. RSPAN mirrored
packets will be forwarded without any modification.
In Destination Switch C, Port7 and Port9 join as RSPAN VLAN members, with Port9 configured to
‘Remove RSPAN tag in TX’. This means packets are mirrored from Source Switch A Port0 to
Destination Switch C Port9 without modification.
Figure 21. RSPAN Illustration
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8.23. Management Information Base (MIB)
The RTL8380M/RTL8382M/RTL8382L MIB (Management Information Base) counters include:
•
Ethernet-like MIB (RFC 3635)
•
Interface Group MIB (RFC 2863)
•
RMON (Remote Network Monitoring) MIB (RFC 2819)
•
Bridge MIB (RFC 1493)
•
Bridge MIB Extension (RFC 2674)
8.24. NIC and CPU Tag Forwarding
NIC interface: This is used for receiving packets from the CPU, or transmitting packets to the CPU. The
architecture is shown in Figure 22.
When a packet is sent from the switch core to the CPU port, the CPU tag can carry status information.
The CPU tag can be divided into a transmit CPU tag, and a receive CPU tag.
•
Transmit CPU Tag: Forces TX port mask. Indicates which ports the packet will NOT be sent to. For
example, if we set port1, port2, and port5 mask bits, then the packet will not be sent to these ports
•
Receive CPU Tag: Indicates which RX port the packet came from
If no CPU tag is attached, the normal process will be followed to perform a look-up in the L2 table.
DMA
NIC
Driver
SDRAM
MAC Rx
NIC
CPU
Port
MAC
Switch
Core
DMA
MAC
MAC Tx
Figure 22. NIC Architecture
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8.25. Indirect Table Access
The RTL8380M/RTL8382M/RTL8382L employs an indirect method to set the control register and the
data register to complete a VLAN/L2 Lookup/ Forwarding/SPT/ACL Table Access:
1. Sets the register to determine which table and which entry is to be accessed
2. Determines the read or write action
3. Hardware executes table access
Read: After the control register setup has been completed by software, hardware access then puts this data
into the data register. Software then reads this data from the data register.
Write: The data is placed in the data register by software and the control register is set. Hardware writes
this data to the table.
8.26. External PHY Register Access
After the RTL8380M/RTL8382M/RTL8382L powers on and initializes, it will set the PHY MII register
via MDC/MDIO. The RTL8380M/RTL8382M/RTL8382L supports three access control registers to
indirectly access an external PHY via the MDC/MDIO interface.
8.27. Switch Interrupt Indication
The RTL8380M/RTL8382M/RTL8382L provides one global interrupt function: switch interrupt.
Interrupt sources are listed below:
•
Port Link Change interrupt
•
Port SA learning constraint interrupt
•
SerDes interrupt
9.
CPU Function Description
9.1. MIPS-4KEc
•
MIPS 4KEc CPU Core (Targeted at 500MHz): 5-stage pipeline, MIPS32 instruction set, additional
MIPS16e instruction set support, 2 GPR sets (one shadow set), and vectored/Non-Maskable Interrupts
(NMI) support
•
Cache Configuration: I-Cache is 16KB, 4-way set associative, and 16-byte line size. D-Cache is
16KB, 4-way set associative, 16-byte line size, and write-back policy. It also has virtually indexed,
physically tagged, and Prefetch instructions
•
MMU Configuration: 4-entry ITLB, 4-entry DTLB, and 32-entry JTLB
•
Misc.: Power-down mode, EJTAG support, internal BIST, internal real-time timer interrupts
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(Count/Compare registers), and CPU breakpoints
9.2. SPI Flash
The RTL8380M/RTL8382M/RTL8382L support 32M-Byte (max) serial I/O, dual I/O SPI Flash.
9.3. SDRAM Interface Configuration (RTL8380M/RTL8382M
Only)
Only the RTL8380M/RTL8382M support 8-bit data bus DDR1/DDR2/DDR3 SDRAM.
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10. Interface Descriptions
10.1. QSGMII
QSGMII-plus (Quad Serial Gigabit Media Independent Interface) reduces PCB complexity and IC pin
count. This innovative 5Gbps serial interface provides an up to 10 inch MAC to PHY communication
path. QSGMII can carry the full duplex gigabit Ethernet data streams of four ports simultaneously, using
only 4 pins.
Port0
MAC
PHY
TX+/-
RX+/-
TX
Port0
RX
Port1
Port1
25MHz
QGMII
RX+/-
Port2
QSGMII
TX+/-
RX
Port2
TX
Port3
Port3
Figure 23. QSGMII Interconnection
10.2. RSGMII
RSGMII (Reduced Serial Gigabit Media Independent Interface) reduces PCB complexity and IC pin
count. This innovative 2.5Gbps serial interface provides an up to 10 inch MAC to PHY communication
path. RSGMII can carry the full duplex gigabit Ethernet data streams of two ports simultaneously, using
only 4 pins.
Figure 24. RSGMII Interconnection
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10.3. SGMII
SGMII (Serial Gigabit Media Independent Interface) conveys PHY and MAC data with significantly less
pins than required for GMII. It operates in both half and full duplex, and at all port speeds. It includes 4
data signals and 2 CLK signals to convey frame data and link rate information between the PHY and
MAC. The data signals operate at 1.25Gbaud, and the CLK operates at 625MHz. Each of these signals is
carried as a differential pair, thus providing signal integrity while minimizing system noise.
Figure 25. SGMII Signal
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10.4. DDR1 SDRAM (RTL8380M/RTL8382M Only)
The RTL8380M/RTL8382M support DDR1 SDRAM with the following features:
•
Bus width is 8 bits
•
One chip selection
•
Supports 4 banks
•
Row count range is 4~16K, and column count range is 512~4K
•
Supports maximum 128M Bytes DDR1 SDRAM
Figure 26. DDR1 SDRAM Configuration
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10.5. DDR2 SDRAM (RTL8380M/RTL8382M Only)
The RTL8380M/RTL8382M supports DDR2 SDRAM with the following features:
•
Bus width is 8 bits
•
One chip selection
•
Supports 4 banks or 8 banks
•
Row count range is 4~16K, and column count range is 512~4K
•
Supports maximum 128M Bytes DDR2 SDRAM
Figure 27. DDR2 SDRAM Configuration
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10.6. DDR3 SDRAM (RTL8380M/RTL8382M Only)
The RTL8380M/RTL8382M supports DDR3 SDRAM with the following features:
•
Bus width is 8 bits
•
One chip selection
•
Supports 8 banks
•
Supports maximum 256M Bytes DDR3 SDRAM
Figure 28. DDR3 SDRAM Configuration
10.7. SPI Flash Interface
The RTL8380M/RTL8382M/RTL8382L support SPI Flash with the following features:
•
Supports serial I/O, dual I/O SPI Flash (max)
•
Supports both MMIO (Memory Mapped I/O) and PIO (Programmed I/O) mode
•
One chip selection
•
Supports maximum 32M Bytes SPI Flash in PIO mode and 16M Bytes in MMIO mode
Figure 29. SPI Flash Configuration
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10.8. UART
The RTL8380M/RTL8382M/RTL8382L provides two UARTs, and each contains a 16-byte FIFO buffer.
The baud rate can be up to 1Mbps and a programmable baud rate generator allows division of any input
reference clock by 1 to 65535, and generates an internal 16x clock. The RTL8380M/RTL8382M provides
a fully programmable serial interface.
In addition to the above functions, the RTL8380M/RTL8382M/RTL8382L provides fully prioritized
interrupt control and loopback functionality for diagnostic capabilities.
The UART interface pins are shown in the following table.
Signal Name
TXD#
RXD#
Table 48. UART Control Interface Pins
Type
Description
Output
Transmit Data.
Input
Receive Data.
10.9. EJTAG
EJTAG is inexpensive, and easy to implement. EJTAG utilizes the 5-pin IEEE 1149.1 JTAG (Joint Test
Action Group) specification for off-chip communication. The interface pins are shown in Table 49.
Signal Name
TDI
TDO
TCK
TMS
TRST
Table 49. EJTAG Interface Pins
Type
Description
Input
Test Data In.
Output
Test Data Out.
Output
Test Clock.
Output
Test Mode Select.
Output (Optional)
Test Reset.
EJTAG Circuitry
TRST
TMS
TAP Controller
A+ D
TCK
CPU
Addr .
Direct Memory
Access
Data
TDO
TDI
A+ D
Debug
Registers
A+ D
System
Memory
Addr.
Instruction, Data, and
Control Registers
Processor
Access
Data
Address / Data Busses
Figure 30. EJTAG Using a 5-Pin JTAG Interface to Access Data Block
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EJTAG provides a path to access internal debug registers and circuitry that monitor and control the
address and data busses of the processor. The DMA and Processor circuit blocks are used to setup and
monitor the processor’s internal busses and to execute the code from the EJTAG interface.
When an access is detected, the EJTAG circuitry makes the transaction address available in the EJTAG
Address Register, and the appropriate data available in the EJTAG Data Register. It takes about 200 TCK
periods to access 32-bit address and data registers in this fashion, so with a 40MHz TCK frequency, the
access time is in the range of 5µs.
10.10.
I2C Master for EEPROM
The EEPROM can be divided into two sizes: 2Kb~8Kb and 32Kb~512Kb. The address of the small size
EEPROM is 8-bits, however the larger EEPROM has word-high addressing and word-low addressing,
and it is 16-bits (two bytes).
Figure 31. 8-Bit EEPROM Sequential Read
10.11.
I2C Slave Interface
The RTL8380M/RTL8382M/RTL8382L supports a I2C slave interface (Slave mode) for external CPU to
access the internal register. It has two I/O pins (i.e., SDA and SCL). SDA is the access data signal, and
SCL is the clock signal (typical clock is 1~2MHz). The read/write data sequence is shown below.
Figure 32. I2C Slave Interface Access Data Sequence
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10.12.
SPI Slave Interface
The RTL8380M/RTL8382M/RTL8382L supports an SPI slave interface (Slave mode) for an external
CPU to access the internal register. It has four I/O pins (SI, SO, SCK, and CS#).
The instruction sets are as shown in the following table.
Instruction Name
Table 50. SPI Slave Interface
Byte 2
Byte 3
Byte 4
Byte 5
Write Data
Byte 1
(Code)
02h
A23~A16
A15~A8
A7~A0
Read Data
03h
A23~A16
A15~A8
A7~A0
Byte 6
Byte 7
Byte 8
D31~D24
D23~D16
D15~D8
D7~D0
D31~D24
D23~D16
D15~D8
D7~D0
Note:
A23~A8: Maps to the switch’s 16-bits register address.
A7~A0 in Write Data Instruction: Dummy byte for switch and conforms to standard SPI 24-bits address format.
A7~A0 in Read Data Instruction: Dummy byte waits for the switch to prepare the register data and conforms to standard
SPI 24-bits address format.
D31~D0: 32-bits Register Data.
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10.13.
Serial LED
The RTL8380M/RTL8382M/RTL8382L supports a serial LED interface to display the link status. The
serial LED interface, LED_CK and LED_DA provide clock and data to enable/disable the external shift
registers. A 74HC164 8-Bit Serial-In, Parallel-Out Shift Register captures the per-port link status and
diagnostic information. In serial shift LED mode, the RTL8380M/RTL8382M/RTL8382L supports perport one/two/three single-color LED to show the speed, link status, and other information.
Figure 33. Serial LED Connection
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The default LED status for RTL8380M/RTL8382M/RTL8382L is as follows:
LED Number
LED0 Defintion
LED1 Defintion
LED2 Defintion
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3-LEDs
1000M Link
100M Link
Link/Act
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11. Electrical AC/DC Characteristics
11.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified referenced to GND unless
otherwise specified.
Table 51. Absolute Maximum Ratings
Parameter
Min
Junction Temperature (Tj)
Storage Temperature
-10
DVDDH, AVDDH, SVDDH, AVDDH_PLL Supply Referenced to DGND,
2.97
AGND
DVDDL, AVDDL, SVDDL, AVDDL_PLL, PLLVDDL Supply Referenced
0.90
to DGND, AGND
MVDDH Supply Referenced to DGND(for DDR1)
2.375
MVDDH Supply Referenced to DGND(for DDR2)
1.71
MVDDH Supply Referenced to DGND(for DDR3)
1.425
VDDIO
1.875（2.5）
1.350（1.5）
Max
+125
+125
Units
°C
°C
3.63
V
1.18
V
2.625
1.89
1.575
2.625（2.5）
V
V
V
V
1.575（1.5）
V
11.2. Operating Range
Table 52. Recommended Operating Range
Parameter
Min
Typical
Ambient Operating Temperature (Ta)
0
DVDDH, AVDDH, SVDDH, AVDDH_PLL
3.135
3.3
Supply Voltage Range
DVDDL, AVDDL, AVDDL_PLL, PLLVDDL
0.95
1.1
Supply Voltage Range
SVDDL Supply Voltage Range
1.05
1.1
MVDDH Supply Voltage Range(for DDR1)
2.375
2.5
MVDDH Supply Voltage Range(for DDR2)
1.71
1.8
MVDDH Supply Voltage Range(for DDR3)
1.425
1.5
VDDIO
1.875
2.5
1.350
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80
1.5
Max
55
Units
°C
3.465
V
1.15
V
1.15
2.625
1.89
1.575
V
V
V
V
2.625
V
1.575
V
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11.3. DC Characteristics
Symbol
VIH
VIL
VOH
VOL
Table 53. DC Characteristics (IO_Power=3.3V)
Parameter
Min
TTL Input High Voltage
2.0
TTL Input Low Voltage
Output High Voltage
2.4
Output Low Voltage
-
Typical
-
Max
0.8
0.4
Units
V
V
V
V
11.4. AC Characteristics
11.4.1. QSGMII Differential Transmitter Characteristics
Symbol
UI
T_X1
T_X2
T_Y1
T_Y2
VTX-DIFFp-p
TTX-EYE
TTX-JITTER
TTX-RISE
TTX-FALL
RTX
Table 54. QSGMII Differential Transmitter Characteristics
Parameter
Min
Typical
Max
Units
Unit Interval
199.94
200
200.06 ps
Eye Mask
0.2
UI
Eye Mask
0.4
UI
Eye Mask
150
mV
Eye Mask
650
mV
Output Differential Voltage
600
900
1300
mV
Minimum TX Eye Width
0.6
UI
Output Jitter
0.4
UI
Output Rise Time
0.15
UI
Output Fall Time
0.15
UI
Differential Resistance
80
100
120
ohm
-
CTX
LTX
Notes
200ps±300ppm
-
Transmit Length in PCB
-
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-
81
10
inch
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TTX-EYE-MIN
T_Y2
T_Y1
Amplitude
0V
VTX-DIFFp-p-MIN
VTX-DIFFp-p-MAX
-T_Y1
-T_Y2
0.0
T_X1
T_X2
1-T_X2
1-T_X1
1.0
Time UI
Figure 34. QSGMII Differential Transmitter Eye Diagram
11.4.2. QSGMII Differential Receiver Characteristics
Symbol
UI
R_X1
R_Y1
R_Y2
VRX-DIFFp-p
TRX-EYE
TRX-JITTER
RRX
Table 55. QSGMII Differential Receiver Characteristics
Parameter
Min
Typical
Max
Units
Unit Interval
Eye Mask
Eye Mask
Eye Mask
Input Differential Voltage
Minimum RX Eye Width
Input Jitter Tolerance
Differential Resistance
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
199.94
100
200
0.4
80
200
100
82
200.06
0.3
650
1300
0.6
120
ps
UI
mV
mV
mV
UI
UI
ohm
Notes
200ps±300ppm
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TRX-EYE-MIN
R_Y2
R_Y1
Amplitude
0V
VRX-DIFFp-p-MIN
VRX-DIFFp-p-MAX
-R_Y1
-R_Y2
0.0
R_X1
0.5
1-R_X1
1.0
Time UI
Figure 35. QSGMII Differential Receiver Eye Diagram
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11.4.3. RSGMII Differential Transmitter Characteristics
Symbol
UI
T_X1
T_X2
T_Y1
T_Y2
VTX-DIFFp-p
TTX-EYE
TTX-JITTER
TTX-RISE
TTX-FALL
RTX
Table 56. RSGMII Differential Transmitter Characteristics
Parameter
Min
Typical
Max
Units
Unit Interval
399.88
400
400.12
ps
Eye Mask
0.2
UI
Eye Mask
0.4
UI
Eye Mask
150
mV
Eye Mask
550
mV
Output Differential Voltage
600
800
1100
mV
Minimum TX Eye Width
0.6
UI
Output Jitter
0.3
UI
Output Rise Time
0.15
UI
Output Fall Time
0.15
UI
Differential Resistance
80
100
120
ohm
CTX
AC Coupling capacitor
75
100
200
nF
-
LTX
Transmit Length in PCB
-
-
10
inch
-
Notes
400ps±300ppm
-
TTX-EYE-MIN
T_Y2
T_Y1
Amplitude
0V
VTX-DIFFp-p-MIN
VTX-DIFFp-p-MAX
-T_Y1
-T_Y2
0.0
T_X1
T_X2
1-T_X2
1-T_X1
1.0
Time UI
Figure 36. RSGMII Differential Transmitter Eye Diagram
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11.4.4. RSGMII Differential Receiver Characteristics
Symbol
UI
R_X1
R_Y1
R_Y2
VRX-DIFFp-p
TRX-EYE
TRX-JITTER
RRX
Table 57. RSGMII Differential Receiver Characteristics
Parameter
Min
Typical
Max
Units
Unit Interval
Eye Mask
Eye Mask
Eye Mask
Input Differential Voltage
Minimum RX Eye Width
Input Jitter Tolerance
Differential Resistance
399.88
60
120
0.4
80
400
100
400.12
0.3
600
1200
0.6
120
ps
UI
mV
mV
mV
UI
UI
ohm
Notes
400ps±300ppm
TRX-EYE-MIN
R_Y2
R_Y1
Amplitude
0V
VRX-DIFFp-p-MIN
VRX-DIFFp-p-MAX
-R_Y1
-R_Y2
0.0
R_X1
0.5
1-R_X1
1.0
Time UI
Figure 37. RSGMII Differential Receiver Eye Diagram
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11.4.5. SGMII Differential Transmitter Characteristics
Symbol
UI
T_X1
T_X2
T_Y1
T_Y2
VTX-DIFFp-p
TTX-EYE
TTX-JITTER
RTX
Table 58. SGMII Differential Transmitter Characteristics
Parameter
Min
Typical
Max
Units
Unit Interval
799.76
800
800.24
ps
Eye Mask
0.1875
UI
Eye Mask
0.4
UI
Eye Mask
125
mV
Eye Mask
500
mV
Output Differential Voltage
400
700
900
mV
Minimum TX Eye Width
0.625
UI
Output Jitter
0.375
UI
Differential Resistance
80
100
120
ohm
CTX
AC Coupling capacitor
75
100
200
nF
-
LTX
Transmit Length in PCB
-
-
10
inch
-
Notes
800ps±300ppm
-
Figure 38. SGMII Differential Transmitter Eye Diagram
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11.4.6. SGMII Differential Receiver Characteristics
Table 59. SGMII Differential Receiver Characteristics
Parameter
Min
Typical
Max
Symbol
UI
R_X1
R_Y1
R_Y2
VRX-DIFFp-p
TRX-EYE
TRX-JITTER
RRX
Unit Interval
Eye Mask
Eye Mask
Eye Mask
Input Differential Voltage
Minimum RX Eye Width
Input Jitter Tolerance
Differential Resistance
799.76
50
100
0.375
80
800
100
Units
800.24
0.3125
600
1200
0.625
120
ps
UI
mV
mV
mV
UI
UI
ohm
Notes
800ps±300ppm
TRX-EYE-MIN
R_Y2
R_Y1
Amplitude
0V
VRX-DIFFp-p-MIN
VRX-DIFFp-p-MAX
-R_Y1
-R_Y2
0.0
R_X1
0.5
1-R_X1
1.0
Time UI
Figure 39. SGMII Differential Receiver Eye Diagram
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11.4.7. DDR2 Characteristics
Figure 40. DDR2 Timing Characteristics
Table 60. DDR2 SDRAM Timing Characteristics
Symbol Description
Min
fCK, fCK# Clock Frequency of the CK and CK#
Duty
Duty Cycle of the CK and CK#
48
tJITper
Clock period jitter
-110
tJITcc
Cycle-to-cycle jitter
-220
tDS
DQ and DM Output Setup Time
450
tDH
DQ and DM Output Hold Time
450
tIS
Address and Control Output Setup Time
600
tIH
Address and Control Output Hold Time
600
tDQSQ
Input DQS–DQ Skew, DQS to Last DQ Valid
tQH
Input DQ–DQS Hold, DQS to First DQ to Go Non-Valid
0.3
Note: Test Condition, fDDR_CK=300MHz.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
88
Typical
300
50
-
-
Max
52
110
220
300
-
Track ID:
Units
MHz
%
ps
ps
ps
ps
ps
ps
ps
CK
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11.4.8. DDR3 Characteristics
Figure 41. DDR3 Timing Characteristics
Symbol
fCK, fCK#
Duty
tJITper
tJITcc
tDS
tDH
tIS
tIH
tDQSQ
Table 61. DDR3 SDRAM Timing Characteristics
Description
Min
Clock Frequency of the CK and CK#
Duty Cycle of the CK and CK#
47
Clock period jitter
-90
Cycle-to-cycle jitter
-165
DQ and DM Output Setup Time
450
DQ and DM Output Hold Time
400
Address and Control Output Setup Time
750
Address and Control Output Hold Time
550
Input DQS–DQ Skew, DQS to Last DQ Valid
-
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
89
Typical
300
50
-
-
Max
53
90
165
300
Track ID:
Units
MHz
%
ps
ps
ps
ps
ps
ps
ps
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
Symbol Description
tQH
Input DQ–DQS Hold, DQS to First DQ to Go Non-Valid
Note: Test Condition, fDDR_CK=300MHz.
Min
0.3
Typical
-
Max
-
Units
CK
11.4.9. SPI Interface Characteristics
Figure 42. SPI Interface Timing
Table 62. SPI Interface Timing Characteristics
Symbol Description
Min
fSPI_SCK Clock Frequency of the SPI_SCK
49.5
Duty
Duty Cycle of the SPI_SCK
45
tSLCH
CS# Active Setup Time
7
tCHSH
CS# Active Hold Time
8
tsetup:O
Data Output Setup Time
4
thold:O
Data Output Hold Time
6
tsetup:I
Data Input Setup Time
4
thold:I
Data Input Hold Time
0
Note: Test Condition, fSPI_SCK=50MHz.
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
90
Typical
50
50
8.1
9.65
8.3
9.65
-
Max
50.5
55
-
Track ID:
Units
MHz
%
ns
ns
ns
ns
ns
ns
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
11.4.10. SMI (MDC/MDIO) Interface Characteristics
Figure 43. SMI (MDC/MDIO) Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
Table 63. SMI (MDC/MDIO) Timing Characteristics
Description
Min
Typ
380
MDC Clock Period
190
MDC High Time
190
MDC Low Time
190
MDIO to MDC Rising Setup Time (Write Data)
190
MDIO to MDC Rising Hold Time (Write Data)
10
MDIO to MDC Rising Setup Time (Read Data)
10
MDIO to MDC rising hold time (Read Data)
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
91
Max
-
Units
ns
ns
ns
ns
ns
ns
ns
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
12. Package Information
12.1. LQFP216-E-PAD (24*24mm)
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
92
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
93
Track ID:
Rev. 0.7
RTL8380M/RTL8382M/RTL8382L
Datasheet
13. Ordering Information
Table 64. Ordering Information
Part Number
Package
Status
RTL8380M-CG
LQFP 216-Pin E-PAD (24*24mm) ‘Green’ Package (Managed)
RTL8382M-CG
LQFP 216-Pin E-PAD (24*24mm) ‘Green’ Package (Managed)
RTL8382L-CG
LQFP 216-Pin E-PAD (24*24mm) ‘Green’ Package (Un-Managed)
Note: See page 11 (RTL8380M), page 25 (RTL8382M), and page 40 (RTL8382L) for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
18-Port & 28-Port & 26-Port 10/100/1000M Switch Controllers
94
Track ID:
Rev. 0.7
工商网监
湘ICP备2023018690号
