SSD2828QN4R

SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD2828QN4 Advance Information MIPI Master Bridge This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com Rev 1.3 P 1/168 SSD2828QN4 Mar 2013 Copyright © 2013 Solomon Systech Limited Appendix 1: IC Revision history of SSD2828 Specification Version 1.0 1.1 1.2 1.3 SSD2828QN4 Change Items Initial release of Advance Information - Modify the description of END and CO (Section 8.1.38) - Modify the timing for data latch in RGB timing (Section 14.4) - Specify the prefix T in RGB timing (Section14.4) - Modify RGB color arrangement (Table 6-3) - Update power up and power down sequence (Section 15 & Section 16) - Include current consumption of using VDDIO=3.3V (Section 13) Rev 1.3 P 2/168 Mar 2013 Effective Date 16-Oct-12 13-Dec-12 09-Jan-13 27-Mar-13 Solomon Systech CONTENTS 1 GENERAL DESCRIPTION ....................................................................................................... 9 2 FEATURES................................................................................................................................. 10 2.1 2.2 REFERENCES ........................................................................................................................................................10 DEFINITIONS ........................................................................................................................................................10 3 ORDERING INFORMATION ................................................................................................. 11 4 BLOCK DIAGRAM .................................................................................................................. 11 5 FUNCTIONAL DESCRIPTION .............................................................................................. 14 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 FUNCTIONAL BLOCKS ..........................................................................................................................................14 CLOCK AND RESET MODULE ...............................................................................................................................14 EXTERNAL INTERFACE.........................................................................................................................................15 PROTOCOL CONTROL UNIT (PCU).......................................................................................................................15 PACKET PROCESSING UNIT (PPU) .......................................................................................................................15 ERROR CORRECTION CODE/ CYCLIC REDUNDANCY CHECK (ECC/CRC)............................................................16 LONG AND COMMAND BUFFERS ..........................................................................................................................16 INTERRUPT SIGNAL ..............................................................................................................................................16 D-PHY CONTROLLER ..........................................................................................................................................16 ANALOG TRANSCEIVER .......................................................................................................................................16 INTERNAL PLL ....................................................................................................................................................17 6 SSD2828QN4 PIN ASSIGNMENT........................................................................................... 18 7 PIN DESCRIPTION .................................................................................................................. 20 8 COMMAND TABLE ................................................................................................................. 23 8.1 REGISTER DESCRIPTION.......................................................................................................................................25 8.1.1 Device Identification Register.....................................................................................................................25 8.1.2 RGB Interface Control Register 1...............................................................................................................26 8.1.3 RGB Interface Control Register 2...............................................................................................................27 8.1.4 RGB Interface Control Register 3...............................................................................................................28 8.1.5 RGB Interface Control Register 4...............................................................................................................29 8.1.6 RGB Interface Control Register 5...............................................................................................................30 8.1.7 RGB Interface Control Register 6...............................................................................................................31 8.1.8 Configuration Register................................................................................................................................33 8.1.9 VC Control Register....................................................................................................................................35 8.1.10 PLL Control Register ..................................................................................................................................36 8.1.11 PLL Configuration Register........................................................................................................................37 8.1.12 Clock Control Register................................................................................................................................38 8.1.13 Packet Size Control Register 1....................................................................................................................39 8.1.14 Packet Size Control Register 2....................................................................................................................40 8.1.15 Packet Size Control Register 3....................................................................................................................41 8.1.16 Generic Packet Drop Register ....................................................................................................................42 8.1.17 Operation Control Register ........................................................................................................................43 8.1.18 Maximum Return Size Register ...................................................................................................................44 8.1.19 Return Data Count Register........................................................................................................................45 8.1.20 ACK Response Status Register....................................................................................................................46 8.1.21 Line Control Register..................................................................................................................................47 8.1.22 Interrupt Control Register ..........................................................................................................................49 8.1.23 Interrupt Status Register .............................................................................................................................50 8.1.24 Error Status Register ..................................................................................................................................52 8.1.25 Delay Adjustment Register 1.......................................................................................................................54 8.1.26 Delay Adjustment Register 2.......................................................................................................................55 SSD2828QN4 Rev 1.3 P 3/168 Mar 2013 Solomon Systech 8.1.27 8.1.28 8.1.29 8.1.30 8.1.31 8.1.32 8.1.33 8.1.34 8.1.35 8.1.36 8.1.37 8.1.38 8.1.39 8.1.40 8.1.41 8.1.42 8.1.43 8.1.44 8.1.45 8.1.46 8.1.47 8.1.48 8.1.49 8.1.50 8.1.51 8.1.52 8.1.53 8.1.54 8.1.55 8.1.56 8.1.57 8.1.58 8.1.59 8.1.60 8.1.61 8.1.62 8.1.63 8.1.64 8.1.65 8.1.66 9 Delay Adjustment Register 3.......................................................................................................................56 Delay Adjustment Register 4.......................................................................................................................57 Delay Adjustment Register 5.......................................................................................................................58 Delay Adjustment Register 6.......................................................................................................................59 HS TX Timer Register 1 ..............................................................................................................................60 HS TX Timer Register 2 ..............................................................................................................................61 LP RX Timer Register 1 ..............................................................................................................................62 LP RX Timer Register 2 ..............................................................................................................................63 TE Status Register.......................................................................................................................................64 SPI Read Register .......................................................................................................................................65 PLL Lock Register.......................................................................................................................................66 Test Register ...............................................................................................................................................67 TE Count Register.......................................................................................................................................69 Analog Control Register .............................................................................................................................70 Analog Control Register 2 ..........................................................................................................................71 Analog Control Register 3 ..........................................................................................................................72 Analog Control Register 4 ..........................................................................................................................73 Interrupt Output Control Register ..............................................................................................................74 RGB Interface Control Register 7...............................................................................................................75 Lane Configuration Register.......................................................................................................................76 Delay Adjustment Register 7.......................................................................................................................77 Pull Control Register 1 ...............................................................................................................................78 Pull Control Register 2 ...............................................................................................................................80 Pull Control Register 3 ...............................................................................................................................81 CABC Brightness Control Register 1..........................................................................................................82 CABC Brightness Control Register 2..........................................................................................................83 CABC Brightness Status Register ...............................................................................................................84 Encoder Control Register ...........................................................................................................................85 Video Sync Delay Register..........................................................................................................................86 Trimming Register ......................................................................................................................................87 GPIO1 Register...........................................................................................................................................89 GPIO2 Register...........................................................................................................................................91 DLYA01 Register ........................................................................................................................................93 DLYA23 Register ........................................................................................................................................94 DLYB01 Register ........................................................................................................................................95 DLYB23 Register ........................................................................................................................................96 DLYC01 Register ........................................................................................................................................97 DLYC23 Register ........................................................................................................................................98 Analog Control Register 5 ..........................................................................................................................99 Read Register ............................................................................................................................................101 CONFIGURATION ................................................................................................................. 102 9.1 LANE MANAGEMENT .........................................................................................................................................102 9.2 USE CASES .........................................................................................................................................................103 9.2.1 RGB + SPI Interface.................................................................................................................................103 9.2.2 MIPI DC Characteristics ..........................................................................................................................105 9.2.3 High Speed Clock Transmission ...............................................................................................................106 9.2.4 Data Lane State Flow ...............................................................................................................................106 9.2.5 High Speed Data Transmission.................................................................................................................107 9.2.6 Bi-Directional Data Lane Turnaround .....................................................................................................109 9.2.7 Escape Mode.............................................................................................................................................109 9.2.8 Low Power Data Transmission.................................................................................................................111 9.2.9 Reset Trigger.............................................................................................................................................112 9.2.10 Tearing Effect............................................................................................................................................113 9.2.11 Acknowledge .............................................................................................................................................114 9.2.12 Packet Transmission .................................................................................................................................115 9.2.13 HS Transmission Example ........................................................................................................................115 9.2.14 General Packet Structure..........................................................................................................................116 9.2.15 Long Packet Format .................................................................................................................................116 9.2.16 Short Packet Structure ..............................................................................................................................117 SSD2828QN4 Rev 1.3 P 4/168 Mar 2013 Solomon Systech 9.2.17 Data Identifier (DI)...................................................................................................................................117 9.2.18 Victual Channel Identifier (VC) ................................................................................................................118 9.2.19 Data Type (DT) .........................................................................................................................................118 9.3 OPERATING MODES ...........................................................................................................................................122 9.3.2 State machine operation............................................................................................................................135 9.3.3 D-PHY operation ......................................................................................................................................136 9.3.4 Analog Transceiver ...................................................................................................................................137 9.3.5 PLL ...........................................................................................................................................................137 9.3.6 Clock Source Example ..............................................................................................................................138 10 EXTERNAL INTERFACE.................................................................................................. 139 10.1 SPI INTERFACE 8 BIT 4 WIRE .............................................................................................................................139 10.2 SPI INTERFACE 8 BIT 3 WIRE .............................................................................................................................141 10.2.1 3 or 4 wires 8bit SPI read back sequence for 0xFF register which is stored MIPI read back data .........143 10.3 SPI INTERFACE 24 BIT 3 WIRE ...........................................................................................................................145 10.3.1 3 wires 24bit SPI read back sequence for 0xFF register which is stored MIPI read back data...............147 11 MAXIMUM RATINGS........................................................................................................ 149 12 RECOMMENDED OPERATING CONDITIONS ........................................................... 150 13 DC CHARACTERISTICS................................................................................................... 151 14 AC CHARACTERISTICS................................................................................................... 153 14.1 14.2 14.3 14.4 14.5 14.6 8 BIT 4 WIRE SPI INTERFACE TIMING ................................................................................................................154 8 BIT 3 WIRE SPI INTERFACE TIMING ................................................................................................................155 24 BIT 3 WIRE SPI INTERFACE TIMING ..............................................................................................................156 RGB INTERFACE TIMING ...................................................................................................................................157 RESET TIMING .................................................................................................................................................158 TX_CLK TIMING ..............................................................................................................................................158 15 POWER UP SEQUENCE .................................................................................................... 159 16 POWER OFF SEQUENCE ................................................................................................. 160 17 EXAMPLE FOR SYSTEM SLEEP IN AND OUT ........................................................... 161 18 SERIAL LINK DATA ORDER........................................................................................... 162 19 PACKAGE INFORMATION.............................................................................................. 165 19.1 DIMENSION FOR SSD2828QN4 .........................................................................................................................165 SSD2828QN4 Rev 1.3 P 5/168 Mar 2013 Solomon Systech TABLES TABLE 3-1: ORDERING INFORMATION .................................................................................................................................11 TABLE 6-1: SSD2828QN4 PINOUT DIAGRAM – 68 QFN-EP (TOP VIEW) ............................................................................18 TABLE 6-2: SSD2828QN4 PIN ASSIGNMENT – 68 QFN-EP (TOP VIEW) .............................................................................19 TABLE 6-3: SSD2828QN4 RGB DATA ARRANGEMENT .......................................................................................................19 TABLE 7-1: MIPI PINS .........................................................................................................................................................20 TABLE 7-2: INTERFACE LOGIC PINS .....................................................................................................................................21 TABLE 7-3: MISCELLANEOUS PINS ......................................................................................................................................22 TABLE 8-1: SSD2828 REGISTER SUMMARY ........................................................................................................................23 TABLE 8-2: DEVICE IDENTIFICATION REGISTER DESCRIPTION ............................................................................................25 TABLE 8-3: RGB INTERFACE CONTROL REGISTER 1 DESCRIPTION .....................................................................................26 TABLE 8-4: RGB INTERFACE CONTROL REGISTER 2 DESCRIPTION .....................................................................................27 TABLE 8-5: RGB INTERFACE CONTROL REGISTER 3 DESCRIPTION .....................................................................................28 TABLE 8-6: RGB INTERFACE CONTROL REGISTER 4 DESCRIPTION .....................................................................................29 TABLE 8-7: RGB INTERFACE CONTROL REGISTER 5 DESCRIPTION .....................................................................................30 TABLE 8-8: RGB INTERFACE CONTROL REGISTER 6 DESCRIPTION .....................................................................................31 TABLE 8-9: CONFIGURATION REGISTER DESCRIPTION ........................................................................................................33 TABLE 8-10: VC CONTROL REGISTER DESCRIPTION ...........................................................................................................35 TABLE 8-11: PLL CONTROL REGISTER DESCRIPTION..........................................................................................................36 TABLE 8-12: PLL CONFIGURATION REGISTER DESCRIPTION ..............................................................................................37 TABLE 8-13: CLOCK CONTROL REGISTER DESCRIPTION .....................................................................................................38 TABLE 8-14: PACKET SIZE CONTROL REGISTER 1 DESCRIPTION .........................................................................................39 TABLE 8-15: PACKET SIZE CONTROL REGISTER 2 DESCRIPTION .........................................................................................40 TABLE 8-16: PACKET SIZE CONTROL REGISTER 3 DESCRIPTION .........................................................................................41 TABLE 8-17: GENERIC PACKET DROP REGISTER DESCRIPTION ...........................................................................................42 TABLE 8-18: OPERATION CONTROL REGISTER DESCRIPTION ..............................................................................................43 TABLE 8-19: MAXIMUM RETURN SIZE REGISTER DESCRIPTION ..........................................................................................44 TABLE 8-20: RETURN DATA COUNT REGISTER DESCRIPTION .............................................................................................45 TABLE 8-21: ACK RESPONSE STATUS REGISTER DESCRIPTION ..........................................................................................46 TABLE 8-22: LINE CONTROL REGISTER DESCRIPTION .........................................................................................................47 TABLE 8-23: INTERRUPT CONTROL REGISTER DESCRIPTION ...............................................................................................49 TABLE 8-24: INTERRUPT STATUS REGISTER DESCRIPTION ..................................................................................................50 TABLE 8-25: ERROR STATUS REGISTER DESCRIPTION .........................................................................................................52 TABLE 8-26: DELAY ADJUSTMENT REGISTER 1 DESCRIPTION .............................................................................................54 TABLE 8-27: DELAY ADJUSTMENT REGISTER 2 DESCRIPTION .............................................................................................55 TABLE 8-28: DELAY ADJUSTMENT REGISTER 3 DESCRIPTION .............................................................................................56 TABLE 8-29: DELAY ADJUSTMENT REGISTER 4 0/1 DESCRIPTION .......................................................................................57 TABLE 8-30: DELAY ADJUSTMENT REGISTER 5 DESCRIPTION .............................................................................................58 TABLE 8-31: DELAY ADJUSTMENT REGISTER 6 DESCRIPTION .............................................................................................59 TABLE 8-32: HS TX TIMER REGISTER 1 DESCRIPTION ........................................................................................................60 TABLE 8-33: HS RX TIMER REGISTER 2 DESCRIPTION ........................................................................................................61 TABLE 8-34: LP TX TIMER REGISTER 1 DESCRIPTION ........................................................................................................62 TABLE 8-35: LP TX TIMER REGISTER 2 DESCRIPTION ........................................................................................................63 TABLE 8-36: TE STATUS REGISTER DESCRIPTION ...............................................................................................................64 TABLE 8-37: SPI READ REGISTER DESCRIPTION .................................................................................................................65 TABLE 8-38: PLL LOCK REGISTER DESCRIPTION ................................................................................................................66 TABLE 8-39: TEST REGISTER DESCRIPTION .........................................................................................................................67 TABLE 8-40: TE COUNT REGISTER DESCRIPTION ................................................................................................................69 TABLE 8-41: ANALOG CONTROL 1 REGISTER DESCRIPTION ................................................................................................70 TABLE 8-42: ANALOG CONTROL REGISTER 2 DESCRIPTION ................................................................................................71 TABLE 8-43: ANALOG CONTROL REGISTER 3 DESCRIPTION ................................................................................................72 TABLE 8-44: ANALOG CONTROL REGISTER 4 DESCRIPTION ................................................................................................73 TABLE 8-45: INTERRUPT OUTPUT CONTROL REGISTER DESCRIPTION .................................................................................74 TABLE 8-46: RGB INTERFACE CONTROL REGISTER 7 DESCRIPTION ...................................................................................75 TABLE 8-47: LANE CONFIGURATION REGISTER DESCRIPTION .............................................................................................76 TABLE 8-48: DELAY ADJUSTMENT REGISTER 7 DESCRIPTION .............................................................................................77 TABLE 8-49: PULL CONTROL REGISTER 1 DESCRIPTION .....................................................................................................78 TABLE 8-50: PULL CONTROL REGISTER 2 DESCRIPTION .....................................................................................................80 TABLE 8-51: PULL CONTROL REGISTER 3 DESCRIPTION .....................................................................................................81 SSD2828QN4 Rev 1.3 P 6/168 Mar 2013 Solomon Systech TABLE 8-52: CABC BRIGHTNESS CONTROL REGISTER 1 DESCRIPTION ..............................................................................82 TABLE 8-53: CABC BRIGHTNESS CONTROL REGISTER 2 DESCRIPTION ..............................................................................83 TABLE 8-54: CABC BRIGHTNESS STATUS REGISTER DESCRIPTION ....................................................................................84 TABLE 8-55: ENCODER CONTROL REGISTER DESCRIPTION .................................................................................................85 TABLE 8-56: VIDEO SYNC DELAY REGISTER DESCRIPTION .................................................................................................86 TABLE 8-57: TRIMMING REGISTER DESCRIPTION ................................................................................................................87 TABLE 8-58: GPIO1 REGISTER DESCRIPTION ......................................................................................................................89 TABLE 8-59: GPIO1 REGISTER DESCRIPTION ......................................................................................................................91 TABLE 8-60: DLYA01 REGISTER DESCRIPTION ..................................................................................................................93 TABLE 8-61: DLYA23 REGISTER DESCRIPTION ..................................................................................................................94 TABLE 8-62: DLYB01 REGISTER DESCRIPTION ..................................................................................................................95 TABLE 8-63: DLYB23 REGISTER DESCRIPTION ..................................................................................................................96 TABLE 8-64: DLYC01 REGISTER DESCRIPTION ..................................................................................................................97 TABLE 8-65: DLYC23 REGISTER DESCRIPTION ..................................................................................................................98 TABLE 8-66: ACR5 REGISTER DESCRIPTION .......................................................................................................................99 TABLE 8-67: READ REGISTER DESCRIPTION ......................................................................................................................101 TABLE 9-1: SSD2828 LANE MANAGEMENT ......................................................................................................................102 TABLE 9-2: OPERATION DURING VIDEO MODE BLLP PERIOD ..........................................................................................104 TABLE 9-3: DSI STATE CODE AND DC CHARACTERISTICS ................................................................................................105 TABLE 9-4: DATA LANE MODE ENTERING/EXITING SEQUENCES ......................................................................................106 TABLE 9-5: START-OF-TRANSMISSION SEQUENCE.............................................................................................................107 TABLE 9-6: END-OF-TRANSMISSION SEQUENCE ................................................................................................................107 TABLE 9-7: MIPI ESCAPE MODE ENTRY CODE .................................................................................................................110 TABLE 9-8: DATA TYPES FOR PROCESSOR-SOURCED PACKETS .........................................................................................118 TABLE 9-9: DATA TYPES FOR PERIPHERAL-SOURCED PACKETS ........................................................................................119 TABLE 9-10: PLL SETTING FOR NON-BURST MODE (PLL REFERENCE USING PCLK) .........................................................123 TABLE 9-11: PLL SETTING FOR NON-BURST MODE (PLL REFERENCE USING TX_CLK) .....................................................123 TABLE 9-12: PLL SETTING FOR BURST MODE...................................................................................................................124 TABLE 9-13: MIPI ERROR REPORT .....................................................................................................................................132 TABLE 11-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS) .................................................................................149 TABLE 12-1: RECOMMENDED OPERATING CONDITIONS ....................................................................................................150 TABLE 13-1: DC CHARACTERISTICS ..................................................................................................................................151 TABLE 13-2: HS TRANSMITTER DC CHARACTERISTICS ....................................................................................................152 TABLE 13-3: LP TRANSMITTER DC CHARACTERISTICS .....................................................................................................152 TABLE 13-4: LP RECEIVER DC CHARACTERISTICS ...........................................................................................................152 TABLE 14-1: 8 BIT 4 WIRE SPI INTERFACE TIMING CHARACTERISTICS.............................................................................154 TABLE 14-2: 8 BIT 3 WIRE SPI INTERFACE TIMING CHARACTERISTICS.............................................................................155 TABLE 14-3: 24 BIT 3 WIRE SPI INTERFACE TIMING CHARACTERISTICS...........................................................................156 TABLE 14-4: RGB INTERFACE TIMING CHARACTERISTICS ................................................................................................157 TABLE 14-5: RESET TIMING.............................................................................................................................................158 TABLE 14-6: TX_CLK TIMING CHARACTERISTICS ...........................................................................................................158 SSD2828QN4 Rev 1.3 P 7/168 Mar 2013 Solomon Systech FIGURES FIGURE 4-1: OVERVIEW OF DISPLAY SYSTEM USING SSD2828............................................................................................11 FIGURE 4-2: SSD2828 INTERFACE DIAGRAM ......................................................................................................................12 FIGURE 4-3: BLOCK DIAGRAM ............................................................................................................................................13 FIGURE 5-1: THE CLOCKING SCHEME OF SSD2828.............................................................................................................14 FIGURE 8-1: TIMING FOR DELAY CALCULATION ..................................................................................................................54 FIGURE 8-2: TIMING FOR DELAY CALCULATION ..................................................................................................................55 FIGURE 8-3: TWAKEUP PERIOD DELAY CALCULATION ............................................................................................................58 FIGURE 8-4: TIMING FOR DELAY CALCULATION ..................................................................................................................59 FIGURE 9-1: SSD2828 WITH RGB AND SPI INTERFACE ....................................................................................................103 FIGURE 9-2: MIPI LINE LEVELS ........................................................................................................................................105 FIGURE 9-3: SWITCHING THE CLOCK LANE BETWEEN HIGH SPEED MODE AND LOW-POWER MODE ................................106 FIGURE 9-4: HIGH-SPEED DATA TRANSMISSION IN BURSTS ..............................................................................................108 FIGURE 9-5: TURNAROUND PROCEDURE ...........................................................................................................................109 FIGURE 9-6: LOW POWER DATA TRANSMISSION ...............................................................................................................111 FIGURE 9-7: TRIGGER – RESET COMMAND IN ESCAPE MODE ............................................................................................112 FIGURE 9-8: TEARING EFFECT COMMAND IN ESCAPE MODE .............................................................................................113 FIGURE 9-9: ACKNOWLEDGE COMMAND IN ESCAPE MODE ...............................................................................................114 FIGURE 9-10: TWO DATA TRANSMISSION MODE (SEPARATE, SINGLE)..............................................................................115 FIGURE 9-11: ONE LANE DATA TRANSMISSION EXAMPLE ................................................................................................115 FIGURE 9-12: TWO LANE HS TRANSMISSION EXAMPLE ....................................................................................................115 FIGURE 9-13: ENDIAN EXAMPLE (LONG PACKET) .............................................................................................................116 FIGURE 9-14: LONG PACKET STRUCTURE ..........................................................................................................................116 FIGURE 9-15: SHORT PACKET STRUCTURE ........................................................................................................................117 FIGURE 9-16: DATA INDENTIFIER STRUCTURE ..................................................................................................................117 FIGURE 9-17: 16-BIT PER PIXEL RGB COLOR FORMAT, LONG PACKET FOR MIPI INTERFACE ...........................................120 FIGURE 9-18: 18-BIT PER PIXEL– RGB COLOR FORMAT, LONG PACKET FOR MIPI INTERFACE .........................................120 FIGURE 9-19: 18-BIT PER PIXEL IN THREE BYTES – RGB COLOR FORMAT, LONG PACKET FOR MIPI INTERFACE .............121 FIGURE 9-20: 24-BIT PER PIXEL – RGB COLOR FORMAT, LONG PACKET FOR MIPI INTERFACE ........................................121 FIGURE 9-21: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC PULSES .................122 FIGURE 9-22: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC EVENTS AND BURST MODE ........................................................................................................................................................................123 FIGURE 9-23: NON-BURST MODE MIPI STRUCTURE ..........................................................................................................124 FIGURE 9-24: BURST MODE MIPI STRUCTURE ...................................................................................................................125 FIGURE 9-25: ACKNOWLEDGEMENT HANDLING AFTER NON-READ COMMAND ................................................................130 FIGURE 9-26: ACKNOWLEDGEMENT HANDLING AFTER READ COMMAND .........................................................................131 FIGURE 9-27: ILLUSTRATION OF INTERRUPT LATENCY ......................................................................................................134 FIGURE 10-1: ILLUSTRATION OF WRITE OPERATION FOR 8 BIT 4 WIRE INTERFACE ...........................................................140 FIGURE 10-2: ILLUSTRATION OF READ OPERATION FOR 8 BIT 4 WIRE INTERFACE ............................................................140 FIGURE 10-3: ILLUSTRATION OF WRITE OPERATION FOR 8 BIT 3 WIRE INTERFACE ...........................................................141 FIGURE 10-4: ILLUSTRATION OF READ OPERATION FOR 8 BIT 3 WIRE INTERFACE ............................................................142 FIGURE 10-5: ILLUSTRATION OF WRITE OPERATION FOR 24 BIT 3 WIRE INTERFACE .........................................................145 FIGURE 10-6: ILLUSTRATION OF READ OPERATION FOR 24 BIT 3 WIRE INTERFACE ..........................................................146 FIGURE 14-1: 8 BIT 4 WIRE SPI INTERFACE TIMING DIAGRAM .........................................................................................154 FIGURE 14-2: 8 BIT 3 WIRE SPI INTERFACE TIMING DIAGRAM .........................................................................................155 FIGURE 14-3: 24 BIT 3 WIRE SPI INTERFACE TIMING DIAGRAM .......................................................................................156 FIGURE 14-4: RGB INTERFACE TIMING DIAGRAM ............................................................................................................157 FIGURE 14-5: TX_CLK TIMING DIAGRAM ........................................................................................................................158 FIGURE 18-1- PACKAGE INFORMATION .............................................................................................................................165 FIGURE 18-2- MARKING INFORMATION .............................................................................................................................166 FIGURE 18-3- TRAY INFORMATION ....................................................................................................................................167 SSD2828QN4 Rev 1.3 P 8/168 Mar 2013 Solomon Systech 1 GENERAL DESCRIPTION The SSD2828 IC is an MIPI master bridge chip that connects an application processor with traditional parallel LCD interface and an LCD driver with MIPI slave interface. The 2828 supports up to 1Gbps per lane speed with maximum 4 lanes using both parallel RGB interface and serial SPI interface. SSD2828QN4 Rev 1.3 P 9/168 Mar 2013 Solomon Systech 2 FEATURES • • • • • • • • • • • • • • • • • 2.1 Support up to total of 4Gbps over the serial link Support up to 4 data lanes Number of signals is significantly reduced when compare to traditional RGB transfer Support up to 1920 pixels per display row in Video mode, up to 60hz refresh rate Support up to 2560 pixels per display row in Video mode, up to 30hz refresh rate Reduce power consumption and decrease EMI by using low amplitude signal over differential pair for serial data. Support parallel RGB interface (DPI 2.0) up to 24-bits Support serial SPI interface (DBI 2.0) up to 16-bits Support both command mode and video mode in MIPI DSI standard Support 16, 18 and 24-bit per pixel in Raw or Pixel mode for command mode transfer Support independent bi-directional data transfer (forward link in High Speed and Low Power mode and reverse link in Low Power mode) for each DSI Support Ultra low power mode in idle state for each DSI Support CABC function for Video mode On-chip PLL with variable output frequency MIPI analog and digital power supply: (MVDD) 1.2V +/-10% IO Power supply: (VDDIO) 1.8 ~ 3.3V +/-10% Support of MIPI standard DSI(v1.01.00), DCS(v1.02.00), D-PHY (v1.00.00) References • • • • • 2.2 MIPI Alliance Standard for Display Serial Interface, version 1.01 MIPI Alliance Standard for Display Command Set, version 1.02 MIPI Alliance Standard for D-PHY, version 1.00 MIPI Alliance Standard for Display Bus Interface, version 2.0 MIPI Alliance Standard for Display Pixel Interface, version 2.0 Definitions • • • • • • HS SPI LP ULPS RGB VC SSD2828QN4 High Speed Type C interface option 1 of MIPI Alliance Standard for Display Bus Interface v2.0 (DBI-2) Low Power Ultra Low Power State MIPI Alliance Standard for Display Pixel Interface v2.0 (DPI-2) Virtual Channel Rev 1.3 P 10/168 Mar 2013 Solomon Systech 3 ORDERING INFORMATION Table 3-1: Ordering Information Ordering Part Number Package Form SSD2828QN4 4 68 QFN-EP (in Tray form) BLOCK DIAGRAM The SSD2828 IC consists of the following modules. • • • • • • • • • Clock and reset module External interface PCU (protocol control unit) PPU (packet processing unit) ECC/CRC Long and command buffers D-PHY controller Analog MIPI transceiver Internal PLL The usage of SSD2828 is given in the diagram below. Application processor SSD2828 LCD driver with MIPI slave interface Parallel LCD interface or Serial SPI interface Figure 4-1: Overview of display system using SSD2828 SSD2828QN4 Rev 1.3 P 11/168 Mar 2013 Solomon Systech Below is the interface diagram for the SSD2828 driving MIPI slave panel. Three types of interface are supported which are RGB and SPI interfaces. The interfaces can be selected through ps[1:0] pins. MIPI Serial Link 1Gbps per lane cm shut pclk vsync hsync den data[23:0] RGB SPI csx SPI sdc sck sdin Control/ Config dp3 dn3 dp2 dn2 dp1 dn1 Datap3 Datan3 Datap2 Datan2 Datap1 Datan1 dp0 dn0 Datap0 Datan0 cp cn Clkp Clkn ps[1:0] Power Ground Power Ground Reset mipi_reset_b SSD2828 MIPI receiver Figure 4-2: SSD2828 Interface Diagram SSD2828QN4 Rev 1.3 P 12/168 Mar 2013 Solomon Systech Figure 4-3: Block Diagram PLL Clock and Reset module Long and Command Buffers ECC/CRC External Interface Protocol Control Unit Packet Processing Unit D-PHY Controller Analog Transceiver SSD2828QN4 Rev 1.3 P 13/168 Mar 2013 Solomon Systech 5 FUNCTIONAL DESCRIPTION 5.1 Functional Blocks 5.2 Clock and Reset Module The clock and reset module controls the generation of the operation clock for the whole system. There are two reference clock sources for the PLL. One is from the tx_clk and the other is from the pclk. The application processor can choose the reference clock for the PLL by program the CSS. The PLL output clock is used to generate the clock and data on the serial link during HS mode. The PLL frequency is the same as the data rate on 1 data lane. Hence, the PLL needs to be programmed according to the HS speed. Please refer to 9.3.5 for how to program the PLL. NOTE: The default value of the CSS is 0 which selects the tx_clk. Hence, after power up, tx_clk must be present so that the registers can be programmed. If the application processor wants to switch the clock source, tx_clk must be provided first so that the CSS field can be programmed. After the CSS is programmed, the tx_clk can be turned off. After powering up, the PLL is in sleep mode. The host needs to program the PLL setting before enable the PLL. If the host needs to switch the clock source of the PLL, it needs to put the PLL into sleep mode first. Afterwards, the host needs to program the PLL with new setting and enable the PLL. In both cases, the PLL needs a certain amount of time to lock the output clock frequency after being enabled. Hence, when the PLL is in sleep mode or when the PLL is enabled but not locked, the whole system is operating using the reference clock. After the PLL gets locked, the system is operating using the PLL output clock. Please see the diagram below for detailed clocking scheme. Since the reference clock is much slower than the PLL output clock, the host needs to operate at low speed too, before the PLL gets locked. Please refer to 14 for the requirement of low speed and normal speed. Reference clock Operating clock pclk xtal_in xtal_io 1 1 OSC 0 PLL 0 tx_clk CSS XTAL_MODE Lock Lock Detector Figure 5-1: The Clocking Scheme of SSD2828 An output lock signal is provided for indication. This signal is connected to one of the interrupt source. The host can use the interrupt signal int to decide whether to operate at low speed or normal speed. The host can also poll the status bit PLS for the lock status. Various clocks are mentioned in this document. Below is the explanation for each of them. • Bit clock It is the output clock from PLL. It is the clock source of all the clocks in the SSD2828. SSD2828QN4 Rev 1.3 P 14/168 Mar 2013 Solomon Systech • Nibble clock It is a clock whose frequency is 1/4 of the bit clock. • Byte clock It is a clock whose frequency is 1/8 of the bit clock. • Low power clock It is a clock generated from byte clock. The divider value is given by field LPD. Please refer to 8.1.12. The low power clock period corresponds to 2 x TLPX, as defined in MIPI D-PHY specification. 5.3 External Interface The external interface is in charge of the communication with the application processor. It supports 2 types of interface, which are RGB and SPI. • Parallel RGB interface for dumb display controller. The data bus width can be 16-bit, 18-bit and 24-bit. • Serial SPI interface for smart display controller. The SPI interface supports 3 modes, which are 8-Bit 3 wire, 8Bit 4 wire and 24-bit 3 wire. The 8-Bit 3 wire mode is the type C option 1 interface as specified in MIPI DBI 2.0. The 8-Bit 4 wire mode is the type C option 3 interface as specified in MIPI DBI 2.0. The SPI interface is a completely separate interface from the other. Please see the pin table description for detailed scheme. The SSD2828 supports one interface configuration. • A combination of RGB and SPI interface This configuration is mainly used to drive a dumb display panel through the MIPI link. The RGB interface inputs the display data to the dumb display. The SPI interface inputs the data which is to configure the dumb display. Alternatively, the SPI interface can also input the data which is to drive a smart display panel, if the MIPI slave can control a dumb display panel and a smart one at the same time. 5.4 Protocol Control Unit (PCU) The PCU is in charge of the handling of outgoing and incoming data stream. It has a state machine to decide what packet to be sent when an event comes in and how to react to the received packet. 5.5 Packet Processing Unit (PPU) The PPU is in charge of packet assembly and disassembly. During transmission, it will form the packet according to the instruction from the PCU. During reception, it will extract necessary information from the packet and pass to the PCU. SSD2828QN4 Rev 1.3 P 15/168 Mar 2013 Solomon Systech 5.6 Error Correction Code/ Cyclic Redundancy Check (ECC/CRC) During transmission, the ECC/CRC module will generate the ECC or CRC for the outgoing bit stream. During reception, the ECC/CRC module will check the correctness of the ECC and CRC field of the incoming stream. If there is 1 bit of error in the data and ECC field, this error will be corrected by the ECC module. If there are more than 1 bit of error in the data and ECC field, the ECC module will detect the error and report it. If there is at least 1 bit of error in the data and CRC field, the CRC module will detect the error and report it. 5.7 Long and Command Buffers In the forward direction, the SSD2828 supports DCS short write, DCS long write, Generic short write, Generic long write packets and all video packets. The internal buffers are used as temporary storage for incoming data, so that the application processor does not need to wait for the packet to be transmitted before writing the next one. All the command packets will be stored in the command buffers, except DCS command 2C/3C. All the long packets in video mode and the long packets with DCS command 2C/3C in command mode will be stored in the long buffer. After a complete packet is written into the buffer, the SSD2828 will send out the packet. The command buffer can contain one or multiple packets, up to the size of 1024 bytes. As long as 1 complete packet is received, the state machine will instructs the D-PHY Controller to send out the packet. Each long buffer can contain, maximum, 2 packets. For each buffer, there are 2 status bits associated. One is buffer empty and the other is buffer available. Buffer empty means there is no packet in the buffer. Buffer available means that there is space to hold at least one packet. The buffer status can be reflected to the application processor through interrupt signal. 5.8 Interrupt signal An interrupt signal is provided to trigger the application processor for certain event in the SSD2828. The events include internal long or command buffer empty, internal long or command buffer available, data ready for read back, acknowledgement response from MIPI slave, BTA response from the MIPI slave, time out, and packet operation ready. Please see the interrupt register description and 9.3.1.6 for more details. 5.9 D-PHY Controller The D-PHY controller is in charge of the communication with the analog transceiver. During transmission, it receives data from PPU and informs the analog transmitter how to transmit. During reception, it receives data from analog receiver and passes the data to the PPU for further processing. At the same time, it is also performing the handshaking process, such as, bus turn around and switching between different modes. 5.10 Analog Transceiver It consists of 4 data lane controllers and 1 clock lane controller. 1 of the data lane controllers is capable of providing reverse transmission. SSD2828QN4 Rev 1.3 P 16/168 Mar 2013 Solomon Systech 5.11 Internal PLL The internal PLL will generate the required high speed clock for the whole system operation. The input reference clock can come from either the tx_clk (_XIN, _XIO) or the pclk. SSD2828QN4 Rev 1.3 P 17/168 Mar 2013 Solomon Systech 6 SSD2828QN4 Pin Assignment Table 6-1: SSD2828QN4 Pinout Diagram – 68 QFN-EP (Top view) SSD2828QN4 Rev 1.3 P 18/168 Mar 2013 Solomon Systech Table 6-2: SSD2828QN4 Pin Assignment – 68 QFN-EP (Top view) QFN pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Net name DATAP0 DATAN0 GND DATAP1 DATAN1 GND CLKP CLKN GND DATAP2 DATAN2 GND DATAP3 DATAN3 MVDD VDDIO PS0 PS1 NC NC NC RESET SDO SDI SCK SDC SHUT DEN HSYNC PCLK MVDD GND VDDIO VSYNC QFN pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Net name DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 CSX0 MVDD SYS_CLK_OUT TX_CLK_XIO TX_CLK_XIN VDDIO GND MVDD GND VDDIO Table 6-3: SSD2828QN4 RGB data arrangement D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 24bpp R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 18bpp X X X X X X R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 16bpp X X X X X X X X R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 SSD2828QN4 Rev 1.3 P 19/168 Mar 2013 Solomon Systech 7 Pin Description SSD2828 Pin Function Description Key: I = Input O =Output I/O = Bi-directional (input/output) P = Power pin GND = System VSS Table 7-1: Power Supply Pins Name Type Connect to GND P GND Ground of Power Supply Power for Analog/Digital Circuits and PLL Circuit Power for IO and Digital Interface Circuits MVDD P Function Power VDDIO Description When not in use Ground for IC - Power supply for the internal analog/digital circuit and PLL circuit. (1.2V +/-10%) Power supply for IO and digital interface circuit. (1.8~3.3V +/-10%) Table 7-1: MIPI Pins Name Type Connect to Function CLKP0 Description When not in use Positive differential clock signal for DSI_0 O CLKN0 Negative differential clock signal for DSI_0 DATAP0 Positive differential data signal 0 for DSI_0 I/O DATAN0 Negative differential data signal 0 for DSI_0 DATAP1 O MIPI Rx DATAN1 MIPI Signals DATAP2 Positive differential data signal 1 for DSI_0 Open Negative differential data signal 1 for DSI_0 Positive differential data signal 2 for DSI_0 O DATAN2 Negative differential data signal 2 for DSI_0 DATAP3 Positive differential data signal 3 for DSI_0 O DATAN3 SSD2828QN4 Negative differential data signal 3 for DSI_0 Rev 1.3 P 20/168 Mar 2013 Solomon Systech Table 7-2: Interface Logic Pins Name Type DATA[23:0] I/O Connect to Function VSYNC Description When not in use RGB data for RGB interface Open VDDIO or GND VDDIO or GND VDDIO or GND VDDIO or GND VDDIO or GND VDDIO VSYNC for RGB interface RGB Interface PCLK DEN PCLK for RGB interface DEN for RGB interface AP HSYNC HSYNC for RGB interface I SDC Data or command for SPI interface (for 8 bit 4 wire) CSX0 Chip select of DSI_0 for SPI interface SPI Interface SCK SDI SDO SSD2828QN4 O - Rev 1.3 P 21/168 Mar 2013 Serial data input for SPI interface (for 8 bit 3 wire, 8 bit 4 wire, 24 bit 3 wire) VDDIO or GND VDDIO or GND Serial data output for SPI interface (for 8 bit 3 wire, 8 bit 4 wire, 24 bit 3 wire) Open Serial clock for SPI interface (for 8 bit 3 wire, 8 bit 4 wire, 24 bit 3 wire) Solomon Systech Table 7-3: Miscellaneous Pins Name Type Connect to Function SHUT VDDIO or GND PS[1:0] I External CLK TX_CLK_XIN Control Signal When not in use Description Shutdown signal of RGB interface (to put the driver into sleep mode). - 1: The panel is shut down (Sending 22h packet when SHUT changes from “0” Æ “1” in video mode) - 0: The panel is operating (Sending 32h packet at the beginning of video mode automatically) Interface selection signal PS[1:0] is for SPI interface - 00: 3 wire 24 bit SPI interface - 01: 3 wire 8 bit SPI interface - 10: 4 wire 8 bit SPI interface - 11: SSL internal test mode Input system clock. 8 ~ 30MHz ----------------------------------------------------------------------Input crystal range for the crystal oscillator input. 8Mhz to 30Mhz Input system clock. Open. ----------------------------------------------------------------------Input crystal range for the crystal oscillator input. 8Mhz to 30Mhz VDDIO GND - TX_CLK_XIO I/O - SYS_CLK_OUT O - Output system clock for MIPI slave Open RESET I VDDIO or GND Active low reset signal to the chip VDDIO SSD2828QN4 Rev 1.3 P 22/168 Mar 2013 Open Solomon Systech 8 COMMAND TABLE Table 8-1: SSD2828 Register Summary Offset 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 SSD2828QN4 Name Device Identification Register RGB Interface Control Register 1 RGB Interface Control Register 2 RGB Interface Control Register 3 RGB Interface Control Register 4 RGB Interface Control Register 5 RGB Interface Control Register 6 Configuration Register VC Control Register PLL Control Register PLL Configuration Register Clock Control Register Packet Size Control Register 1 Packet Size Control Register 2 Packet Size Control Register 3 Packet Drop Register Operation Control Register Maximum Return Size Register Return Data Count Register ACK Response Register Line Control Register Interrupt Control Register Interrupt Status Register Error Status Register Delay Adjustment Register 1 Delay Adjustment Register 2 Delay Adjustment Register 3 Delay Adjustment Register 4 Delay Adjustment Register 5 Delay Adjustment Register 6 HS TX Timer Register 1 HS TX Timer Register 2 LP RX Timer Register 1 LP RX Timer Register 2 TE Status Register SPI Read Register PLL Lock Register Test Register TE Count Register Analog Control Register 1 Analog Control Register 2 Analog Control Register 3 Analog Control Register 4 Interrupt Output Control Register RGB Interface Control Register 7 Lane Configuration Register Delay Adjustment Register 7 Pull Control Register 1 Pull Control Register 2 Pull Control Register 3 Rev 1.3 P 23/168 Mar 2013 Mnemonic DIR VICR1 VICR2 VICR3 VICR4 VICR5 VICR6 CFGR VCR PCR PLCR CCR PSCR1 PSCR2 PSCR3 PDR OCR MRSR RDCR ARSR LCR ICR ISR ESR DAR1 DAR2 DAR3 DAR4 DAR5 DAR6 HTTR1 HTTR2 LRTR1 LRTR2 TSR LRR PLLR TR TECR ACR1 ACR2 ACR3 ACR4 IOCR VICR7 LCFR DAR7 PUCR1 PUCR2 PUCR3 Reset Value 0x2828 0x020A 0x0214 0x0428 0x0780 0x0438 0x0024 0x0301 0x0045 0x0000 0x8120 0x0003 0x0000 0x0000 0x0100 0x0000 0x0000 0x0001 0x0000 0x0000 0x0000 0x0080 0xCF06 0x0000 0x1402 0x2803 0x0416 0x0A0A 0x1000 0x0405 0x0000 0x0010 0x0000 0x0010 0x0000 0x00FA 0x1450 0x0005 0x0001 0x2020 0x64A0 0x99A4 0x8098 0x0000 0x0000 0x0000 0x0010 0x5556 0x6656 0x0159 Solomon Systech Offset 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xFF SSD2828QN4 Name CABC Brightness Control Register 1 CABC Brightness Control Register 2 CABC Brightness Status Register Encoder Control Register Video Sync Delay Register Trimming Register GPIO Register 1 GPIO Register 2 DLYA01 Register DLYA23 Register DLYB01 Register DLYB23 Register DLYC01 Register DLYC23 Register Analog Control Register 5 Read Register Rev 1.3 P 24/168 Mar 2013 Mnemonic CBCR1 CBCR2 CBSR ECR VSDR TMR GPIO1 GPIO2 DLYA01 DLYA23 DLYB01 DLYB23 DLYC01 DLYC23 ACR5 RR Reset Value 0x0000 0x6900 0x0000 0x7800 0x0002 0x0000 0x0000 0x0000 0x2020 0x2020 0x2020 0x2020 0x2020 0x2020 0x0000 0x0000 Solomon Systech 8.1 Register Description 8.1.1 Device Identification Register Offset Address DIR BIT Device Identification Register 15 14 13 12 NAME 11 10 9 8 3 2 1 0 DIR[15:8] TYPE RO RESET 0x28 BIT 0xB0 7 6 5 4 NAME DIR[7:0] TYPE RO RESET 0x28 Table 8-2: Device Identification Register Description Name DIR Bit 15-0 SSD2828QN4 Description Device Identification Number Rev 1.3 P 25/168 Mar 2013 Setting 0x2828 Solomon Systech 8.1.2 RGB Interface Control Register 1 Offset Address VICR1 BIT RGB Interface Control Register 1 15 14 13 12 NAME 11 10 9 8 3 2 1 0 VSA TYPE RW RESET 0x02 BIT 0xB1 7 6 5 4 NAME HSA TYPE RW RESET 0x0A Table 8-3: RGB Interface Control Register 1 Description Name VSA Bit 15-8 HSA Bit 7-0 SSD2828QN4 Description Vertical Sync Active Period – These bits specify the Vsync active period. The Vsync active period is from the Vsync falling edge to rising edge, in terms of Hsync pulses. It is only used in non-burst mode with Sync pulses. Please refer to 9.3 for more details. Horizontal Sync Active Period – These bits specify the Hsync active period. The Hsync active period is from the Hsync falling edge to rising edge, in terms of pclk. It is only used in non-burst mode with Sync pulses. Please refer to 9.3 for more details. Rev 1.3 P 26/168 Mar 2013 Setting The minimum value is 1. The minimum value is 1. Solomon Systech 8.1.3 RGB Interface Control Register 2 Offset Address VICR2 BIT RGB Interface Control Register 2 15 14 13 12 NAME 11 10 9 8 3 2 1 0 VBP TYPE RW RESET 0x02 BIT 0xB2 7 6 5 4 NAME HBP TYPE RW RESET 0x14 Table 8-4: RGB Interface Control Register 2 Description Name VBP Bit 15-8 HBP Bit 7-0 SSD2828QN4 Description Vertical Back Porch Period – These bits specify the vertical back porch period in terms of Hsync pulses. The vertical back porch period depends on the video mode setting. If the mode is non-burst mode with Sync pulses, it is from the Vsync rising edge to the Hsync of the first line of active display. If the mode is non-burst mode with Sync events, it is from the Vsync falling edge to the Hsync of the first line of active display. If the mode is burst mode, it is the same as the non-burst mode with Sync events. Please refer to 9.3 for more details. Horizontal Back Porch Period – These bits specify the horizontal back porch period in terms of pclk. The horizontal back porch period depends on the non-burst mode setting. If the mode is non-burst mode with Sync pulses, it is from the Hsync rising edge to the start of the valid display pixel. If the mode is non-burst mode with Sync events, it is from the Hsync falling edge to the start of the valid display pixel. If the mode is burst mode, it is the same as the non-burst mode with Sync events. Please refer to 9.3for more details. Rev 1.3 P 27/168 Mar 2013 Setting Solomon Systech 8.1.4 RGB Interface Control Register 3 Offset Address VICR3 BIT RGB Interface Control Register3 15 14 13 12 NAME 11 10 9 8 3 2 1 0 VFP TYPE RW RESET 0x04 BIT 0xB3 7 6 5 4 NAME HFP TYPE RW RESET 0x28 Table 8-5: RGB Interface Control Register 3 Description Name VFP Bit 15-8 HFP Bit 7-0 SSD2828QN4 Description Vertical Front Porch Period – These bits specify the vertical front porch period in terms of Hsync pulses. The vertical front porch period is from the first Hsync after the last line of active display to the next Vsync falling edge. Please refer to 9.3 for more details. Horizontal Front Porch Period – These bits specify the horizontal front porch period in terms of pclk. The horizontal front porch period is from the end of the valid display pixel to the next Hsync falling edge. Please refer to 9.3 for more details. Rev 1.3 P 28/168 Mar 2013 Setting Solomon Systech 8.1.5 RGB Interface Control Register 4 Offset Address VICR4 BIT RGB Interface Control Register 4 15 14 13 12 NAME 11 10 9 8 2 1 0 HACT[15:8] TYPE RW RESET 0x07 BIT 0xB4 7 6 5 4 NAME 3 HACT[7:0] TYPE RW RESET 0x80 Table 8-6: RGB Interface Control Register 4 Description Name HACT Bit 15-0 SSD2828QN4 Description Horizontal Active Period – These bits specify the horizontal active period in terms of pclk. During the horizontal active period, the den signal should always be high. Please refer to 9.3 for more details. Rev 1.3 P 29/168 Mar 2013 Setting The maximum value is 0x0A00. Solomon Systech 8.1.6 RGB Interface Control Register 5 Offset Address VICR5 BIT RGB Interface Control Register 5 15 14 13 12 NAME 11 10 9 8 2 1 0 VACT[15:8] TYPE RW RESET 0x04 BIT 0xB5 7 6 5 4 NAME 3 VACT[7:0] TYPE RW RESET 0x38 Table 8-7: RGB Interface Control Register 5 Description Name VACT Bit 15-0 SSD2828QN4 Description Vertical Active Period – These bits specify the vertical active period in terms of Hsync pulses. Please refer to 9.3 for more details. Rev 1.3 P 30/168 Mar 2013 Setting The minimum value is 1. Solomon Systech 8.1.7 RGB Interface Control Register 6 Offset Address VICR6 RGB Interface Control Register6 12 11 0xB6 BIT 15 14 13 NAME VS_P HS_P PCLK_P 10 9 8 TYPE RW RW RW RO RO RO RO RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 3 2 1 CBM BIT 7 6 5 4 NAME NVB NVD BLLP VCS VM VPF 0 TYPE RW RW RW RW RW RW RESET 0x0 0x0 0x1 0x0 0x1 0x0 Table 8-8: RGB Interface Control Register 6 Description Name VS_P Bit 15 VS_P – This bit control the polarity of the Vsync pulse input. Setting 0 – Vsync Pulse is active low 1 – Vsync Pulse is active high HS_P Bit 14 HS_P – This bit control the polarity of the Hsync pulse output. 0 – Hsync Pulse is active low 1 – Hsync Pulse is active high PCLK_P Bit 13 PCLK_P – This bit control the polarity of the CM output. 0 – Data is launch at falling edge, SSD2828 latch data at rising edge 1 – Data is launch at rising edge, SSD2828 latch data at falling edge Compress Burst Mode Control – If the mode is burst and this bit is 1, MIPITX will send video packet in compressed burst mode (i.e. no blanking packet after horizontal sync packet) Non Video Data Burst Mode Control – This bit specifies how non video data will be interleaved with video data transmission in burst mode. 0 – Video with blanking packet. 1 - Video with no blanking packet. Reserved Bit 12-9 CBM Bit 8 NVB Bit 7 NVD Bit 6 Description Non Video Data Transmission Control –This bit specifies how non video data will be interleaved with video data transmission. Please refer to 9.2.1 for more details. 0 – Non video data will be transmitted during any BLLP period. 1 - Non video data will only be transmitted during vertical blanking period. 0 – Non video data will be transmitted using HS mode. 1 – Non video data will be transmitted using LP mode. The SSD2828 will send non video data (written from the SPI interface) during the vertical blanking period (non burst mode) or any BLLP period in burst mode (depends on NVB setting). The data can be sent either in high speed mode or low power mode. This bit selects which mode to use. If LP mode is selected, the data SSD2828QN4 Rev 1.3 P 31/168 Mar 2013 Solomon Systech Name Description lane will enter LP mode for BLLP period, even if there is no non-video data to send. Please note that sending data in LP mode is much slower than HS mode. It is the responsibility of the host processor to make sure that the duration is long enough to finish the data transfer and the timing of Hsync and Vsync is not affected. BLLP Control – This bit specifies the SSD2828 operation during BLLP period. This bit takes effect only for non burst mode and NVD being 0. When the video mode is burst mode, the SSD2828 will not send any blanking packet during BLLP. It will enter LP mode. When NVD is 1 in non burst mode, the SSD2828 will stay in LP mode after sending the non video data (if there is any), until the BLLP period ends. When NVD is 0 in non burst mode, the SSD2828 will use this bit to decide whether to send blanking packet or enter LP mode after sending non video data (if there is any), until the BLLP period ends. Please note that entering and exiting from LP mode needs more time, as the speed of LP mode is slow. It is the responsibility of the host processor to make sure that the period is long enough to finish the data transfer and the timing of Hsync and Vsync is not affected. Video Clock Suspend – This bit specifies the clock lane behavior. This bit is only applicable for burst mode. When the video mode is non burst mode, the clock lane will remain in HS mode all the time. BLLP Bit 5 VCS Bit 4 VM Bit 3-2 Video Mode – These bits specify the video mode the SSD2828 will use, when RGB interface is selected. Please refer to MIPI DSI for the definition of different modes. VPF Bit 1-0 Video Pixel Format – These bits specify the pixel format for video mode. Setting 0 – Blanking packet will be sent during BLLP period. 1 – LP mode will be used during BLLP period. 0 – The clock lane remains in HS mode, when there is no data to transmit. 1 – The clock lane enters LP mode when there is no data to transmit. 00 – Non burst mode with sync pulses 01 – Non burst mode with sync events 10 – Burst mode 11 – Reserved 00 – 16bpp 01 – 18bpp, packed 10 – 18bpp, loosely packed 11 – 24bpp 24bpp D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 18bpp X X X X X X 16bpp X X X X X X SSD2828QN4 Rev 1.3 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 32/168 X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Mar 2013 Solomon Systech 8.1.8 Configuration Register Offset Address CFGR Configuration Register BIT 15 14 13 12 NAME 0xB7 11 10 9 8 TXD LPE EOT ECD TYPE RO RO RO RO RW RW RW RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 BIT 7 6 5 4 3 2 1 0 NAME REN DCS CSS HCLK VEN SLP CKE HS TYPE RW RW RW RW RW RW RW RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 Table 8-9: Configuration Register Description Name Reserved Bit 15-12 TXD Bit 11 LPE Bit 10 EOT Bit 9 ECD Bit 8 REN Bit 7 DCS Bit 6 SSD2828QN4 Description Transmit Disable – This bit specifies whether the SSD2828 will disable the sending of MIPI Packets stored in the buffers. Software can enable TXD, fill out the buffers and then disable it to send all packets out in 1 burst. Long Packet Enable – This bit specifies whether the SSD2828 will send out a Generic Long Write Packet or Generic Short Write Packet when the payload is no more than 2 bytes. It also specifies whether the SSD2828 will send out a DCS Long Write Packet or DCS Short Write Packet when the payload is no more than 1 byte. EOT Packet Enable – This bit specifies whether the SSD2828 will send out the EOT packet at the end of HS transmission or not. ECC CRC Check Disable – This bit specifies whether SSD2828 will perform ECC and CRC checking for the packets received from the MIPI slave. Read Enable –This bit specifies whether the next operation is a write or read operation. DCS Enable – This bit specifies whether the packet to be sent is DCS packet or generic packet. This bit applies for both write and read operation. Rev 1.3 P 33/168 Mar 2013 Setting 0 – Transmit on 1 – Transmit halt 0 – Short Packet 1 – Long Packet 0 – Do not send 1 – Send 0 – Enable 1 – Disable 0 – Write operation 1 – Read operation 0 – Generic packet (The packet can be any one of Generic Long Write, Generic Short Write, Generic Read packet, depending on the configuration.) 1 – DCS packet (The packet can be any one of DCS Long Write, DCS Short Write, DCS Read packet, depending on the configuration.) Solomon Systech Name CSS Bit 5 HCLK Bit 4 VEN Bit 3 SLP Bit 2 CKE Bit 1 HS Bit 0 SSD2828QN4 Description Clock Source Select – This bit selects the clock source for the PLL. Please refer to 5.2 for the system behavior when the clock source is switched. The CSS setting should be programmed only when PEN is 0. It has no effect when PEN is 1. HS Clock Disable – This bit controls the clock lane behavior during the reverse direction communication. This bit takes effect only when CKE is 0 and VEN is 0. Video Mode Enable – This bit controls the video mode operation. Only after this bit is set to 1, video mode is enabled. This bit takes effect only when the interface setting is RGB + SPI. Please refer to 0 for the video mode operation. Sleep Mode Enable – This bit controls the sleep mode operation. Please refer to 9.3.2 for the sleep mode operation. When this bit is set to 1, the HS bit will be cleared to 0 automatically. Clock Lane Enable – This bit controls the clock lane mode when data lane enters LP mode. HS Mode – This bit controls whether the SSD2828 is using HS or LP mode to send data. This bit can be affected by the SLP bit value. Rev 1.3 P 34/168 Mar 2013 Setting 0 – The clock source is tx_clk 1 – The clock source is pclk 0 – HS clock is enabled 1 – HS clock is disabled 0 – Video mode is disabled 1 – Video mode is enabled 0 – Sleep mode is disabled 1 – Sleep mode is enabled. Only the register interface is active. 0 – Clock lane will enter LP mode, if it is not in reverse direction communication. Clock lane will follow the setting of HCLK, if it is in reverse direction communication. 1 – Clock lane will enter HS mode for all the cases. 0 – LP mode 1 – HS mode Solomon Systech 8.1.9 VC Control Register Offset Address VCR BIT VC Control Register 15 14 13 12 0xB8 11 10 9 8 NAME TYPE RO RO RO RO RO RO RO RO RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 BIT 7 6 5 4 3 2 1 0 NAME VCM VCE VC2 VC1 TYPE RW RW RW RW RESET 0x1 0x0 0x1 0x1 Table 8-10: VC Control Register Description Name Reserved Bit 15-8 VCM Bit 7-6 VCE Bit 5-4 VC2 Bit 3-2 VC1 Bit 1-0 SSD2828QN4 Description Setting Virtual Channel ID for Maximum Return Size Packet – These bits specify the VC ID for the Maximum Return Size Packet sent by SSD2828. This register field is included as the VC ID for this packet might be different from the VC ID for the packets carrying the actual data. Virtual Channel ID for EOT Packet – These bits specify the VC ID for the EOT Packet sent by SSD2828. This register field is included as the VC ID for this packet might be different from the VC ID for the packets carrying the actual data. Virtual Channel ID for SPI Interface – These bits specify the VC ID for the packets written in through the SPI interface, when the interface setting is RGB + SPI This register field is included as the RGB + SPI interface can address two different LCD panels at the same time. The VC ID for the two panels is different. Virtual Channel ID for RGB Interface – These bits specify the VC ID for the packets written in through the RGB interface, when the interface is RGB + SPI Rev 1.3 P 35/168 Mar 2013 Solomon Systech 8.1.10 PLL Control Register Offset Address PCR BIT PLL Control Register 15 14 13 12 11 0xB9 10 9 8 NAME SYSD SYS_DIS TYPE RW RW RO RO RO RO RO RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 5 4 3 2 1 BIT 7 6 NAME 0 PEN TYPE RO RO RO RO RO RO RO RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Table 8-11: PLL Control Register Description Name SYSD Bit 15-14 Description SYS_clk Divider – These bits give the divider value for generating the sys_clk output from the tx_clk or crystal input. SYS_DIS Bit 13 SYS_clk DISable – This bit will shut off the Sys_clk signal output when enabled. Setting 00 – Divide by 1 01 – Divide by 2 10 – Divide by 4 11 – Divide by 8 0 – Enable Sys_clk output 1 – Disable Sys_clk output Reserved Bit 12-1 PEN Bit 0 PLL Enable – This bit controls the PLL operation. 0 – PLL power down 1 – PLL enable Remark: Frequency of PLL can only be changed during PEN = 0 SSD2828QN4 Rev 1.3 P 36/168 Mar 2013 Solomon Systech 8.1.11 PLL Configuration Register Offset Address PLCR BIT PLL Configuration Register 15 14 13 12 11 0xBA 10 NAME FR TYPE RW RO RW RESET 0x2 0x0 0x01 BIT 7 9 8 1 0 MS 6 5 4 NAME 3 2 NS TYPE RW RESET 0x20 Table 8-12: PLL Configuration Register Description Name FR Bit 15-14 Description Frequency Range – These bits select the range of the output clock. The FR setting should be programmed only when PEN is 0. It has no effect when PEN is 1. Setting 00 – 62.5 < f OUT < 125 01 – 126 < f OUT < 250 10 – 251 < f OUT < 500 11 – 501 < f OUT < 1000 Reserved Bit 13 MS Bit 12-8 PLL Divider – These bits specify the PLL predivider value, MS. The frequency of the phase detector, f REF is determined by f PRE = f IN - 0x00 : MS=1 - 0x01 : MS=1 - 0x02 : MS=2 … - 0x1F : MS=31 MS The input frequency, f IN and phase detector frequency, f REF should be between 5Mhz to 100Mhz. NS Bit 7-0 The MS setting should be programmed only when PEN is 0. It has no effect when PEN is 1. PLL Multiplier – These bits specify the PLL output frequency multiplier value, NS. The output frequency, f OUT is determined by f OUT = f PRE ∗ NF - 0x00 : NS=1 - 0x01 : NS=1 - 0x02 : NS=2 … - 0xFF : NS=255 The NS setting should be programmed only when PEN is 0. It has no effect when PEN is 1. e.g. TX_CLK = 10MHz, 0xBAh = 0x8028h PLL = 40 x 10 / 1 = 400Mbps SSD2828QN4 Rev 1.3 P 37/168 Mar 2013 Solomon Systech 8.1.12 Clock Control Register Offset Address CCR Clock Control Register BIT 15 14 13 12 0xBB 11 10 9 8 NAME TYPE RO RO RO RO RO RO RO RO RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 BIT 7 6 5 4 3 2 1 0 NAME LPD TYPE RO RO RW RESET 0x0 0x0 0x03 Table 8-13: Clock Control Register Description Name Reserved Bit 15-6 LPD Bit 5-0 Description LP Clock Divider – These bits give the divider value for generating the LP mode clock from the byte clock. Setting 0x0 – Divide by 1 0x1 – Divide by 2 … 0x3F – Divide by 64 Remark: e.g. LPD = 0x4 PLL = 400Mbps LP clock = 400Mbps / LPD / 8 = 400 / 5 / 8 = 10MHz SSD2828QN4 Rev 1.3 P 38/168 Mar 2013 Solomon Systech 8.1.13 Packet Size Control Register 1 Offset Address PSCR1 BIT Packet Size Control Register1 15 14 13 12 NAME 11 10 9 8 3 2 1 0 TDC[15:8] TYPE RW RESET 0x00 BIT 0xBC 7 6 5 4 NAME TDC[7:0] TYPE RW RESET 0x00 Table 8-14: Packet Size Control Register 1 Description Name TDC Bit 15-0 Description Transmit Data Count – These bits set the total number of data bytes to be transmitted by the SSD2828 in the next operation. The SSD2828 will use the value in this field to decide what type of packet to send out. Setting Partition mode When TDC > PST. Non-partition mode When TDC PST) For DCS Long Write packet with DCS command being 0x2C or 0x3C, there is no limit in the maximum number of bytes to be transmitted in 1 write. The PST value can be set to maximum of 4096 bytes. The SSD2828 will auto insert 0x3C command at these boundaries. The maximum MCU speed at the input is 1/12 of the link frequency. Non-Partition mode(TDC LP-00 =>LP-01 =>LPHigh Speed Data Transmission 00 Bi-Directional Data Lane Turnaround LP-11 =>LP-01 =>LP-00 =>HS-0 LP-11 =>LP-10 =>LP-00 =>LP-10 =>LPEscape 00 SSD2828QN4 Rev 1.3 P 106/168 Mar 2013 Exiting Mode Sequences LP-00 =>LP-10 =>LP11 (HS-0 or HS-1) =>LP-11 High-Z Solomon Systech 9.2.5 High Speed Data Transmission High-Speed Data Transmission occurs in bursts. Transmission starts from, and ends with, a Stop state. During the intermediate time between bursts a Data Lane shall remain in the Stop state, unless a Turnaround or Escape request is presented on the Lane. During a HS Data Burst the Clock Lane shall be in High-Speed mode, providing a DDR Clock to the Slave side. After a Transmit request, a Data Lane leaves the Stop state and prepares for High-Speed mode by means of a Start-of-Transmission (SoT) procedure. Table 9-5 describes the sequence of events on TX and RX side. Table 9-5: Start-of-Transmission Sequence Observes Stop state Observes transition from LP-11 to LP-01 on the Lines Observes transition form LP-01 to LP-00 on the Lines, enables Line Termination after time TD-TERM-EN Enables HS-RX and waits for Time-out THS-SETTLE in order to neglect transition effects Starts looking for Leader-Sequence Synchronizes upon recognition of Leader Sequence ‘011101’ Receives payload data At the end of a Data Burst, a Data Lane leaves High-Speed Transmission mode and enters the Stop state by means of an End-of-Transmission (EoT) procedure. Table 9-6 shows a possible sequence of events during the EoT procedure. Note, EoT processing may be handled by the protocol or by the D-PHY. Table 9-6: End-of-Transmission Sequence Receives payload data Detects the Lines leaving LP-00 state and entering Stop state (LP-11) and disables Termination Neglect bits of last period THS-SKIP to hide transition effects Detect last transition in valid Data, determine last valid Data byte and skip trailer sequence SSD2828QN4 Rev 1.3 P 107/168 Mar 2013 Solomon Systech The following shows the sequence of the high speed data transmission including SoT data. Figure 9-4: High-Speed Data transmission in Bursts SSD2828QN4 Rev 1.3 P 108/168 Mar 2013 Solomon Systech 9.2.6 Bi-Directional Data Lane Turnaround The transmission direction of a bi-directional Data Lane can be swapped by means of a Link Turnaround procedure. This procedure enables information transfer in the opposite direction of the current direction. The procedure is the same for either a change from Forward-to-Reverse direction or Reverse-to-Forward direction. TLPX TLPX TLPX TTA- GO drive overlap LP-11 LP-10 LP-00 LP-10 LP-00 TTA- SURE LP-00 LP-00 TTA- GET LP-10 LP-11 TLPX TLPX Figure 9-5: Turnaround Procedure 9.2.7 Escape Mode Escape mode is a special mode of operation for Data Lanes using Low-Power states. With this mode some additional functionality becomes available. Escape mode operation shall be supported in the Forward direction and is optional in the Reverse direction. If supported, Escape mode does not have to include all available features. A Data Lane enters Escape mode via an Escape mode Entry procedure (LP-11, LP-10, LP-00, LP-01, LP-00). As soon as the final Bridge state (LP-00) is observed on the Lines the Lane shall enter Escape mode in Space state (LP-00). If an LP-11 is detected at any time before the final Bridge state (LP-00), the Escape mode Entry procedure shall be aborted and the receive side shall wait for, or return to, the Stop state. For Data Lanes, once Escape mode is entered, the transmitter shall send an 8-bit entry command to indicate the requested action. Table 9-7 lists all currently available Escape mode commands and actions. All unassigned commands are reserved for future expansion. SSD2828QN4 Rev 1.3 P 109/168 Mar 2013 Solomon Systech The Stop state is be used to exit Escape mode and cannot occur during Escape mode operation because of the Spaced-One-Hot encoding. Stop state immediately returns the Lane to Control mode. If the entry command doesn’t match a supported command, that particular Escape mode action shall be ignored and the receive side waits until the transmit side returns to the Stop state. Table 9-7: MIPI Escape Mode Entry Code SSD2828QN4 Escape Mode Action Command Type Entry Command Pattern (first bit transmitted to last bit transmitted) Low-Power Data Transmission mode 11100001 Ultra-Low Power State mode 00011110 Undefined-1 mode 10011111 Undefined-2 mode 11011110 Reset-Trigger [Remote Application] Trigger 01100010 Tearing Effect Trigger 01011101 Acknowledge Trigger 00100001 Unknown-5 Trigger 10100000 Rev 1.3 P 110/168 Mar 2013 Solomon Systech 9.2.8 Low Power Data Transmission The Low Power Data Transmission can be started as the following sequences: z Start: LP-11 z Escape Mode Entry: LP-11, LP-10, LP-00, LP-01,LP-00 z Low Power Data Transmission command: 11100001 „ One or more bytes (8 bit) „ Pause mode when data lane are stopped z Exit Escape Mode: LP-00, LP-10, LP-11 z Stop State : LP-11 Dp Dn Escape Mode Entry First Data Byte 01110101 LPDT Command Pause: Asynchronous no transition Second Data Byte Exit 11010000 Escape LP Clk = EXOR(Dp,Dn) Figure 9-6: Low Power Data Transmission SSD2828QN4 Rev 1.3 P 111/168 Mar 2013 Solomon Systech 9.2.9 Reset Trigger The AP can inform to the display module that it should be reseted in Reset trigger when data lanes are entering in Escape Mode. The Remote Application Reset (RAR) is using a following sequence: z Start: LP-11 z Escape Mode Entry: LP-11, LP-10, LP-00, LP-01, LP-00 z Remote Application Reset (RAR) command in Escape Mode: 0110 0010 (First to Last bit) z Mark-1: LP-00, LP-10, LP-11 z Stop State: LP-11 LP-11>10>00>01>00>01>00>10>00>... Dp Dn 0 1 Escape Mode Entry 1 0 0 0 1 Entry Command 0 Mark-1 and Stop State LP CLK = EXOR(Dp, Dn) Figure 9-7: Trigger – Reset Command in Escape Mode SSD2828QN4 Rev 1.3 P 112/168 Mar 2013 Solomon Systech 9.2.10 Tearing Effect The display module can inform to the AP when a tearing effect event (New V-synch) has been happen on the display module by Tearing Effect (TEE). The Tearing Effect (TEE) is using a following sequence: z Start: LP-11 z Escape Mode Entry (EME): LP-11, LP-10, LP-00, LP-01, LP-00 z Tearing Effect: 0101 1101 (First to Last bit) z Mark-1: LP-00, LP-10, LP-11 z Stop State: LP-11 Figure 9-8: Tearing Effect Command in Escape Mode SSD2828QN4 Rev 1.3 P 113/168 Mar 2013 Solomon Systech 9.2.11 Acknowledge The display module can inform to the AP when an error has not recognized on it by Acknowledge (ACK). The Acknowledge (ACK) is using a following sequence: z Start: LP-11 z Escape Mode Entry: LP-11, LP-10, LP-00, LP-01, LP-00 z Acknowledge (ACK) command: 0010 0001 (First to Last bit) z Mark-1: LP-00 =>LP-10 =>LP-11 z Stop State: LP-11 Figure 9-9: Acknowledge Command in Escape Mode SSD2828QN4 Rev 1.3 P 114/168 Mar 2013 Solomon Systech 9.2.12 Packet Transmission SSL MIPI CORE supports two data transmission defined in MIPI DSI specification. Figure 9-10: Two Data Transmission Mode (Separate, single) EoT Packet EoT Packet EoT Packet LPS SoT SP SP EoT LPS SoT SP SP EoT LPS SoT SP EoT LPS LgP Separate Transmissions KEY: LPS – Low Power State SP – Short Packet SoT – Start of Transmission LgP – Long Packet EoT – End of Transmission EoT Packet LPS SoT SP SP SP EoT LPS LgP Single Transmission 9.2.13 HS Transmission Example Figure 9-11: One Lane Data Transmission Example Figure 9-12: Two Lane HS Transmission Example Number of Bytes, N, transmitted is an integer multiple of the number of lanes: All Data Lanes finish at the same time LANE 0: SoT Byte 0 Byte 2 Byte 4 Byte N-6 Byte N-4 Byte N-2 EoT LANE 1: SoT Byte 1 Byte 3 Byte 5 Byte N-5 Byte N-3 Byte N-1 EoT Number of Bytes, N, transmitted is NOT an integer multiple of the number of lanes: Data Lane 0 finishes 1 byte later than Data Lane 1 LANE 0: SoT Byte 0 Byte 2 Byte 4 Byte N-5 Byte N-3 Byte N-1 LANE 1: SoT Byte 1 Byte 3 Byte 5 Byte N-4 Byte N-2 EoT KEY: LPS – Low Power State SSD2828QN4 Rev 1.3 P 115/168 SoT – Start of Transmission Mar 2013 EoT LPS EoT – End of Transmission Solomon Systech 9.2.14 General Packet Structure Two packet structures are defined for low-level protocol communication: Long packets and Short packets. For both packet structures, the Data Identifier is always the first byte of the packet. All packet data traverses the interface as bytes. Sequentially, a transmitter shall send data LSB first, MSB last. For packets with multi-byte fields, the least significant byte shall be transmitted first unless otherwise specified. Figure 9-13: Endian Example (Long Packet) DI WC (LS Byte) WC (MS Byte) ECC Data CRC (LS Byte) CRC (MS Byte) 0x29 0x01 0x00 0x06 0x01 0x0E 0x1E 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 L S B M L S S B B M L S S B B M L S S B B M L S S B B M S B Time 9.2.15 Long Packet Format Figure 9-14 shows the structure of the Long packet. A Long packet shall consist of three elements: a 32-bit Packet Header (PH), an application-specific Data Payload with a variable number of bytes, and a 16-bit Packet Footer (PF). The Packet Header is further composed of three elements: an 8-bit Data Identifier, a 16bit Word Count, and 8-bit ECC. The Packet Footer has one element, a 16-bit checksum. Long packets can be from 6 to 65,541 bytes in length. Figure 9-14: Long Packet Structure SSD2828QN4 Rev 1.3 P 116/168 Mar 2013 Solomon Systech 9.2.16 Short Packet Structure Figure 9-15 shows the structure of the Short packet. A Short packet shall contain an 8-bit Data ID followed by two command or data bytes and an 8-bit ECC; a Packet Footer shall not be present. Short packets shall be four bytes in length. The Error Correction Code (ECC) byte allows single-bit errors to be corrected and 2-bit errors to be detected in the Short packet. Figure 9-15: Short Packet Structure All packet data traverses the interface as bytes. Sequentially, a transmitter shall send data LSB first, MSB last. For packets with multi-byte fields, the least significant byte shall be transmitted first unless otherwise specified. Figure 9-13 shows a complete Long packet data transmission. Note, the figure shows the byte values in standard positional notation, i.e. MSB on the left and LSB on the right, while the bits are shown in chronological order with the LSB on the left, the MSB on the right and time increasing left to right. 9.2.17 Data Identifier (DI) The Data Identifier defines the Virtual Channel for the data and the Data Type for the application specific payload data. Figure 9-16: Data Indentifier Structure B7 SSD2828QN4 Rev 1.3 B6 B5 B4 B3 B2 VC DT Virtual Channel Indentifier (VC) Data Type (DT) P 117/168 Mar 2013 B1 B0 Solomon Systech 9.2.18 Victual Channel Identifier (VC) The VC is the address of the channel between the AP and the display modules. During the data transactions, both AP and display module will use the same VC for communication. In SSD2085, the VC for the command mode is 0x02H and the VC for the video mode is 0x01H. 9.2.19 Data Type (DT) There are two groups of Data Type: z Processor to Display Module, z Display Module to Processor Table 9-8: Data Types for Processor-sourced Packets Data Type, hex Data Type, binary Description Packet Size 01h 00 0001 Sync Event, V Sync Start Short 11h 01 0001 Sync Event, V Sync End Short 21h 10 0001 Sync Event, H Sync Start Short 31h 11 0001 Sync Event, H Sync End Short 08h 00 1000 End of Transmission (EoT) packet Short 02h 00 0010 Color Mode (CM) Off Command Short 12h 01 0010 Color Mode (CM) On Command Short 22h 10 0010 Shut Down Peripheral Command Short 32h 11 0010 Turn On Peripheral Command Short 03h 00 0011 Generic Short WRITE, no parameters Short 13h 01 0011 Generic Short WRITE, 1 parameter Short 23h 10 0011 Generic Short WRITE, 2 parameters Short 04h 00 0100 Generic READ, no parameters Short 14h 01 0100 Generic READ, 1 parameter Short 24h 10 0100 Generic READ, 2 parameters Short 05h 00 0101 DCS WRITE, no parameters Short 15h 01 0101 DCS WRITE, 1 parameter Short 06h 00 0110 DCS READ, no parameters Short 37h 11 0111 Set Maximum Return Packet Size Short 09h 00 1001 Null Packet, no data Long SSD2828QN4 Rev 1.3 P 118/168 Mar 2013 Solomon Systech Data Type, hex Data Type, binary Description Packet Size 19h 01 1001 Blanking Packet, no data Long 29h 10 1001 Generic Long Write Long 39h 11 1001 DCS Long Write/write_LUT Command Packet Long 0Eh 00 1110 Packed Pixel Stream, 16-bit RGB, 5-6-5 Format Long 1Eh 01 1110 Packed Pixel Stream, 18-bit RGB, 6-6-6 Format Long 2Eh 10 1110 Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format Long 3Eh 11 1110 Packed Pixel Stream, 24-bit RGB, 8-8-8 Format Long x0h and xFh, unspecified xx 0000 xx 1111 DO NOT USE All unspecified codes are reserved Table 9-9: Data Types for Peripheral-sourced Packets Data Type, hex Data Type, binary Description Packet Size 00h – 01h 00 000x Reserved Short 02h 00 0010 Acknowledge and Error Report Short 03h – 07h 00 0011 – 00 0111 Reserved 08h 00 1000 End of Transmission (EoT) packet 09h – 10h 00 1001 – 01 0000 Reserved 11h 01 0001 Generic Short READ Response, 1 byte returned Short 12h 01 0010 Generic Short READ Response, 2 bytes returned Short 13h – 19h 01 0011 – 01 1001 Reserved 1Ah 01 1010 Generic Long READ Response 1Bh 01 1011 Reserved 1Ch 01 1100 DCS Long READ Response 1Dh – 20h 01 1101 – 10 0000 Reserved 21h 10 0001 DCS Short READ Response, 1 byte returned Short 22h 23h – 3Fh 10 0010 10 0011 – 11 1111 DCS Short READ Response, 2 bytes returned Reserved Short SSD2828QN4 Rev 1.3 P 119/168 Mar 2013 Short Long Long Solomon Systech Figure 9-17: 16-bit per pixel RGB Color Format, Long packet for MIPI Interface 1 byte 0 R 0 5b 1 byte 4 5 RG 4 0 7 0 GG 2 3 2 3 GB 5 0 6b 5b 7 B 4 ... Pixel 1 2 bytes 1 byte 1 byte 5b Data Type Virtual Channel ID 1 byte Word Count 1 byte 6b ... 5b 1 byte 5b 1 byte 6b ... ECC Pixel 1 2 bytes 5b Checksum Pixel n Data ID Packet Header Variable Size Payload Checksum Time Figure 9-18: 18-bit per Pixel– RGB Color Format, Long packet for MIPI Interface SSD2828QN4 Rev 1.3 P 120/168 Mar 2013 Solomon Systech Figure 9-19: 18-bit per Pixel in Three Bytes – RGB Color Format, Long packet for MIPI Interface Figure 9-20: 24-bit per Pixel – RGB Color Format, Long packet for MIPI Interface SSD2828QN4 Rev 1.3 P 121/168 Mar 2013 Solomon Systech 9.3 Operating Modes The video data come from the RGB interface and the configuration is done through the SPI interface. To support different bpp settings, the following data pins are used. For all cases, R should be at the upper bits and B should be at the lower bits. • data[15:0] for 16 bpp. • data[17:0] for 18 bpp, packed. • data[17:0] for 18 bpp, loosely packed. • data[23:0] for 24 bpp. The user, first, needs to program the registers VICR1 to VICR6 with correct values. The user also needs to program the END and CO bits to 0 and 1 respectively. After programming those register fields, the user can turn on the RGB interface and enable the VEN bit to start transmission. All three video mode sequence defined in the MIPI DSI specification are supported. In Non-Burst Mode, the CSS (register 0xB7 bit 5) can be set to 0 or 1. When it is set to 1 to select the pclk as PLL reference clock, the PLL multiplication factor should be equal to the bpp value. When it is set to 0 to select the tx_clk as PLL reference clock, the PLL multiplication factor should be set such that the serial link data rte is faster than the incoming data rate. Please refer to the table below for the PLL settings. Registers VICR1 to VICR6 (0xB1 to 0xB6) needs to be programmed. (VICR1 is not used for non-burst mode with Sync Events). (VICR1 is not used for non-burst mode with Sync Events.) Below is the diagram to illustrate the definition of all the fields. Figure 9-21: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Pulses SSD2828QN4 Rev 1.3 P 122/168 Mar 2013 Solomon Systech Table 9-10: PLL Setting for Non-burst Mode (PLL reference using pclk) BPP (bit per pixel) PLL Multiplication Factor 16 18, packed 18, loosely packed 24 16 18, packed 18, loosely packed 24 1 data lane 16 18 24 24 3 data lane 5.33 6 8 8 2 data lane 8 9 12 12 4 data lane 4 4.5 6 6 PLL Output Clock Frequency 1 data lane 16 x pclk 18 x pclk 24 x pclk 24 x pclk 3 data lane 5.33 x pclk 6 x pclk 8 x pclk 8 x pclk 2 data lane 8 x pclk 9 x pclk 12 x pclk 12 x pclk 4 data lane 4 x pclk 4.5 x pclk 6 x pclk 6 x pclk Table 9-11: PLL Setting for Non-burst Mode (PLL reference using tx_clk) BPP (bit per pixel) 16 18, packed 18, loosely packed 24 16 18, packed 18, loosely packed 24 PLL Multiplication Factor 1 data lane 2 data lane NA NA NA NA NA NA NA NA 3 data lane 4 data lane NA NA NA NA NA NA NA NA PLL Output Clock Frequency 1 data lane >= 16 x pclk >= 18 x pclk >= 24 x pclk >= 24 x pclk 3 data lane >= 5.33 x pclk >= 6 x pclk >= 8 x pclk >= 8 x pclk 2 data lane >= 8 x pclk >= 9 x pclk >= 12 x pclk >= 12 x pclk 4 data lane >= 4 x pclk >= 4.5 x pclk >= 6 x pclk >= 6 x pclk In Burst Mode, the CSS (register 0xB7 bit 5) needs to be set to 0 to select the tx_clk as PLL reference clock. The PLL multiplication factor should be set such that the serial link data rate is faster than the incoming data rate. Please refer to the table below for the PLL settings. Registers VICR2 to VICR6 (0xB1 to 0xB6) needs to be programmed. VICR1 is not used for this mode. The definition of all the fields is the same as non-burst mode with Sync Events. Figure 9-22: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Events and Burst Mode SSD2828QN4 Rev 1.3 P 123/168 Mar 2013 Solomon Systech Table 9-12: PLL Setting for Burst Mode BPP (bit per pixel) PLL Multiplication PLL Output Clock Frequency Factor 1 data lane 2 data lane 1 data lane 2 data lane 16 NA NA >= 16 x pclk >= 8 x pclk 18, packed NA NA >= 18 x pclk >= 9 x pclk 18, loosely packed NA NA >= 24 x pclk >= 12 x pclk 24 NA NA >= 24 x pclk >= 12 x pclk 3 data lane 4 data lane 3 data lane 4 data lane 16 NA NA >= 5.33 x pclk >= 4 x pclk 18, packed NA NA >= 6 x pclk >= 4.5 x pclk 18, loosely packed NA NA >= 8 x pclk >= 6 x pclk 24 NA NA >= 8 x pclk >= 6 x pclk *: This value should be set such that the serial link data rate is faster than incoming data rate The SSD2828 will also monitor the status of CM and SHUT signal. When there is a change of these signals, it will send out appropriate packets. On the rising edge of CM, the CM on packet will be sent. On the falling edge of CM, the CM off packet will be sent. On the rising edge of SHUT, the Shut Down Peripheral packet will be sent. On the falling edge of SHUT, the Turn On Peripheral packet will be sent. With these packets, the MIPI slave will be able to reconstruct the RGB interface signals. Non-Burst Mode HBP LP00 Sync event, V sync start Blanking Packet LP01 Sync event, H sync start Blanking Packet LP11 Sync event, H sync start Blanking Packet Sync event, H sync start Blanking Packet LP11 Null packet Pixel data HFP VBP Sync event, H sync start Blanking Packet Packed Pixel Stream Blanking Packet Sync event, H sync start Blanking Packet Packed Pixel Stream Blanking Packet Sync event, H sync start Blanking Packet Packed Pixel Stream Blanking Packet Sync event, H sync start Blanking Packet Sync event, H sync start Blanking Packet Sync event, H sync start Blanking Packet 1st Line 2nd Line 1280th Line VFP Null packet Figure 9-23: Non-Burst mode MIPI structure SSD2828QN4 Rev 1.3 P 124/168 Mar 2013 Solomon Systech Burst Mode HBP Pixel data LP11 LP00 Sync event, V sync start Blanking Packet LP11 LP01 Sync event, H sync start Blanking Packet LP11 LP11 Sync event, H sync start Blanking Packet LP11 VBP Blanking Packet Sync event, H sync start Sync event, H sync start Blanking Packet Packed Pixel Stream LP11 Sync event, H sync start Blanking Packet Packed Pixel Stream LP11 Sync event, H sync start Blanking Packet Packed Pixel Stream LP11 Sync event, H sync start Blanking Packet LP11 Sync event, H sync start Blanking Packet LP11 Sync event, H sync start Blanking Packet LP11 1st Line 2nd Line 1280th Line VFP LP11 Figure 9-24: Burst mode MIPI structure SSD2828QN4 Rev 1.3 P 125/168 Mar 2013 Solomon Systech 9.3.1.1 Write Operation To perform write operation, the user needs to set the REN bit to 0. The SSD2828 can issue four kinds of packets for write operation, which are Generic Short Write Packet, Generic Long Write Packet, DCS Short Write Packet and DCS Long Write Packet. The bit DCS controls whether Generic Write Packet or DCS Write Packet will be sent out. The VC1 or VC2 field determines the VC ID of the outgoing packets. (Please see the 8.1.9 for the difference between VC1 and VC2.) The SSD2828 needs to know the payload size of the outgoing packets. Hence, the user needs to program the corresponding control registers. PSCR1 and PSCR2 form the TDC field that indicates the total number of payload bytes. To send a DCS Write Packet, the user needs to write the DCS command/header and the payload to the register PDR and DCS bit set to 1. If the TDC field is no more than 2, the SSD2828 will send out DCS Short Write Packet with the correct type. Otherwise, DCS Long Write Packet will be sent out. To send a Generic Write Packet, the user needs to write the payload to the register PDR and DCS bit set to 0. If the TDC field is no more than 2, the SSD2828 will send out Generic Short Write Packet with the correct type. Otherwise, Generic Long Write Packet will be sent out. For DCS Write Packet, the partition is only enabled if the DCS command is 0x2C or 0x3C. Otherwise, SSD2828 will not perform automatic partition. (This is because the DCS command 0x2C and 0x3C are to write display data into the LCD panel display memory.) The payload will be partitioned into a few packets where the payload of each packet is PST bytes. The first byte is the DCS command and the following PST bytes are the payload. Only the last packet might contain less payload, as the total payload might not be integer multiple of PST. If the incoming DCS command is 0x2C, the DCS command for the first packet is 0x2C and the DCS command for all other packets is 0x3C. If the incoming DCS command is 0x3C, the DCS command of all the packets is 0x3C. For example, in the raw data mode(IFC=0), if the TDC field is 200 and PST field is 80, 3 packets will be sent. The first two have 80 bytes of payload. The last packet has 40 bytes of payload. After performing a write operation, the user can optionally make a BTA to let the MIPI slave report its status. This is done by setting FBW bit to 1. The SSD2828 will automatically make a BTA after each write operation. Please refer to 0 for how to handle the acknowledgement received. SSD2828QN4 Rev 1.3 P 126/168 Mar 2013 Solomon Systech 0xA3 Escape Mode Entry 0x11 0x00 DI LPDT Command DI = 1010 0011 VC = 10 DT = 10 0011 Generic Short WRITE, 2 parameters SSD2828QN4 Rev 1.3 P 127/168 Mar 2013 Solomon Systech 9.3.1.2 Read Operation To perform read operation, the user needs to set the REN bit to 1. The SSD2828 can issue two kinds of packets for read operation, which are Generic Read Packet, and DCS Read Packet. The bit DCS controls whether Generic Read Packet or DCS Read Packet will be sent out. The VC1 or VC2 field determines the VC ID of the outgoing packets. (Please see the 8.1.9 for the difference between VC1 and VC2.) Before the read packet is sent out, the SSD2828 will always send out the Set Maximum Return Size Packet. This is to limit the Read Response Packet sent by the MIPI slave such that there is no over flow. Two factors determine the maximum size. One is the limit of the SSD2828 and the other is the limit of the application processor. The user should choose the smaller one among these two limits to use as the maximum return size. The parameter in the Set Maximum Return Size Packet is taken from register MRSR. The user could program the MRSR before every read so that the correct value is sent through Set Maximum Return Size Packet. If the value in the MRSR is already the desired value, the user can choose not to program it. The SSD2828 will always automatically send out Set Maximum Return Size Packet using the value in MRSR. To send a DCS Read Packet, the user just needs to write the DCS command (as there is no parameter for DCS read) to PDR register and DCS bit set to 1. To send a Generic Read Packet, the user needs to write the payload to the register PDR and DCS bit set to 0. Similar to the write operation, the TDC field is used to determine the payload size of the outgoing packet. For DCS Read Packet, the payload is just the DCS command. There is no parameter associated. For Generic Read Packet, the SSD2828 will send out the correct packet type according to the TDC value. After sending out the read packet, the SSD2828 will automatically perform a BTA to wait for the Read Response Packet from the MIPI slave. The return data will be stored in register RR. No matter what read packet is sent out, there is only one packet returning data. Therefore, no matter whether the read is DCS read or Generic read, no matter what command is used in DCS read, the return data is always stored in register RR. The user can read the data out when the RDR bit is set to 1. After seeing RDR bit been set to 1, the user should first read register RDCR which contains the number of bytes returned by the MIPI slave. By using this information, the user will know how many data should be read out from register RR. After all the return data are read out, the RDR bit will be set to 0 by the SSD2828. After the RDR bit been set to 1, the user can choose not to read the data out from register RR. The user can continue performing another operation. Once the user does so, the RDR bit will be set to 0 by the SSD2828. There might be Acknowledge and Error Report Packet sent by the MIPI slave at the same time. The operation of acknowledgement handling is described in 0. Under certain circumstance, the MIPI slave might only send back Acknowledge and Error Report Packet without any data. Thus, the RDR bit will not be set. Therefore, it is recommended that the user check the bit BTAR first. The BTAR is to indicate whether the MIPI slave has passed the bus authority back to the SSD2828 or not. Only when the BTAR is 1, there might be return data. If there is no return data, the user should follow 0 to handle the acknowledgement. SPI command write AP Rev 1.3 MIPI read request SSD2828 SPI read back SSD2828QN4 RDR = 0 Read buffer is empty P 128/168 Mar 2013 RDR = 1 Read buffer stores read back data Display IC MIPI read back Solomon Systech MIPI read back SSD2828 DP0/DN0 output Rx DP0/DN0 output e.g. SSD2085 0xB7, 0x0382 Set REN = 1, DCS = 0 for generic read 0xBC, 0x0001 Set the number of return packet for the command which is read 0xBF, 0x000A e.g. SSD2085 command 0x0A can read display status 8bit, 0x0014 Check DP0/DN0 waveforms Read from Rx 0x14 0x00 DP0 DN0 SSD2828QN4 Rev 1.3 P 129/168 Mar 2013 Solomon Systech 9.3.1.3 Acknowledgement Operation The SSD2828 can perform a BTA to give the bus authority to the MIPI slave and let it report its status. The BTA can be enabled by setting FBW bit to 1 and performing a write operation, or just performing a read operation. After the MIPI slave passes the bus authority back, the SDD2828 will set bit BTAR to 1. If there is no error on the slave side, the MIPI slave will return ACK trigger message, if the packet before BTA is a write packet. The MIPI slave will return Read Response Packet, if the packet before BTA is a read packet. In this case, after receiving the response from the MIPI slave, SSD2828 will set bit ARR and ATR bits to 1. ARR indicates that response has been received from MIPI slave. ATR indicates that the MIPI slave has reported no error with ACK trigger message. Consequently, the register ARSR will be cleared to 0. If there is error on the slave side, the MIPI slave will return Acknowledge and Error Report packet, if the packet before BTA is a write packet. The MIPI slave will return Read Response Packet (depending on the error type) and Acknowledge and Error Report Packet, if the packet before BTA is a read packet. In this case, after receiving the response from the MIPI slave, SSD2828 will set bit ARR bit to 1 and ATR bits to 0. ARR indicates that response has been received from MIPI slave. ATR indicates that the MIPI slave has sent Acknowledge and Error Report Packet instead of ACK trigger message. Therefore, the MIPI slave has reported error. The error reported by the MIPI slave will be stored in register ARSR. The user can read this register to see what error the MIPI slave has encountered. For the detailed description of each error bit, please refer to MIPI DSI specification. Below are the flow charts of handling the MIPI slave acknowledgement. They are just for reference. BTAR == 1? N Y ARR == 1? N Error! No Acknowledgement N Handle Slave Error Report Y ATR == 1? Y Slave has no error. Proceed Figure 9-25: Acknowledgement Handling after Non-Read Command SSD2828QN4 Rev 1.3 P 130/168 Mar 2013 Solomon Systech BTAR == 1? N Y ARR == 1? N Error! No Acknowledgement N Handle Slave Error Report Y Y Slave has no error. Proceed ATR == 1? Y N RDR == 1? Correctable? N Y Y RDR == 1? N Read return data and Proceed Error! No return data Error! Extra return data Proceed Figure 9-26: Acknowledgement Handling after Read Command BTA Tx Rx Read return data Remark: LP clock of Rx must be within 10% of Tx LP clock SSD2828QN4 Rev 1.3 P 131/168 Mar 2013 Solomon Systech Bit Description 0 SoT Error 1 SoT Sync Error 2 EoT Sync Error 3 Escape Mode Entry Command Error 4 Low-Power Transmit Sync Error 5 Peripheral Timeout Error 6 False Control Error 7 Contention Detected 8 ECC Error, single-bit (detected and corrected) 9 ECC Error, multi-bit (detected, not corrected) 10 Checksum Error (Long packet only) 11 DSI Data Type Not Recognized 12 DSI VC ID Invalid 13 Invalid Transmission Length 14 Reserved 15 DSI Protocol Violation Table 9-13: MIPI error report SSD2828QN4 Rev 1.3 P 132/168 Mar 2013 Solomon Systech 9.3.1.4 Tearing Effect (TE) Operation The TE operation is to perform a BTA following the previous BTA without transmitting anything in between. The bus is handed to the MIPI slave for providing TE information. After getting the TE event from display driver, the MIPI slave will pass the bus authority back to the SSD2828 by using BTA trigger message. The TE operation can be enabled by setting bit FBT and FBW to 1 before writing the last command to the MIPI slave. Afterwards, the application processor can instruct the SSD2828 to send out the last command in a write packet. Since FBW is 1, the SSD2828 will automatically perform a BTA after the write operation. The MIPI slave will response and pass the bus authority back. Since FBT is 1, the SSD2828 will perform another BTA without sending any data. This makes the MIPI slave enter TE mode. The MIPI slave will send a TE trigger message back when it gets the TE event. After getting the trigger message, the SSD2828 will set the TE pin to 1 to indicate that TE event has been received. DATA[16] is used as the TE pin. At the same time, bit TER will be set to 1. The application processor can write 1 to this bit to clear it. As the TE trigger message only determines when the TE pin will be set to 1, a counter is used to determine when to set the TE pin to 0. The TE pin will be set to 0, once the counter reaches the value in TEC. The counter uses the reference clock to do counting. If the MIPI slave does not send back the TE trigger message but just perform a BTA to pass the bus back, the SSD2828 will automatically perform another BTA to pass the bus to the MIPI slave again. It will continue do so until the MIPI slave respond with the TE trigger message, or the FBT bit is set to 0, or the LP RX timer expires. If the MIPI slave does not send back the TE trigger message and still holds the bus, the user can set the bit FBC to 1 to force a bus contention. After bus contention is resolved, the slave will pass the bus back to SSD2828. 9.3.1.5 Contention Detection and Timer Operation Two timers have been defined in SSD2828 to resolve the potential contention issue on the bus. The two timers are the HS TX timer and LP RX timer. Please see the register description for the detailed usage. Whenever the SSD2828 sees a contention being detected, it will reset the state machine and enter the default mode, which is LP TX idle mode. The data line will be kept at LP11. 9.3.1.6 Interrupt Operation An interrupt signal int_0/int_1 has been provided to interrupt the application processor so that it does not need to poll the status all the time. This will save the processing time of the application processor. int_0/int_1 is an active low signal, in other words, when the event has happened, it will go low. There are many sources that can be mapped to the interrupt signal. The user can select different source to perform different task. If more than 1 source is selected, the int_0/int_1 signal will go low when the event for 1 of the sources has happened. In this case, the user needs to read the register ISR to determine what event has happened. The different sources can be enabled/disabled through register ICR. Below is the list of available interrupt sources and their usage. RDR To indicate that return data from MIPI slave is available for read. BTAR To indicate whether the SSD2828 has the bus authority or not. It can be used after SSD2828 makes a BTA. If the MIPI slave has returned the bus authority back to SSD2828, the interrupt will be set to indicate so. Please note that, on power up, the bus authority is already on the SSD2828. Hence, the SSD2828 will show that it has the bus authority. ARR To indicate whether the SSD2828 has received the acknowledge response from the MIPI slave. The acknowledge response can either report error or not error. This is to be determined by the ATR bit. The above three interrupts are provided to the user to handle reading data from the MIPI slave or getting acknowledgement response from the MIPI slave. SSD2828QN4 Rev 1.3 P 133/168 Mar 2013 Solomon Systech PLS To indicate whether the PLL has been locked or not. If the PLL is not locked, the programming speed at the external interface must be slow. After changing the PLL setting or changing the reference clock source, the user also needs to use this interrupt to determine the PLL status. On power up, only PLS interrupt is enabled. This is to let the user determine the programming speed before configuring the SSD2828. LPTO To indicate that there is LP RX time out. HSTO To indicate that there is HS TX time out. The above two interrupts are provided to the user for error handling. PO To indicate whether the SSD2828 is ready to accept any data from the user. The SSD2828 has several internal buffers to hold the data written by the user. When the user writes after than the serial link speed, those buffers will be full. If the user still writes data to SSD2828, those data will be lost. The length of the payload of the next packet that the user is going to write is determined by TDC, PST, and DCS fields. The SSD2828 will use these fields to decide whether the user can write the next packet or not. Hence, after programming the above mentioned fields, the user needs to check the interrupt status before writing. SE, SA, SLE, SLA, MLE, MLA All these interrupts are provided to indicate the status of the internal data buffers. They are used if the user is familiar with the buffer management of the SSD2828. Otherwise, it is recommended to use the PO interrupt. One important thing to note is the interrupt latency. The output interrupt signal does not change immediately after an operation. This is due to the internal processing of the SSD2828. For example, after changing the interrupt source from one to another, the output int_0/int_1 level will remain at the old level for a short period after the programming is done. Another example is that after programming the TDC field, the interrupt will take a short period to reflect the correct PO status on int_0/int_1. There is always a delay between the actual event and the interrupt. In order to guarantee that the user can get the correct interrupt, it is recommended that the user performs a read of any SSD2828 local register before taking in the interrupt signal or polling the interrupt status bits. The read operation will cover the interrupt latency period. Alternatively, the user can wait for certain amount of time to make sure the interrupt reflects the true status. Below is a diagram for illustration. Start of read operation Interrupt reflects true status Event happens End of read operation int_b_0/ int_b_1 Time Figure 9-27: Illustration of Interrupt Latency SSD2828QN4 Rev 1.3 P 134/168 Mar 2013 Solomon Systech 9.3.1.7 Internal Buffer Status There are totally 1 data buffer inside the SSD2828QN4, which is SPI command interface buffer (CB). For CB buffers, all packets will be stored into them. They can store multiple packets and each packet size can be set to 1023 bytes. Below is a list of possible packets • Generic Short Write Packet • Generic Read Packet • DCS Short Write Packet • DCS Read Packet • Generic Long Write Packet • DCS Long Write Packet In case of automatic partitioning, the packet length is determined by the PST field. It is not recommended to make the PST field so small. The user can write the data through SPI interface. All packets will be written into the CB buffers. Hence, the user needs to check the corresponding interrupts. The usage of the interrupts is listed below. CBE To indicate that the Command buffer is empty. CBA To indicate that the Command buffer can hold at least 1 more packet. The user can write 1 such packet into CB buffer. The interrupts mentioned here can be used as flow control between the application processor and the SSD2828. However, it requires the user to know the buffer operation well. The PO interrupt is a combination of the eight. It makes decision according to the parameters provided by the user for the next packet to be written. Hence, the user does not need to know which buffer is going to be used and how the buffer status is. 9.3.2 State machine operation The state machine controls the sending and receiving of the data packet over the serial link. It is triggered by an event from the application processor or the received data. Once a complete packet is written into the SSD2828 buffer, it will send it out through the serial link. The user can write 1 to bit COP at any time to cancel all the current operations. Please see 8.1.17 for the description. When the SSD2828 is in high speed mode, the serial link is mainly used to send display data. If there is no data to send, it will send null packet to maintain the serial link timing. If the application processor does not have display data to send in a long period, it can turn the serial link into low power mode by setting the register bit HS to 0. When the SSD2828 is in low power mode, the serial link is mainly used to send command and configuration data. If there is no data to sent, the SSD2828 will be idle in LP TX stop mode. The user can also enter sleep mode by writing 1 to SLP bit. Once the SLP bit is set to 1, the SSD2828 will automatically enter LP mode. If the HS bit is 1, the SSD2828 will clear the HS bit to 0 and switch from HS to LP mode. Afterwards, the SSD2828 will issue ULPS trigger message to the MIPI slave to enter Ultra Low Power State. During this state, the clock to SSD2828 can be switched off such that the SSD2828 only consumes leakage current. This will save the overall system power consumption. When exiting from the ULPS, the user can write 0 to SLP bit. However, the user should be aware that the time to exit from ULPS is relatively long (pleaser refer to MIPI DPHY specification). Hence, the user cannot perform any data transmission before the system exits from ULPS. SSD2828QN4 Rev 1.3 P 135/168 Mar 2013 Solomon Systech During reception, the state machine will disassemble the incoming data packet and put the received register content into the internal buffer for reading out. Once all the data are put into the buffers, it will set the register bit RDY to 1 to indicate that the SSD2828 is ready for read. The total number of received bytes will also be stored in RDCR. After the reception is completed, the SSD2828 will perform a bus turn around to enter the transmission mode. It will always come back to the LP TX stop mode before it enters any other mode. 9.3.3 D-PHY operation D-PHY controls the operation of the analog transceiver. It controls whether the serial link is in high speed or low power mode and whether it’s in transmit or receive mode. In transmit mode, the D-PHY will perform the handshaking procedure when switching between LP mode and HS mode according to the control from PCU. During HS mode, D-PHY will provide parallel data and clock to the analog transmitter for transmitting in differential signals serially. During LP mode, D-PHY will directly drive the Datap and Datan line output. It will provide serial data to the analog transmitter. In receive mode, D-PHY will detect the handshaking sequence in LP mode and inform the PCU. Once entering escape mode, it will collect the serial data from analog receiver and put them in byte form for the PCU to process. Various timing parameter has been defined in MIPI DPHY specification. The timing parameters are a mixture of absolute time and cycle counts. Hence, for different operation speed, there is different timing requirement. Registers DAR1 to DAR6 are provided for this purpose. The user can adjust the value in these registers to have different DPHY timing parameters. This gives maximum flexibility for different operation speed. SSD2828QN4 Rev 1.3 P 136/168 Mar 2013 Solomon Systech 9.3.4 Analog Transceiver 9.3.5 PLL The PLL output frequency is calculated by the equations below, f IN MS = f PRE * NS f PRE = f OUT where the f IN is the input reference clock frequency and f OUT is the output clock frequency of the PLL. The clock frequencies need to satisfy the constraint below. 5MHz > f IN ≥ 100 MHz 5MHz > f REF ≥ 100 MHz 62.5MHz > f OUT ≥ 1000MHz The value of FR, MS, and NS are controlled in the register PLCR. All the values of FR, MS and NS can only be modified when the PLL is turned off. Hence, the sequence for modification is to turn off PLL, modify register value, and turn on PLL. SSD2828QN4 Rev 1.3 P 137/168 Mar 2013 Solomon Systech 9.3.6 Clock Source Example SSD2828QN4 Rev 1.3 P 138/168 Mar 2013 Solomon Systech 10 External Interface The SSD2828 supports three types of SPI interface, • 8-Bit 3 wire (type C option 1, DBI 2.0) • 8-Bit 4 wire (type C option 3, DBI 2.0) • 24-bit 3 wire and RGB interfaces. The selection is controlled by ps[1:0] pins. RGB interface supports 4 bpp settings. Below are the data pins used for each interface. For all cases, R should be at the upper bits and B should be at the lower bits. • data[15:0] for 16 bpp. • data[17:0] for 18 bpp, packed. • data[17:0] for 18 bpp, loosely packed. • data[24:0] for 24 bpp. SPI interface supports 8-Bit data bus. The least significant byte should be written first. Below is the operation and timing diagram for each of the interfaces. 10.1 SPI Interface 8 bit 4 Wire This interface consists of sdcx, sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8Bit data. The first cycle should be a command write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During 1 operation, the application processor can write or read multiple bytes. sdcx indicates whether the operation is for data or command. When sdcx is 1, the operation is for data. When sdcx is 0, the operation is for command. sdcx is sampled at every 8th rising edge of sck during 1 operation. During write operation, sdin will be sampled by SSD2828 at the rising edge of sck. The first rising edge of sck after the falling edge of csx samples the bit 7 of the 8-Bit data. The second rising edge of sck samples the bit 6 of the 8-Bit data, and so on. The value of sdcx is sampled at the 8th rising edge of sck, together with bit 0 of the 8-Bit data. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles. SSD2828QN4 Rev 1.3 P 139/168 Mar 2013 Solomon Systech SDC SCK SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDO Data bit 7-0 Data bit 15-8 CSX0 Command Write Cycle Data Write Cycle Data Write Cycle Figure 10-1: Illustration of Write Operation for 8 bit 4 Wire Interface Remark: Send LSB 8bit of data before MSB 8bit During read operation, since there is no rwx signal to indicate whether the operation is read or write. After csx is driven low, the first cycle is always a command write cycle, which specifies the register to access. The second cycle is still a command write cycle. If the command in this cycle matches the command in register LRR, the SPI interface will enter read mode. The subsequent cycles will be read cycles. If the command does not match, the SPI interface will remain in write mode. After entering the read mode, the return data is provided on sdout, on the falling edge of sck. The application processor should use the rising edge of sck to sample the data. sdcx should be driven to 1 during the read cycles. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles. SDC SCK SDI D 7 D6 D5 D 4 D3 D 2 D1 D0 D 7 D 6 D5 D4 D 3 D 2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDO D7 D6 D5 D4 D3 D2 D 1 D 0 CSX0 Command Write Cycle Write the actual address to read Command Write Cycle Return Data Read Cycle Return Data Read Cycle Write special command to enter read mode Figure 10-2: Illustration of Read Operation for 8 bit 4 Wire Interface SSD2828QN4 Rev 1.3 P 140/168 Mar 2013 Solomon Systech 10.2 SPI Interface 8 bit 3 Wire This interface consists of sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8-Bit data. The first cycle should be a write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During 1 operation, the application processor can write or read multiple bytes. Instead of sdcx, an sdcx bit is used to indicate whether the operation is for data or command. Each byte is associated with an sdcx bit. When sdcx is 1, the operation is for display data. When sdcx is 0, the operation is for command. The sdcx bit is sent priori to each byte. In other words, the sdcx bit is the first bit of every 9 bits during 1 operation. During write operation, sdin will be sampled by SSD2828 at the rising edge of sck. The first rising edge of sck after the falling edge of csx samples the sdcx bit. The second rising edge samples bit 7 of the 8-Bit data. The third rising edge of sck samples the bit 6 of the 8-Bit data, and so on. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles. SCK SDI 0 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 SDO Data bit 7-0 CSX0 Command Write Cycle Data Write Cycle Data bit 15-8 Data Write Cycle Figure 10-3: Illustration of Write Operation for 8 bit 3 Wire Interface Remark: Send LSB 8bit of data before MSB 8bit During read operation, since there is no rwx signal to indicate whether the operation is read or write. After csx is driven low, the first cycle is always a command write cycle, which specifies the register to access. The second cycle is still a command write cycle. If the command in this cycle matches the command in register LRR, the SPI interface will enter read mode. The subsequent cycles will be read cycles. If the command does not match, the SPI interface will remain in write mode. After entering the read mode, the return data is provided on sdout, on the falling edge of sck. The application processor should use the rising edge of sck to sample the data. Please note that there is no sdcx bit to read out from SSD2828. Hence, each read cycle consists of 8-Bits instead of 9 bits. This is the difference between read and write cycles. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles. SSD2828QN4 Rev 1.3 P 141/168 Mar 2013 Solomon Systech SCK SDI 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 SDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSX0 Return Data Read Cycle Command Write Cycle Command Write Cycle Return Data Read Cycle Write special command to enter read mode Write the actual address to read Figure 10-4: Illustration of Read Operation for 8 bit 3 Wire Interface Read sequence of register e.g.0xB0h Send D4h 0xFA, 0x00 #1 #2 #3 #4 CS SCK #1 Send B0h, with DC bit =0 SDI #2 0xB0 Send 0xFA, with DC bit =0 0xFA 0x28 #3 Read data from SDO Data [7:0] 28 #4 Read data from SDO Data [15:8] 28 SSD2828QN4 Rev 1.3 P 142/168 Mar 2013 0x28 SDO Solomon Systech 10.2.1 3 or 4 wires 8bit SPI read back sequence for 0xFF register which is stored MIPI read back data Send 0xB7 0x82, 0x03 e.g. LP generic read Send 0xBB 0xXX, 0x00 "XX" is the register for LP freq. setting Rx internal clock freq. must be similar to Tx Send 0xC1 0x0A, 0x00 Max. return packet is 255 bytes Send 0xC0 0x00, 0x01 Send 0xBC 0x01, 0x00 Send 0xBF 0xXX, 0x00 "XX" is the register of display driver MIPI Read Preparation for 0xFF read Send 0xD4 0xFA, 0x00 Set read command "FA" for 3 wire 8bit Send C6h, with DC bit =0 Read register 0xC6 Send 0xFA, with DC bit =0 "FA" read command If Bit 0 is "0" SSD2828QN4 Read data from SDO Data [7:0] Confirm bit0 is "1" Read data from SDO Data [15:8] Rev 1.3 P 143/168 Mar 2013 Solomon Systech Read sequence of register FFh (1st Byte data of 0xXX) Send FFh, with DC bit =0 Send 0xFA, with DC bit =0 Read data from SDO Data [7:0] Read data from SDO Data [15:8] Read sequence of register FFh (2nd Byte data of 0xXX) Send 0xFA, with DC bit =0 Read data from SDO Data [7:0] Read data from SDO Data [15:8] Read sequence of register FFh (xxth Byte data of 0xXX) Send 0xFA, with DC bit =0 SSD2828QN4 Read data from SDO Data [7:0] Read data from SDO Data [15:8] Rev 1.3 P 144/168 Mar 2013 Solomon Systech 10.3 SPI Interface 24 bit 3 Wire This interface consists of sck, sdin, sdout and csx. It only supports 16-bit data. Each cycle contains 16-bit data. The first cycle should be a write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. The csx should be driven from 1 to 0 to start cycle and from 0 to 1 to end a cycle. During 1 operation, the application processor can have multiple write or read cycles. However, the csx must go from 0 to 1 at the end of each cycle. Each cycle contains 24-bit data. Among the 24-bit data, the first 8-Bit are for control purpose and the next 16-bit are the actual data. The first 6 bits are the ID bit for SSD2828, which must be 011100. If this field does not match, the cycle will not be taken in. The 7th bit is the sdcx bit which is the same as the 8-Bit 3 wire interface. The 8th bit is the RW bit which indicates whether the current cycle is a read or write cycle. When RW is 1, the cycle is a read cycle. When RW is 0, the cycle is a write cycle. During write operation, sdin will be sampled by SSD2828 at the rising edge of sck. Please see the diagram below for illustration. It is an example for writing data 0x1264 to register address 0x28. First Transmission (Command) CSX0 1 2 SCK 3 4 5 6 7 8 9 11 D15 SDI “0” “1” “1” “1” “0” “0” SDC RW CSX0 SCK 10 “0” “0” 12 13 14 …… “0” “0” “0” 15 16 17 18 D8 D7 “0” “0” “0” 19 20 21 22 …… 23 24 D0 “0” “0” “1” “0” “1” “0” “0” “0” 17 18 19 20 21 22 23 24 Second Transmission (Data) 1 2 3 4 5 6 7 8 9 SDI 10 11 D15 “0” “1” “1” “1” “0” “0” SDC RW “0” “0” 12 13 14 …… “0” “1” “0” 15 16 D8 D7 “0” “1” “0” …… “0” “1” “1” D0 “0” “0” “1” “0” “0” Figure 10-5: Illustration of Write Operation for 24 bit 3 wire Interface Remark: Send MSB 8bit of data before LSB 8bit SSD2828QN4 Rev 1.3 P 145/168 Mar 2013 Solomon Systech During read operation, the first 8-Bit are still written by the application processor to specify whether the following 16-bit are for command or data. Afterwards, the SSD2828 will provide the return data on sdout, on the falling edge of sck. The application processor should use the rising edge of sck to sample. Please see the diagram below for illustration. CSX0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK SDI Invalid “0” “1” “1” “1” “0” “0” SDC RW SD O “0” “0” “0” “1” “0” “0” “1” “0” “0” “1” “1” “0” “0” “1” “0” “0” Figure 10-6: Illustration of Read Operation for 24 bit 3 Wire Interface Read sequence of register e.g.0xB1h #1 #3 SCK SDO 0x00 Send B1h, with DS bit =0 Data [15:0] 0014 Read data from SDO SSD2828QN4 Rev 1.3 0x14 P 146/168 Mar 2013 Solomon Systech 10.3.1 3 wires 24bit SPI read back sequence for 0xFF register which is stored MIPI read back data Send 0x7000B7 0x720382 e.g. LP generic read Send 0x7000BB 0x7200XX "XX" is the register for LP freq. setting Rx internal clock freq. must be similar to Tx Send 0x7000C1 0x72000A Max. return packet is 255 bytes Send 0x7000C0 0x720001 Send 0x7000BC 0x720001 Send 0x7000BF 0x7200XX "XX" is the register of display driver MIPI Read Preparation for 0xFF read Send 0x7000C6h Read register 0xC6 Send 0x730000 SPI Read If Bit 0 is "0" Read data from SDO SSD2828QN4 Rev 1.3 P 147/168 Mar 2013 Data [15:0] Confirm bit0 is "1" Solomon Systech Read sequence of register FFh (1st and 2nd Byte data of 0xXX) Send 0x7000FF Send 0x730000 Read data from SDO Data [15:0] Read sequence of register FFh (nth and n+1th Byte data of 0xXX) Send 0x730000 Read data from SDO SSD2828QN4 Rev 1.3 P 148/168 Mar 2013 Data [15:0] Solomon Systech 11 MAXIMUM RATINGS Table 11-1: Maximum Ratings (Voltage Referenced to VSS) Symbol Parameter Value Unit MVDD Core Power Supply -0.3 to 1.44 V VDDIO I/O Power Supply -0.3 to 4.0 V TSOL Solder Temperature / Time 225 for 40 sec max at solder ball o TSTG Storage Temperature -40 to 100 o C C Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits specified in the electrical characteristics tables and Pin Description section This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. SSD2828QN4 Rev 1.3 P 149/168 Mar 2013 Solomon Systech 12 RECOMMENDED OPERATING CONDITIONS Table 12-1: Recommended Operating Conditions Symbol Parameter Min Typ Max Unit MVDD Digital Core Power Supply 1.08 1.2 1.32 V VDDIO I/O AND Digital Power Supply 2.97 3.3 3.63 V 1.62 1.8 1.98 V -30 25 85 TA SSD2828QN4 Operating Temperature Rev 1.3 P 150/168 Mar 2013 o C Solomon Systech 13 DC Characteristics Conditions: Voltage referenced to GND MVDD = 1.2V VDDIO = 1.8V Frame frequency = 60Hz Number of lane = 4 Display pattern = 1080x1920, 8 colors vertical bar TA = 25°C Table 13-1: DC Characteristics Symbol Parameter Test Condition Min Typ Max Unit - 46.8 76.2 mA - 0.36 0.75 mA IVDDIO_HS (3.3V) - 0.79 1.64 mA IMVDD_LP - 16.00 39.90 mA 0.17 0.43 0.37 0.94 292.4 435 75.6 150 165.2 327.8 VDDIO x 0.8 - - V - - VDDIO x 0.15 V IMVDD_HS IVDDIO_HS (1.8V) High Speed Mode Current IVDDIO_LP (1.8V) Low Power Mode Current 1Gbps 10Mbps - IVDDIO_LP (3.3V) - IMVDD_ULPS - IVDDIO_ULPS Ultra Low Power (1.8V) State Current PLL off, no change in all input signals IVDDIO_ULPS (3.3V) - mA mA μA μA μA VOH (CMOS) Output High Voltage (CMOS) VOL (CMOS) Output Low Voltage IOL= 2 ~ 16 mA (CMOS) VIH (CMOS) Input High Voltage (CMOS) VDDIO x 0.7 - - V VIL (CMOS) Input Low Voltage (CMOS) - - VDDIO x 0.2 V IOZ Tri-state Output Leakage Current - - μA IIN Input Leakage Current - μA CIN Input Capacitance - pF SSD2828QN4 Rev 1.3 P 151/168 IOH = -2 ~ -16 mA VIN = VDDIO or GND - Mar 2013 +/-1 +/-1 2.2 Solomon Systech Table 13-2: HS Transmitter DC Characteristics Symbol VCMTX |VOD| Parameter Min Typ Max Unit HS Transmit Static Common-mode Voltage 150 - 250 mV HS Transmit Differential Voltage 140 - 270 mV |ΔVOD| HS Differential Mismatch - - 10 mV VOHHS HS Output High Voltage - - 360 mV Table 13-3: LP Transmitter DC Characteristics Symbol Parameter Min Typ Max Unit VOH LP Thevenin Output High Level 1.1 1.2 1.3 V VOL LP Thevenin Output Low Level -50 - 50 mV ZOLP LP Transmitter Output Impedance 110 - - Ohm Table 13-4: LP Receiver DC Characteristics Symbol SSD2828QN4 Parameter Min Typ Max Unit VIH LP Logic 1 Input Voltage 880 - - mV VIL LP Logic 0 Input Voltage - - 550 mV Rev 1.3 P 152/168 Mar 2013 Solomon Systech 14 AC Characteristics NOTE: 1. After PLL gets locked, T is the period of the PLL output clock unless specified. Before PLL gets locked, T is the period of PLL input reference clock. The reference clock can be either the tx_clk or the pclk, depending on the CSS bit. 1 / T = PLL / 2, e.g. When PLL is Off , TX_CLK = 10MHz, PLL = TX_CLK x 2 = 20Mbps 1 / T = 10MHz 2. W is the width of the display, e.g. the number of pixels for the horizontal line. 3. The AC characteristics specifie the maximum speed of the incoming signals at the input interface. However, the data throughput on the serial link is another factor affecting the speed. If the user takes in the INT signal, there will be automatic flow control. If the user does not take the INT signal, the user needs to ensure that the output throughput is larger than the incoming data rate. SSD2828QN4 Rev 1.3 P 153/168 Mar 2013 Solomon Systech 14.1 8 Bit 4 Wire SPI Interface Timing Table 14-1: 8 Bit 4 Wire SPI Interface Timing Characteristics Symbol tcycle fCLK tAS tAH tCSS tCSH tDSW tDHW tACC tDHR tCLKL tCLKH tCSWD tCSRD tR tF Parameter Min Clock Cycle Time Serial Clock Cycle Time Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Read Data Access Time Read Data Hold Time Clock Low Time Clock High Time Chip Select Write Delay Time Chip Select Read Delay Time Rise time Fall time 8T 4 0 4 0 4 0 1.2+4T 4T 4T 8T 16T - Typ Max Unit 1/8T 4.4+6T 4.4+6T 2 2 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: All timings are based on 20% to 80% of supply voltage Write SDC tAS tCSS CSX0 tAH tCSH tCSWD tcycle tCLKL SCK tCLKH tR tF tDHW tDSW SDI Valid Data Read SDC tAS tCSS CSX0 tAH tCSH tCSRD tcycle tCLK SCK L tF tR tDHR tACC SDO tCLKH Valid Data Figure 14-1: 8 Bit 4 Wire SPI Interface Timing Diagram SSD2828QN4 Rev 1.3 P 154/168 Mar 2013 Solomon Systech 14.2 8 Bit 3 Wire SPI Interface Timing Table 14-2: 8 Bit 3 Wire SPI Interface Timing Characteristics Symbol tcycle fCLK tCSS tCSH tDSW tOHW tACC tDHR tCLKL tCLKH tCSWD tCSRD tR tF Parameter Min Clock Cycle Time Serial Clock Cycle Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Read Data Access Time Read Data Hold Time Clock Low Time Clock High Time Chip Select Write Delay Time Chip Select Read Delay Time Rise time Fall time 8T 4 0 4 0 1.2+4T 4T 4T 8T 16T - Typ Max Unit 1/8T 4.4+6T 4.4+6T 2 2 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns Note: All timings are based on 20% to 80% of supply voltage Write tCSS CSX0 tCSH tCSWD tcycle tCLKL SCK tR tF tDSW SDO tCLKH tDHW Valid Data Read tCSS CSX0 tCSH tCSRD tcycle tCLKL SCK tR tF tDHR tACC SDO tCLKH Valid Data Figure 14-2: 8 Bit 3 Wire SPI Interface Timing Diagram SSD2828QN4 Rev 1.3 P 155/168 Mar 2013 Solomon Systech 14.3 24 Bit 3 Wire SPI Interface Timing Table 14-3: 24 Bit 3 Wire SPI Interface Timing Characteristics Symbol tcycle fCLK tCSS tCSH tDSW tOHW tACC tDHR tCLKL tCLKH tCSWD tCSRD tR tF Parameters Min Max Units Clock Cycle Time Serial Clock Cycle Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Read Data Access Time 8T 4 0 4 0 - Typ 1/8T 4.4+6T ns MHz ns ns ns ns ns Read Data Hold Time Clock Low Time Clock High Time Chip Select Write Delay Time Chip Select Read Delay Time Rise time Fall time 1.2+4T 4.4+6T 4T 4T 8T 16T - 2 2 ns ns ns ns ns ns ns Note: All timings are based on 20% to 80% of supply voltage Write tCSS CSX0 tCSH tCSWD tcycle SCK tCLK L tF tDSW SDI tCLKH tR tDHW Valid Data Read tCSS CSX0 tCSH tCSRD tcycle SCK tCLK L tF tR tDHR tACC SDO tCLKH Valid Data Figure 14-3: 24 Bit 3 Wire SPI Interface Timing Diagram SSD2828QN4 Rev 1.3 P 156/168 Mar 2013 Solomon Systech 14.4 RGB Interface Timing Table 14-4: RGB Interface Timing Characteristics Symbol tpclk tvsys tvsyh thsys thsyh thv tCKL tCKH tds tdh Parameters pclk Period Vertical Sync Setup Time Vertical Sync Hold Time Horizontal Sync Setup Time Horizontal Sync Hold Time Phase difference of Sync Signal Falling Edge pclk Low Period pclk High Period Data Setup Time Data hold Time Min 16/18/24T 5 5 5 5 0 8/9/12T 8/9/12T 3.3 3.3 Typ 16/18/24T Max ns ns ns ns ns W 8/9/12T 8/9/12T Units tpclk ns ns ns ns Note: 1. T represents the total bit rate Tmax = 1 / (PLL x number of lane) Tmax = 1 / 4G = 250ps 2. All timings are based on 20% to 80% of supply voltage 3. W is the number of pixel in a horizontal line 4. The pclk period depends on the bit per pixel (bpp) setting and whether the video mode is burst or non-burst mode. In burst mode, the values in the Min column should be followed. In non-burst mode, the values in the Typ column should be followed. tvsys tvsyh VSYNC thsyh thsys HSYNC thv tDOTCLK PCLK tCKL tds tCKH tdh DATA[23:0] Figure 14-4: RGB Interface Timing Diagram SSD2828QN4 Rev 1.3 P 157/168 Mar 2013 Solomon Systech 14.5 RESET Timing Table 14-5: RESET Timing Symbol TRESET Parameters RESET “Low” Pulse Width Min Typ Max Units 10 - - ms 14.6 TX_CLK Timing Table 14-6: TX_CLK Timing Characteristics Symbol Min Typ Max Units TX_CLK Frequency 8 - 30 MHz tR Rise Time - 10 ns tF Fall Time - 10 ns fTXCLK Parameters Figure 14-5: TX_CLK Timing Diagram SSD2828QN4 Rev 1.3 P 158/168 Mar 2013 Solomon Systech 15 Power up sequence VDDIO VDDIOC MAVDDV >=0ms VCC12A MDVDD MAVDD >=0ms >=10ms RESB >=0ms TX_CLK >=1ms Input interface e.g. SPI PLL ON Leave ULP mode >=1ms Sleep out command PEN = 1 SLP = 0 VEN&HS = 1 Video mode ON >=1ms RGB signals SSD2828QN4 Rev 1.3 P 159/168 Mar 2013 Solomon Systech 16 Power off sequence VDDIO VDDIOC MAVDDV >=0ms VCC12A MDVDD MAVDD >=0ms RESB >=0ms TX_CLK Video mode OFF Enter ULP mode PLL OFF >=10ms Sleep in command VEN&HS = 0 SLP = 1 PEN = 0 >=0ms RGB signals SSD2828QN4 Rev 1.3 P 160/168 Mar 2013 Solomon Systech 17 Example for system sleep in and out Note: Following example is only for reference, application must be related to the particular information of AP and driver IC, e.g.Wait time and TX_CLK (_XIN, _XIO) csontrol of AP Video Display Mode AP switches ON TX_CLK Driver Display OFF Command e.g. 0x28 AP switches ON RGB signals Wait time (Depend on driver IC) Wait 10ms Driver Sleep In Command e.g. 0x10 Driver IC Sleep In SSD2828 PLL ON e.g. 0xB9 0x0001 Wait time (Depend on driver IC) SSD2828 Leaves ULP Mode e.g. 0xB7 0x0300 AP switches OFF RGB signals Driver Sleep In Command e.g. 0x11 SSD2828 Video Mode OFF e.g. 0xB7 0x0300 Wait time (Depend on driver IC) SSD2828 Enters ULP Mode e.g. 0xB7 0x0304 Driver Display OFF Command e.g. 0x29 Driver IC Sleep In SSD2828 PLL OFF e.g. 0xB9 0x0000 Wait time (Depend on driver IC) Wait 10ms SSD2828 Video Mode ON e.g. 0xB7 0x0309 AP switches OFF TX_CLK SSD2828 Sleep In SSD2828QN4 Rev 1.3 P 161/168 Video Display Mode Mar 2013 Solomon Systech 18 Serial Link Data Order There are many possible ways of doing parallel to serial conversion. SSD2828 provides flexibility by programming two register bits END and CO. During video mode, they must be programmed to 0 and 1 respectively. Below is the order to receive the display data over the serial link, when the END bit is 1 and CO bit is 0. For 16 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Time For 18 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 Time For 24 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0 Time Below is the order to send the display data over the serial link, when the END bit is 0 and CO bit is 0. For 16 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 Time For 18 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB G1 G0 B5 B4 B3 B2 B1 B0 R3 R2 R1 R0 G5 G4 G3 G2 B5 B4 B3 B2 B1 B0 R5 R4 R1 R0 G5 G4 G3 G2 G1 G0 Time SSD2828QN4 Rev 1.3 P 162/168 Mar 2013 Solomon Systech For 24 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Time Below is the order to send the display data over the serial link, when the END bit is 1 and CO bit is 1. For 16 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0 Time For 18 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R0 B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 Time For 24 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Time Below is the order to send the display data over the serial link, when the END bit is 0 and CO bit is 1. For 16 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB G2 G1 G0 R4 R3 R2 R1 R0 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0 B4 B3 B2 B1 B0 G5 G4 G3 Time For 18 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 SSD2828QN4 LSB MSB Rev 1.3 Byte2 LSB P 163/168 Mar 2013 MSB Byte3 LSB MSB Byte4 LSB Solomon Systech G1 G0 R5 R4 R3 R2 R1 R0 B3 B2 B1 B0 G5 G4 G3 G2 R5 R4 R3 R2 R1 R0 B5 B4 B1 B0 G5 G4 G3 G2 G1 G0 Time For 24 bit per pixel data, below is the byte order. Each byte of data is sent in the order of LSB first and MSB last. MSB Byte 1 LSB MSB Byte2 LSB MSB Byte3 LSB MSB Byte4 LSB R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0 Time SSD2828QN4 Rev 1.3 P 164/168 Mar 2013 Solomon Systech 19 PACKAGE INFORMATION 19.1 Dimension for SSD2828QN4 Figure 19-1- Package Information SSD2828QN4 Rev 1.3 P 165/168 Mar 2013 Solomon Systech Figure 19-2- Marking Information SSD2828QN4 Rev 1.3 P 166/168 Mar 2013 Solomon Systech Figure 19-3- Tray Information SSD2828QN4 Rev 1.3 P 167/168 Mar 2013 Solomon Systech Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. The product(s) listed in this datasheet comply with Directive 2002/95/EC of the European Parliament and of the council of 27 January 2004 on the restriction of the use of certain hazardous substances in electrical and electronic equipment and People’s Republic of China Electronic Industry Standard SJ/T 11363-2006 “Requirements for concentration limits for certain hazardous substances in electronic information products (电子信息产品 中有毒有害物质的限量要求)”. Hazardous Substances test report is available upon request. http://www.solomon-systech.com SSD2828QN4 Rev 1.3 P 168/168 Mar 2013 Solomon Systech