SIT8925AE-13-33E-125.000000 数据手册
SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
AEC-Q100 with extended temperature range (-55°C to 125°C)
Automotive, extreme temperature and other high-rel electronics
Frequencies between 115.2 MHz and 137 MHz accurate to 6 decimal
points
Infotainment systems, collision detection devices, and in-vehicle
networking
100% pin-to-pin drop-in replacement to quartz-based XO
Power train control
Excellent total frequency stability as low as ±25 ppm
Industry best G-sensitivity of 0.1 PPB/G
LVCMOS/LVTTL compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm x mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Electrical Specifications
Table 1. Electrical Characteristics[1, 2]
Parameter and Conditions
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Range
Output Frequency Range
f
115.20
–
137
MHz
F_stab
-25
–
+25
ppm
-30
–
+30
ppm
–
+50
ppm
Refer to Table 13 and Table 14 for the exact list of supported
frequencies
Frequency Stability and Aging
Frequency Stability
-50
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Operating Temperature Range
Operating Temperature Range
(ambient)
T_use
-40
–
+105
°C
-40
–
+125
°C
Extended Industrial, AEC-Q100 Grade 2
Automotive, AEC-Q100 Grade 1
-55
–
+125
°C
Extended Temperature, AEC-Q100
Supply Voltage and Current Consumption
Supply Voltage
Current Consumption
Vdd
Idd
1.62
1.8
1.98
V
2.25
–
3.63
V
All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V
and 3.3V are supported. Contact SiTime for 1.5V support
–
6
8
mA
No load condition, f = 125 MHz, Vdd = 2.25V to 3.63V
–
4.8
6
mA
No load condition, f = 125 MHz, Vdd = 1.62V to 1.98V
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
45
–
55
%
Tr, Tf
–
1.5
3
ns
Vdd = 2.25V - 3.63V, 20% - 80%
–
1.5
2.5
ns
Vdd = 1.8V, 20% - 80%
Output High Voltage
VOH
90%
–
–
Vdd
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
Output Low Voltage
VOL
–
–
10%
Vdd
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Input High Voltage
VIH
70%
–
–
Vdd
Pin 1, OE
Input Low Voltage
VIL
–
–
30%
Vdd
Pin 1, OE
Input Pull-up Impedence
Z_in
–
100
–
k
Pin 1, OE logic high or logic low
Input Characteristics
Startup and Resume Timing
Startup Time
T_start
–
–
5
ms
Measured from the time Vdd reaches its rated minimum value
Enable/Disable Time
T_oe
–
–
130
ns
f = 115.20 MHz. For other frequencies, T_oe = 100 ns + 3 *
cycles
RMS Period Jitter
T_jitt
–
1.5
2.5
ps
f = 125 MHz, 2.25V to 3.63V
–
1.8
3
ps
f = 125 MHz, 1.8V
–
0.7
–
ps
f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
–
1.5
–
ps
f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz
Jitter
RMS Phase Jitter (random)
T_phj
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at
25 °C temperature.
SiTime Corporation
Rev. 1.01
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised June 18, 2015
SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Table 2. Pin Description
Pin
Top View
Symbol
Functionality
Output Enable
1
OE/NC
No Connect
H[3]: specified frequency output
L: output is high impedance. Only output driver is disabled.
OE/NC
1
4
VDD
GND
2
3
OUT
[3]
Any voltage between 0 and Vdd or Open : Specified frequency
output. Pin 1 has no function.
2
GND
Power
Electrical ground[4]
3
OUT
Output
Oscillator output
4
VDD
Power
Power supply voltage[4]
Figure 1. Pin Assignments
Notes:
3. In OE mode, a pull-up resistor of 10kΩ or less is recommended if pin 1 is not externally driven.
If pin 1 needs to be left floating, use the NC option.
4. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
N
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Min.
Max.
Unit
Storage Temperature
Parameter
-65
150
°C
Vdd
-0.5
4
V
Electrostatic Discharge
–
2000
V
Soldering Temperature (follow standard Pb free soldering guidelines)
–
260
°C
Junction Temperature[5]
–
150
°C
Note:
5.Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration[6]
JA, 4 Layer Board
JA, 2 Layer Board
JC, Bottom
7050
142
273
30
5032
97
199
24
3225
109
212
27
2520
117
222
26
2016
152
252
36
(°C/W)
Package
(°C/W)
(°C/W)
Note:
6. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table.
Table 5. Maximum Operating Junction Temperature[7]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
105°C
113°C
125°C
133°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Condition/Test Method
Mechanical Shock
MIL-STD-883F, Method 2002
Mechanical Vibration
MIL-STD-883F, Method 2007
Temperature Cycle
JESD22, Method A104
Solderability
MIL-STD-883F, Method 2003
Moisture Sensitivity Level
MSL1 @ 260°C
Rev. 1.01
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SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform[8]
Vdd
Vout
0.1µF
tr
3
4
Power
Supply
Test
Point
1
tf
80% Vdd
15pF
(including probe
and fixture
capacitance)
2
50%
20% Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
Vdd
1k
OE/NC Function
Figure 2. Test Circuit
Figure 3. Waveform
Note:
8. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
u
90% Vdd
Vdd
Vdd
50% Vdd
T_start
Pin 4 Voltage
[9]
No Glitch
during start up
OE Voltage
T_oe
CLK Output
CLK Output
HZ
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 4. Startup Timing (OE Mode)
Figure 5. OE Enable Timing (OE Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Disable Timing (OE Mode Only)
Note:
9. SiT8925 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.01
Page 3 of 12
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SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots[10]
1.8V
2.5V
2.8V
3.0V
3.3V
DUT 2
DUT 3
DUT 4
DUT 5
DUT 6
DUT 7
DUT 8
DUT 9
DUT 10
25
6.5
20
Frequency (ppm)
6.0
5.5
Idd (mA)
DUT 1
5.0
4.5
4.0
15
) 10
m
p 5
(p
y c
n 0
e
u ‐5
q
re
F ‐10
‐15
3.5
‐20
3.0
‐25
-55
-35
-15
5
25
45
65
85
105
125
‐55
‐35
‐15
5
Frequency (MHz)
Figure 7. Idd vs Frequency
2.5 V
2.8 V
3.0 V
1.8 V
3.3 V
4.0
55
3.5
54
2.5
2.0
1.5
1.0
85
105
125
2.5 V
2.8 V
3.0 V
3.3 V
52
51
50
49
48
47
0.5
46
119
121
123
125
127
129
131
133
135
45
119
137
121
123
125
Figure 9. RMS Period Jitter vs Frequency
1.8 V
2.5 V
2.8 V
127
129
131
133
135
137
Frequency (MHz)
Frequency (MHz)
3.0 V
Figure 10. Duty Cycle vs Frequency
1.8 V
3.3 V
2.5
2.5
2.0
2.0
Fall time (ns)
Rise time (ns)
65
53
3.0
0.0
1.5
1.0
0.5
2.5 V
2.8 V
3.0 V
3.3 V
1.5
1.0
0.5
0.0
0.0
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
Figure 11. 20%-80% Rise Time vs Temperature
Rev. 1.01
45
Figure 8. Frequency vs Temperature
Duty cycle (%)
RMS period jitter (ps)
1.8 V
25
Temperature (°C)
Temperature (°C)
Figure 12. 20%-80% Fall Time vs Temperature
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SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots[10]
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
1.8 V
2.0
1.0
1.8
0.9
2.5 V
2.8 V
3.0 V
3.3 V
IPJ (ps)
IPJ (ps)
0.8
1.6
1.4
1.2
1.0
115
0.7
0.6
0.5
120
125
130
0.4
115
135
Frequency (MHz)
120
125
130
135
Frequency (MHz)
Figure 13. RMS Integrated Phase Jitter Random
(12k to 20 MHz) vs Frequency[11]
Figure 14. RMS Integrated Phase Jitter Random
(900 kHz to 7.5 MHz) vs Frequency[11]
Notes:
10. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
11. Phase noise plots are measured with Agilent E5052B signal source analyzer.
Rev. 1.01
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SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Programmable Drive Strength
The SiT8925 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
• Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time.
• Improves the downstream clock receiver’s (RX) jitter by decreasing (speeding up) the clock rise/fall time.
• Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Applications Notes
section: http://www.sitime.com/support/application-notes.
EMI Reduction by Slowing Rise/Fall Time
Figure 15 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
trise=0.05
0
Harmonic amplitude (dB)
SiT8925 Drive Strength Selection
Tables 7 through 11 define the rise/fall time for a given capacitive load and supply voltage.
1. Select the table that matches the SiT8925 nominal supply
voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
2. Select the capacitive load column that matches the application requirement (5 pF to 30 pF)
3. Under the capacitive load column, select the desired
rise/fall times.
4. The left-most column represents the part number code for
the corresponding drive strength.
5. Add the drive strength code to the part number for ordering
purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 7 through
11, the maximum frequency the oscillator can operate with
guaranteed full swing of the output voltage over temperature
as follows:
trise=0.1
trise=0.15
trise=0.2
10
M a x F re q u e n c y =
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
-10
-20
1
5 x T rf_ 2 0 /8 0
where Trf_20/80 is the typical value for 20%-80% rise/fall
time.
-30
-40
Example 1
-50
-60
Calculate fMAX for the following condition:
-70
-80
The SiT8925 can support up to 30 pF in maximum capacitive
loads with up to 3 additional drive strength settings. Refer to
the Rise/Tall Time Tables (Table 7 to 11) to determine the
proper drive strength for the desired combination of output
load vs. rise/fall time.
1
3
5
7
9
11
Harm onic num ber
Figure 15. Harmonic EMI reduction as a Function of
Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to speed
up the rise/fall time of the input clock. Some chipsets may also
require faster rise/fall time in order to reduce their sensitivity to
this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to
Table 11) to determine the proper drive strength.
• Vdd = 3.3V (Table 11)
• Capacitive Load: 30 pF
• Desired Tr/f time = 1.46 ns (rise/fall time part number code
= U)
Part number for the above example:
SiT8925AAE12-18E-137.000000
Drive strength code is inserted here. Default setting is “-”
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3V SiT8925 device with
default drive strength setting, the typical rise/fall time is 0.46ns
for 5 pF output load. The typical rise/fall time slows down to 1
ns when the output load increases to 15 pF. One can choose
to speed up the rise/fall time to 0.72 ns by then increasing the
driven strength setting on the SiT8925 to “F”.
Rev. 1.01
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SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Rise/Fall Time (20% to 80%) vs CLOAD Tables
Table 7. Vdd = 1.8V Rise/Fall Times for Specific CLOAD
Table 8. Vdd = 2.5V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
5 pF
15 pF
Drive Strength \ C LOAD
5 pF
15 pF
T
0.93
n/a
R
1.45
n/a
E
0.78
n/a
B
1.09
n/a
U
F or "-": default
0.70
1.48
0.65
1.30
0.62
1.28
0.54
1.00
U
0.43
0.96
F
0.34
0.88
T or "-": default
E
Table 9. Vdd = 2.8V Rise/Fall Times for Specific CLOAD
Table 10. Vdd = 3.0V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ C LOAD
5 pF
15 pF
30 pF
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
n/a
R
1.29
n/a
n/a
R
1.22
n/a
B
0.97
n/a
n/a
0.89
n/a
n/a
T or "-": default
E
0.55
1.12
n/a
B
T or "-": default
0.51
1.00
n/a
0.44
1.00
n/a
E
0.38
0.92
n/a
U
0.34
0.88
n/a
0.83
n/a
0.29
0.81
1.48
U
F
0.30
F
0.27
0.76
1.39
Table 11. Vdd = 3.3V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
1.16
n/a
n/a
B
T or "-": default
0.81
n/a
n/a
0.46
1.00
n/a
E
0.33
0.87
n/a
U
F
0.28
0.79
1.46
0.25
0.72
1.31
Note:
12. “n/a” indicates that the resulting rise/fall time from the respective combination of the drive strength and output load does not provide rail-to-rail swing and is not
available.
Rev. 1.01
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SiT8925
High Frequency, Automotive AEC-Q100 Oscillator
The Smart Timing Choice
The Smart Timing Choice
Pin 1 Configuration Options (OE or NC)
Pin 1 of the SiT8925 can be factory-programmed to support
two modes: Output Enable (OE) or No Connect (NC). These
modes can also be programmed with the Time Machine using
field programmable devices.
In addition, the SiT8925 supports “no runt” pulses and “no
glitch” output during startup or when the output driver is
re-enabled from the OE disable mode as shown in the
waveform captures in Figure 16 and Figure 17.
Output Enable (OE) Mode
In the OE mode, applying logic low to the OE pin only disables
the output driver and puts it in Hi-Z mode. The core of the
device continues to operate normally. Power consumption is
reduced due to the inactivity of the output. When the OE pin is
pulled High, the output is typically enabled in