VP0808
P-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
•
The VP0808 Enhancement-mode (normally-off)
transistor uses a vertical DMOS structure and a
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power
handling capabilities of bipolar transistors and the high
input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
Free from Secondary Breakdown
Low Power Drive Requirement
Ease of Paralleling
Low CISS and Fast Switching Speeds
Excellent Thermal Stability
Integral Source-Drain Diode
High Input Impedance and High Gain
Applications
•
•
•
•
•
•
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance,
and fast switching speeds are desired.
Motor Controls
Converters
Amplifiers
Switches
Power Supply Circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Package Type
3-lead TO-92
(Top view)
DRAIN
SOURCE
GATE
See Table 2-1 for pin information.
2022 Microchip Technology Inc. and its subsidiaries
DS20006004A-page 1
VP0808
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ...................................................................................................................................... BVDSS
Drain-to-Gate Voltage ......................................................................................................................................... BVDGS
Gate-to-Source Voltage ......................................................................................................................................... ±30V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle
Parameter
Sym.
Min.
Drain-to-Source Breakdown Voltage
BVDSS
–80
—
—
V
Gate Threshold Voltage
VGS(th)
–1
—
–4.5
V
VGS = VDS, ID = –1 mA
Gate Body Leakage Current
Zero-Gate Voltage Drain Current
On-State Drain Current
Static Drain-to-Source On-State Resistance
Note 1:
Typ. Max.
Unit
Conditions
VGS = 0V, ID = –10 µA
—
—
–100
nA
VGS = ±20V, VDS = 0V
(Note 1)
—
—
–10
µA
VGS = 0V,
VDS = Maximum rating
—
—
–500
µA
VDS = 0.8 Maximum rating,
VGS = 0V, TA = 125°C
(Note 1)
ID(ON)
–1.1
—
—
A
VGS = –10V, VDS = –15V
RDS(ON)
—
—
5
Ω
VGS = –10V, ID = –1A
IGSS
IDSS
Specification is obtained by characterization and is not 100% tested.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All AC parameters are not 100% sample tested.
Parameter
Sym.
Min.
Forward Transconductance
GFS
200
—
—
Input Capacitance
CISS
—
—
150
pF
Common-Source Output Capacitance
COSS
—
—
60
pF
Reverse Transfer Capacitance
CRSS
—
—
25
pF
Turn-On Delay Time
td(ON)
—
—
15
ns
tr
—
—
40
ns
td(OFF)
—
—
30
ns
tf
—
—
30
ns
VSD
—
–1.2
—
V
Rise Time
Turn-Off Delay Time
Fall Time
DIODE PARAMETER
Diode Forward Voltage Drop
Note 1:
Typ. Max.
Unit
Conditions
mmho VDS = –10V, ID = –500 mA
VGS = 0V,
VDS = –25V,
f = 1 MHz
VDD = –25V,
ID = –500 mA,
RGEN = 25Ω
VGS = 0V, ISD = –900 mA
(Note 1)
Unless otherwise stated, all DC parameters are 100% tested at 25°C. Pulse test: 300 µs pulse, 2% duty
cycle
DS20006004A-page 2
2022 Microchip Technology Inc. and its subsidiaries
VP0808
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ. Max.
Unit
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
132
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
3-lead TO-92
THERMAL CHARACTERISTICS
Package
3-lead TO-92
Note 1:
ID (Note 1)
(Continuous)
(mA)
ID
(Pulsed)
(A)
Power Dissipation
at TA = 25°C
(W)
IDR (Note 1)
(mA)
IDRM
(A)
–280
–3
1
–280
–3
ID (continuous) is limited by maximum rated TJ.
2022 Microchip Technology Inc. and its subsidiaries
DS20006004A-page 3
VP0808
2.0
PIN DESCRIPTION
The details on the pins of VP0808 are listed in
Table 2-1. Refer to Package Type for the location of
pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
Source
2
Gate
Gate
3
Drain
Drain
DS20006004A-page 4
Description
Source
2022 Microchip Technology Inc. and its subsidiaries
VP0808
3.0
FUNCTIONAL DESCRIPTION
Figure 3-1 illustrates the switching waveforms and test
circuit for VP0808.
0V
INPUT
Pulse
Generator
10%
-10V
td(ON)
RGEN
90%
t(OFF)
t(ON)
tr
td(OFF)
D.U.T.
tf
INPUT
0V
90%
OUTPUT
10%
VDD
FIGURE 3-1:
TABLE 3-1:
OUTPUT
RL
90%
10%
VDD
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
ID(ON)
(Minimum)
(A)
–80
5
–1.1
2022 Microchip Technology Inc. and its subsidiaries
DS20006004A-page 5
VP0808
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20006004A-page 6
3-lead TO-92
Example
XXXXXX
X e3
YWWNNN
VP0808
L e3
232476
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2022 Microchip Technology Inc. and its subsidiaries
VP0808
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2022 Microchip Technology Inc. and its subsidiaries
DS20006004A-page 7
VP0808
NOTES:
DS20006004A-page 8
2022 Microchip Technology Inc. and its subsidiaries
VP0808
APPENDIX A:
REVISION HISTORY
Revision A (April 2022)
• Converted Supertex Doc# DSFP-VP0808 to
Microchip DS20006004A
• Changed the package marking format
• Removed the 3-Lead TO-92 L P002, P003, P005,
P013, and P014 media types to align packaging
specifications with the actual BQM
• Added some sections to comply with the standard
Microchip format
• Made minor text changes throughout the
document
2022 Microchip Technology Inc. and its subsidiaries
DS20006004A-page 9
VP0808
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
VP0808
=
P-Channel Enhancement-Mode Vertical
DMOS FET
Package:
L
=
3-lead TO-92
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
1000/Bag for an L Package
DS20006004A-page 10
Example:
a) VP0808L-G:
P-Channel EnhancementMode, Vertical DMOS FET,
3-lead TO-92, 1000/Bag
2022 Microchip Technology Inc. and its subsidiaries
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•
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•
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DS20006009A-page 11
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