AD9251

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9251 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 33 mW per channel at 20 MSPS 73 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit DNL = ±0.45 LSB Serial port control options Scalable analog input: 1 V p-p to 2 V p-p differential Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB SPI VIN+A ADC VIN–A PROGRAMMING DATA CMOS OUTPUT BUFFER ORA D13A D0A DCOA VREF SENSE VCM RBIAS VIN–B ADC VIN+B REF SELECT MUX OPTION AD9251 DRVDD CMOS OUTPUT BUFFER ORB D13B D0B DCOB DIVIDE 1 TO 8 DUTY CYCLE STABILIZER MODE CONTROLS 07938-001 CLK+ CLK– SYNC DCS PDWN DFS OEB Figure 1. PRODUCT HIGHLIGHTS 1. The AD9251 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9251 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR 2. 3. 4. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9251 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 AD9251-80 .................................................................................. 12 AD9251-65 .................................................................................. 14 AD9251-40 .................................................................................. 15 AD9251-20 .................................................................................. 16 Equivalent Circuits ......................................................................... 17 Theory of Operation ...................................................................... 19 ADC Architecture ...................................................................... 19 Analog Input Considerations.................................................... 19 Voltage Reference ....................................................................... 22 Clock Input Considerations ...................................................... 23 Power Dissipation and Standby Mode .................................... 25 Digital Outputs ........................................................................... 26 Timing ......................................................................................... 26 Built-In Self-Test (BIST) and Output Test .................................. 27 Built-In Self-Test (BIST) ............................................................ 27 Output Test Modes ..................................................................... 27 Channel/Chip Synchronization .................................................... 28 Serial Port Interface (SPI) .............................................................. 29 Configuration Using the SPI ..................................................... 29 Hardware Interface..................................................................... 30 Configuration Without the SPI ................................................ 30 SPI Accessible Features .............................................................. 30 Memory Map .................................................................................. 31 Reading the Memory Map Register Table............................... 31 Open Locations .......................................................................... 31 Default Values ............................................................................. 31 Memory Map Register Table ..................................................... 32 Memory Map Register Descriptions ........................................ 34 Applications Information .............................................................. 35 Design Guidelines ...................................................................... 35 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 36 REVISION HISTORY 7/09—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD9251 GENERAL DESCRIPTION The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus. The AD9251 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). Rev. 0 | Page 3 of 36 AD9251 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 MATCHING CHARACTERISTICS Offset Error Gain Error1 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 3 Input Common-Mode Voltage Input Common-Mode Range REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD2 IDRVDD2 (1.8 V) IDRVDD2 (3.3 V) POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Temp Full Full Full Full Full 25°C Full 25°C 25°C 25°C Full Full Full 25°C Full Full Full Full Full AD9251-20/AD9251-40 Min Typ Max 14 Guaranteed ±0.1 ±0.70 1.8 ±0.60 ±0.3 ±1.75 ±0.6 ±0.0 ±0.2 ±2 0.981 0.993 2 0.98 2 6 0.9 0.5 7.5 1.3 1.005 ±0.65 Min 14 AD9251-65 Typ Max Min 14 AD9251-80 Typ Max Unit Bits Guaranteed ±0.1 ±0.50 1.8 ±0.75 ±0.45 ±1.75 ±0.6 ±0.0 ±0.2 ±2 0.981 0.993 2 0.98 2 6 0.9 0.5 7.5 1.3 0.5 1.005 ±0.65 Guaranteed ±0.1 ±0.70 1.8 ±0.70 ±0.45 ±2.50 ±1.0 ±0.0 ±0.2 ±2 0.981 0.993 2 0.98 2 6 0.9 1.3 7.5 1.005 ±0.65 % FSR % FSR LSB LSB LSB LSB % FSR % FSR ppm/°C V mV LSB rms V p-p pF V V kΩ Full Full Full Full Full Full Full Full Full Full 1.7 1.7 1.8 1.9 3.6 39.4/52.8 1.7 1.7 1.8 1.9 3.6 72.9 1.7 1.7 1.8 1.9 3.6 85.5 V V mA mA mA mW mW mW mW mW 36.5/49.5 3.4/5.6 6.3/10.6 66/89 71.8/99 86.5/124 37/37 2.2 69.0 8.4 16.0 125 139.0 176.7 37 2.2 80.5 10.3 19.5 145 163.4 209 37 2.2 77.0/105.5 146.5 173 Standby Power 4 Power-Down Power 1 2 3 Measured with 1.0 V external reference. Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active. Rev. 0 | Page 4 of 36 AD9251 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz T WO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) CROSSTALK 2 ANALOG INPUT BANDWIDTH 1 2 Temp 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C Full 25°C AD9251-20/AD9251-40 Min Typ Max 74.7 74.4 73.6 73.7 71.5 74.6 74.3 73.4 73.6 70.0 12.0 12.0 11.9 11.3 −95 −95 −81 −94 −80 95 94 81 93 80 −98 −98 -90 −98 −95 90 −110 700 Min AD9251-65 Typ Max 74.5 74.3 Min AD9251-80 Typ Max 74.3 74.1 73.6 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz 73.6 73.7 72.5 71.5 74.4 74.2 73.4 73.6 72.4 70.0 12.0 12.0 11.9 11.3 −95 −95 −81 −94 −80 95 94 81 93 81 80 −98 −98 −90 −98 −95 90 −110 700 −96 −89 −95 90 −110 700 80 −97 −97 92 −92 −81 −80 93 93 70.0 12.0 12.0 11.9 11.3 −93 −93 73.5 71.5 74.1 74.0 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. 0 | Page 5 of 36 AD9251 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (CSB)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 μA High Level Output Voltage, IOH = 0.5 mA Low Level Output Voltage, IOL = 1.6 mA Low Level Output Voltage, IOL = 50 μA DRVDD = 1.8 V High Level Output Voltage, IOH = 50 μA High Level Output Voltage, IOH = 0.5 mA Low Level Output Voltage, IOL = 1.6 mA Low Level Output Voltage, IOL = 50 μA 1 2 Temp Min AD9251-20/AD9251-40/AD9251-65/AD9251-80 Typ Max CMOS/LVDS/LVPECL 0.9 Unit Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 0.2 GND − 0.3 −10 −10 8 10 4 3.6 AVDD + 0.2 +10 +10 12 V V p-p V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF 1.2 0 −50 −10 30 2 1.2 0 −10 40 26 2 1.2 0 −10 40 26 5 DRVDD + 0.3 0.8 −75 +10 DRVDD + 0.3 0.8 +10 135 DRVDD + 0.3 0.8 +10 130 Full Full Full Full Full Full Full Full 3.29 3.25 0.2 0.05 1.79 1.75 0.2 0.05 V V V V V V V V Internal 30 kΩ pull-down. Internal 30 kΩ pull-up. Rev. 0 | Page 6 of 36 AD9251 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) Wake-Up Time 2 Standby OUT-OF-RANGE RECOVERY TIME 1 2 Temp Full Full Full Full Full Full Full Full Full Full Full Full AD9251-20/AD9251-40 Min Typ Max 625 20/40 25.0/12.5 1.0 0.1 3 3 0.1 9 350 600/400 2 Min AD9251-65 Typ Max 625 65 7.69 1.0 0.1 3 3 0.1 9 350 300 2 Min AD9251-80 Typ Max 625 80 6.25 1.0 0.1 3 3 0.1 9 350 260 2 Unit MHz MSPS ns ns ns ps rms ns ns ns Cycles μs ns Cycles 3 50/25 3 15.38 3 12.5 Conversion rate is the clock rate after the CLK divider. Wake-up time is dependent on the value of the decoupling capacitors. N–1 N VIN N+1 N+2 tA N+3 N+4 N+5 tCH CLK+ CLK– tCLK tDCO DCOA/DCOB tSKEW 07938-002 07938-003 CH A/CH B DATA N–9 N–8 N–7 N–6 N–5 tPD Figure 2. CMOS Output Data Timing N–1 N VIN tA N+3 N+1 N+4 N+5 N+2 tCH CLK+ CLK– tCLK tDCO DCOA/DCOB tSKEW CH A/CH B DATA CH A N–9 CH B N–9 CH A N–8 CH B N–8 CH A N–7 CH B N–7 CH A N–6 CH B N–6 CH A N–5 tPD Figure 3. CMOS Interleaved Output Timing Rev. 0 | Page 7 of 36 AD9251 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Conditions SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 10 Min Typ 0.24 0.40 Max Unit ns ns ns ns ns ns ns ns ns ns ns CLK+ tSSYNC SYNC tHSYNC 07938-004 Figure 4. SYNC Input Timing Requirements Rev. 0 | Page 8 of 36 AD9251 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND D0A/D0B through D13A/D13B to AGND DCOA/DCOB to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −40°C to +85°C 150°C −65°C to +150°C THERMAL CHARACTERISTICS The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the user’s circuit board. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Airflow Velocity (m/sec) 0 1.0 2.5 Package Type 64-Lead LFCSP 9 mm × 9 mm (CP-64-4) 1 2 3 θJA1, 2 23 20 18 θJC1, 3 2.0 θJB1, 4 12 Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 9 of 36 AD9251 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CLK+ CLK– SYNC NC NC (LSB) D0B D1B D2B D3B DRVDD D4B D5B D6B D7B D8B D9B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9251 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D13A (MSB) D12A D11A D10A D9A DRVDD D8A D7A D6A D5A NOTES 1. NC = NO CONNECT 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. D10B D11B DRVDD D12B (MSB) D13B ORB DCOB DCOA NC NC (LSB) D0A DRVDD D1A D2A D3A D4A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 5. Pin Configuration Table 8. Pin Function Description Pin No. 0 1, 2 3 4, 5, 25, 26 6 to 9, 11 to 18, 20, 21 10, 19, 28, 37 22 23 24 27, 29 to 36, 38 to 42 43 44 Mnemonic GND CLK+, CLK− SYNC NC D0B to D13B DRVDD ORB DCOB DCOA D0A to D13A ORA SDIO/DCS Description Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. Do Not Connect. Channel B Digital Outputs. D13B = MSB. Digital Output Driver Supply (1.8 V to 3.3 V). Channel B Out-of-Range Digital Output. Channel B Data Clock Digital Output. Channel A Data Clock Digital Output. Channel A Digital Outputs. D13A = MSB. Channel A Out-of-Range Digital Output. SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pulldown in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high = twos complement output. DFS low = offset binary output. SPI Chip Select. Active low enable; 30 kΩ internal pull-up. Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high. 30 kΩ internal pull-down. Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation. Rev. 0 | Page 10 of 36 45 SCLK/DFS 46 47 48 CSB OEB PDWN 07938-005 AD9251 Pin No. 49, 50, 53, 54, 59, 60, 63, 64 51, 52 55 56 57 58 61, 62 Mnemonic AVDD VIN+A, VIN−A VREF SENSE VCM RBIAS VIN−B, VIN+B Description 1.8 V Analog Supply Pins. Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev. 0 | Page 11 of 36 AD9251 TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –15 –30 80MSPS 9.7MHz @ –1dBFS SNR = 73.4dB (74.4dBFS) SFDR = 94.4dBc 0 –15 –30 80MSPS 30.5MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 93.6dBc AMPLITUDE (dBFS) AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 07938-033 –45 –60 –75 –90 –105 –120 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 07938-034 3 2 6 5 4 3 5 2 6 4 Figure 6. AD9251-80 Single-Tone FFT with fIN = 9.7 MHz 0 –15 –30 80MSPS 70.3MHz @ –1dBFS SNR = 72.1dB (73.1dBFS) SFDR = 93.5dBc Figure 9. AD9251-80 Single-Tone FFT with fIN = 30.5 MHz 0 –15 –30 80MSPS 200MHz @ –1dBFS SNR = 70.5dB (71.5dBFS) SFDR = 80.2dBc AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 07938-062 AMPLITUDE (dBFS) –45 –60 –75 2 –90 –105 –120 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 46 5 3 2 6 3 5 4 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 Figure 7. AD9251-80 Single-Tone FFT with fIN = 70.3 MHz 0 –15 –30 80MSPS 30.5MHz @ –7dBFS 32.5MHz @ –7dBFS SFDR = 89.5dBc (96.5dBFS) Figure 10. AD9251-80 Single-Tone FFT with fIN = 200 MHz 0 –20 AMPLITUDE (dBFS) –45 –60 –75 –90 SFDR/IMD3 (dBc/dBFS) SFDR (dBc) –40 IMD3 (dBc) –60 F2 – F1 –105 2F1 + F2 2F2 + F1 F1 + F2 –80 SFDR (dBFS) –100 IMD3 (dBFS) 07938-054 2F2 – F1 2F1 – F2 –120 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 07938-200 –120 –90 –78 Figure 8. AD9251-80 Two-Tone FFT with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz –66 –54 –42 –30 INPUT AMPLITUDE (dBFS) –18 –6 Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz Rev. 0 | Page 12 of 36 07938-036 AD9251 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 90 80 SFDR (dBc) 100 120 SFDRFS SNR/SFDR (dBFS/dBc) 60 50 40 30 20 10 07938-057 SNR/SFDR (dBFS) 70 SNR (dBFS) 80 SNRFS 60 SFDR 40 SNR 20 0 50 100 150 INPUT FREQUENCY (MHz) 200 –80 –60 –40 INPUT AMPLITUDE (dBFS) –20 0 Figure 12. AD9251-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 120 SFDR (dBc) 100 Figure 15. AD9251-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 450,000 400,000 350,000 SNR/SFDR (dBFS/dBc) NUMBER OF HITS 80 SNR (dBFS) 300,000 250,000 200,000 150,000 100,000 60 40 20 50,000 07938-055 07938-048 07938-037 0 10 0 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 OUTPUT CODE 20 30 40 50 60 SAMPLE RATE (MSPS) 70 80 Figure 13. AD9251-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 0.5 0.4 0.3 1.0 0.2 2.0 1.5 Figure 16. Grounded Input Histogram DNL ERROR (LSB) INL ERROR (LSB) 0.1 0 –0.1 –0.2 0.5 0 –0.5 –1.0 –0.3 –0.4 07938-038 –1.5 –2.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE –0.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE Figure 14. DNL Error with fIN = 9.7 MHz Figure 17. INL with fIN = 9.7 MHz Rev. 0 | Page 13 of 36 07938-061 0 0 –90 AD9251 AD9251-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –15 –30 65MSPS 9.7MHz @ –1dBFS SNR = 73.5dB (74.5dBFS) SFDR = 97.7dBc 120 SFDRFS 100 AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 07938-030 SNR/SFDR (dBFS) 80 SNRFS 60 SFDR 40 SNR 6 5 2 4 3 20 3 6 9 12 15 18 21 FREQUENCY (MHz) 24 27 30 –80 –60 –40 INPUT AMPLITUDE (dBFS) –20 0 Figure 18. AD9251-65 Single-Tone FFT with fIN = 9.7 MHz 0 –15 –30 65MSPS 70.3MHz @ –1dBFS SNR = 72.6dB (73.6dBFS) SFDR = 94.1dBc Figure 21.AD9251-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 100 90 80 SFDR (dBc) SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) 70 60 50 40 30 20 10 –45 –60 –75 –90 –105 –120 07938-032 SNR (dBFS) 2 3 4 5 6 3 6 9 12 15 18 21 FREQUENCY (MHz) 24 27 30 0 50 100 150 INPUT FREQUENCY (MHz) 200 Figure 19. AD9251-65 Single-Tone FFT with fIN = 70.3 MHz 0 –15 –30 Figure 22. AD9251-65 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 65MSPS 30.5MHz @ –1dBFS SNR = 73.3dB (74.3dBFS) SFDR = 99.3dBc AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 3 6 9 12 15 18 21 FREQUENCY (MHz) 24 27 30 07938-031 2 4 6 5 3 Figure 20. AD9251-65 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 14 of 36 07938-056 0 07938-060 0 –90 AD9251 AD9251-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –15 –30 –45 –60 –75 –90 –105 –120 07938-028 40MSPS 9.7MHz @ –1dBFS SNR = 73.5dB (74.5dBFS) SFDR = 95.4dBc 120 SFDRFS 100 SNR/SFDR (dBFS) AMPLITUDE (dB) 80 SNRFS 60 SFDR 40 SNR 4 5 3 6 2 20 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 –80 –60 –40 INPUT AMPLITUDE (dBFS) –20 0 Figure 23. AD9251-40 Single-Tone FFT with fIN = 9.7 MHz 0 –15 –30 Figure 25. AD9251-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 40MSPS 30.5MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 95.7dBc AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 07938-029 4 5 3 6 2 Figure 24. AD9251-40 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 15 of 36 07938-059 0 –90 AD9251 AD9251-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –15 –30 20MSPS 9.7MHz @ –1dBFS SNR = 73.5dBFS (74.5dBFS) SFDR = 97.2dBc 120 SFDR (dBFS) 100 SNR/SFDR (dBc/dBFS) AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 07938-024 80 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) 20 2 4 6 53 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 FREQUENCY (MHz) –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 Figure 26. AD9251-20 Single-Tone FFT with fIN = 9.7 MHz 0 –15 –30 20MSPS 30.5MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 98.1dBc Figure 28. AD9251-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz AMPLITUDE (dBFS) –45 –60 –75 –90 –105 –120 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 FREQUENCY (MHz) 07938-026 2 4 6 5 3 Figure 27. AD9251-20 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 16 of 36 07938-058 0 –100 AD9251 EQUIVALENT CIRCUITS AVDD DRVDD VIN±x Figure 29. Equivalent Analog Input Circuit Figure 32. Equivalent Digital Output Circuit CLK+ 5Ω 15kΩ 0.9V 15kΩ 5Ω CLK– SCLK/DFS, SYNC, OEB, AND PDWN 350Ω 30kΩ 07938-043 DRVDD 07938-040 Figure 30. Equivalent Clock Input Circuit Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit AVDD AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ 07938-041 RBIAS AND VCM 375Ω 07938-042 07938-039 Figure 31. Equivalent SDIO/DCS Input Circuit Figure 34. Equivalent RBIAS, VCM Circuit Rev. 0 | Page 17 of 36 07938-044 AD9251 DRVDD AVDD AVDD 350Ω CSB 30kΩ 375Ω VREF 07938-045 07938-047 7.5kΩ Figure 35. Equivalent CSB Input Circuit Figure 37. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit 07938-046 Rev. 0 | Page 18 of 36 AD9251 THEORY OF OPERATION The AD9251 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input is permitted, but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9251 can be used as a baseband or direct downconversion receiver, where one ADC is used for I input data and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. Programming and control of the AD9251 is accomplished using a 3-bit SPI-compatible serial interface. VIN–x ANALOG INPUT CONSIDERATIONS The analog input to the AD9251 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. H CPAR VIN+x H CSAMPLE S S S S CSAMPLE CPAR H H 07938-006 ADC ARCHITECTURE The AD9251 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. Figure 38. Switched-Capacitor Input Circuit The clock signal alternately switches the input circuit between sample-and-hold mode (see Figure 38). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Rev. 0 | Page 19 of 36 AD9251 Input Common Mode VIN 200Ω 76.8Ω 90Ω 33Ω VIN–x The analog inputs of the AD9251 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 39 and Figure 40. An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. 100 SFDR (dBc) 90 SNR/SFDR (dBFS/dBc) AVDD ADA4938 0.1µF 120Ω 200Ω 10pF ADC VIN+x VCM 07938-007 33Ω Figure 41. Differential Input Configuration Using the ADA4938-2 For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer-coupling is the recommended input configuration. An example is shown in Figure 42. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. VIN+x R 2V p-p 49.9Ω R VIN–x C ADC VCM 07938-008 80 SNR (dBFS) 70 0.1µF Figure 42. Differential Transformer-Coupled Configuration 60 The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. 0.6 0.7 0.8 0.9 1.0 1.1 INPUT COMMON-MODE VOLTAGE (V) 1.2 1.3 Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 32.1 MHz, fS = 80 MSPS 100 07938-049 50 0.5 At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9251. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 44). An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 45. See the AD8352 data sheet for more information. In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 9. Example RC Network SFDR (dBc) 90 SNR/SFDR (dBFS/dBc) 80 SNR (dBFS) 70 60 07938-050 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 INPUT COMMON-MODE VOLTAGE (V) 1.2 1.3 Figure 40. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 10.3 MHz, fS = 20 MSPS Frequency Range (MHz) 0 to 70 70 to 200 R Series (Ω Each) 33 125 C Differential (pF) 22 Open Differential Input Configurations Optimum performance is achieved while driving the AD9251 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9251 (see Figure 41), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Rev. 0 | Page 20 of 36 AD9251 Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 43 shows a typical single-ended input configuration. 1V p-p 49.9Ω 10µF AVDD 1kΩ 0.1µF 1kΩ C R 07938-009 R VIN+x AVDD 1kΩ 10µF 0.1µF 1kΩ ADC VIN–x Figure 43. Single-Ended Input Configuration 0.1µF 2V p-p PA S S P 0.1µF 25Ω 0.1µF R VIN–x 0.1µF 25Ω C R VIN+x ADC VCM 07938-010 Figure 44. Differential Double Balun Input Configuration VCC 0.1µF ANALOG INPUT 0Ω 16 1 2 CD RD RG 3 4 ANALOG INPUT 5 0.1µF 0Ω 14 0.1µF 0.1µF 8, 13 11 0.1µF 0.1µF R 200Ω VIN+x C 0.1µF 200Ω R VIN–x VCM 07938-011 AD8352 10 ADC Figure 45. Differential Input Configuration Using the AD8352 Rev. 0 | Page 21 of 36 AD9251 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9251. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference. In either internal or external reference mode, the maximum input range of the ADC can be varied by configuring SPI Address 0x18 as shown in Table 11, resulting in a selectable differential span from 1 V p-p to 2 V p-p. If the internal reference of the AD9251 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 47 shows how the internal reference voltage is affected by loading. 0 Internal Reference Connection A comparator within the AD9251 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 46), setting VREF to 1.0 V. REFERENCE VOLTAGE ERROR (%) –0.5 –1.0 INTERNAL VREF = 0.993V –1.5 VIN+A/VIN+B VIN–A/VIN–B –2.0 ADC CORE –2.5 VREF 1.0µF 0.1µF SELECT LOGIC SENSE 0.5V 07938-012 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) Figure 47. VREF Accuracy vs. Load Current ADC Figure 46. Internal Reference Configuration Table 10. Reference Configuration Summary Selected Mode Fixed Internal Reference Fixed External Reference SENSE Voltage (V) AGND to 0.2 AVDD Resulting VREF (V) 1.0 internal 1.0 applied to external VREF pin Resulting Differential Span (V p-p) 2.0 2.0 Table 11. Scaled Differential Span Summary Selected Mode Fixed Internal or External Reference Fixed Internal or External Reference Fixed Internal or External Reference Fixed Internal or External Reference Fixed Internal or External Reference Resulting VREF (V) 1.0 (internal or external) 1.0 (internal or external) 1.0 (internal or external) 1.0 (internal or external) 1.0 (internal or external) SPI Register 0x18 (Hex) 0xC0 0xC8 0xD0 0xD8 0xE0 Resulting Differential Span (V p-p) 1.0 1.14 1.33 1.6 2.0 Rev. 0 | Page 22 of 36 07938-014 –3.0 AD9251 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 48 shows the typical drift characteristics of the internal reference in 1.0 V mode. 4 3 2 VREF ERROR (mV) VREF ERROR (mV) 1 0 –1 –2 –3 –4 –5 07938-052 Clock Input Options The AD9251 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 50 and Figure 51 show two preferred methods for clocking the AD9251 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer or an RF balun. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9251 to approximately 0.8 V p-p differential. –6 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 48. Typical VREF Drift 0.1µF CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9251 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 49) and require no external bias. AVDD Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) 1nF CLOCK INPUT 50Ω 0.1µF CLK+ 0.1µF ADC CLK– SCHOTTKY DIODES: HSMS2822 07938-018 1nF 0.9V CLK+ CLK– Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz) 2pF 2pF 07938-016 Figure 49. Equivalent Clock Input Circuit Rev. 0 | Page 23 of 36 07938-017 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 37). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9251 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. Mini-Circuits® ADT1-1WT, 1:1 Z 0.1µF CLOCK INPUT 50Ω 100Ω 0.1µF SCHOTTKY DIODES: HSMS2822 XFMR 0.1µF CLK+ ADC CLK– AD9251 If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. Input Clock Divider The AD9251 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. Optimum performance will be obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. The AD9251 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. 0.1µF CLOCK INPUT 0.1µF CLOCK INPUT 50kΩ 50kΩ AD951x PECL DRIVER 240Ω 240Ω 0.1µF CLK+ 100Ω 0.1µF CLK– 07938-019 ADC Figure 52. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 53. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9251 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9251. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 55. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. 80 0.1µF CLOCK INPUT 0.1µF CLOCK INPUT 50kΩ 50kΩ AD951x LVDS DRIVER 0.1µF CLK+ 100Ω 0.1µF CLK– 07938-020 ADC Figure 53. Differential LVDS Sample Clock (Up to 625 MHz) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 54). VCC 0.1µF CLOCK INPUT 50Ω 1 1kΩ 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ ADC CLK– 07938-021 0.1µF 150Ω DCS ON 75 70 65 DCS OFF 60 55 50 45 07938-053 RESISTOR IS OPTIONAL. Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) SNR (dBFS) 40 10 20 30 40 50 60 POSITIVE DUTY CYCLE (%) 70 80 Figure 55. SNR vs. DCS On/Off Rev. 0 | Page 24 of 36 AD9251 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ] In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 56. 80 75 POWER DISSIPATION AND STANDBY MODE As shown in Figure 57, the analog core power dissipated by the AD9251 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD × CLOAD × fCLK × N where N is the number of output bits (30, in the case of the AD9251). This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 57 was taken using the same operating conditions as those used for the Typical Performance Characteristics, with a 5 pF load on each output driver. 150 0.05ps 70 0.2ps SNR (dBFS) 65 60 55 50 3.0ps 1 10 100 0.5ps 1.0ps 1.5ps 2.0ps 2.5ps 1k 07938-022 45 FREQUENCY (MHz) Figure 56. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9251. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. See the AN-501 Application Note and the AN-756 Application Note available on www.analog.com for more information. ANALOG CORE POWER (mW) 130 AD9251-80 110 AD9251-65 90 AD9251-40 70 AD9251-20 0 10 20 30 40 50 CLOCK RATE (MSPS) 60 70 80 07938-051 50 Figure 57. AD9251 Analog Core Power vs. Clock Rate Rev. 0 | Page 25 of 36 AD9251 The AD9251 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2.2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9251 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 12. SCLK/DFS Mode Selection (External Pin Mode) Voltage at Pin AGND DRVDD SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) Digital Output Enable Function (OEB) The AD9251 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI interface. If the OEB pin is low, the output data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the output disable (OEB) bit (Bit 4) in Register 0x14. DIGITAL OUTPUTS The AD9251 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families. Output data can also be multiplexed onto a single output bus to reduce the total number of traces required. The CMOS output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12). TIMING The AD9251 provides latched data with a pipeline delay of 9 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9251. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9251 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9251 provides two data clock output (DCO) signals intended for capturing the data in an external register. The CMOS data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 13. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) < −VREF − 0.5 LSB = −VREF =0 = +VREF − 1.0 LSB > +VREF − 0.5 LSB Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 OR 1 0 0 0 1 Rev. 0 | Page 26 of 36 AD9251 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9251 includes a built-in test feature designed to enable verification of the integrity of each channel as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9251 is included. Various output test options are also provided to place predictable values on the outputs of the AD9251. generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation will not equal the predetermined value at the end of the test. At that point, the user will need to rely on verifying the output data. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9251 signal path. Perform the BIST test after a reset to ensure the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. Once completed, the BIST compares the signature results with a pre-determined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying the test passed. If the BIST test failed, Bit 0 of Register 0x24 is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence OUTPUT TEST MODES The output test options are described in Table 17 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 27 of 36 AD9251 CHANNEL/CHIP SYNCHRONIZATION The AD9251 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. Drive the SYNC input using a single-ended CMOS-type signal. Rev. 0 | Page 28 of 36 AD9251 SERIAL PORT INTERFACE (SPI) The AD9251 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 58 and Table 5. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits as shown in Figure 58. All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK, the SDIO, and the CSB (see Table 14). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) is an activelow control that enables or disables the read and write cycles. Table 14. Serial Port Interface Pins Pin SCLK SDIO Function Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip Select Bar. An active-low control that gates the read and write cycles. CSB tDS tS CSB tHIGH tDH tLOW tCLK tH SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Port Interface Timing Diagram Rev. 0 | Page 29 of 36 07938-023 AD9251 HARDWARE INTERFACE The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9251. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9251 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SDIO/DCS and SCLK/DFS serve a dual function when the SPI interface is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9251. Table 15. Mode Selection Pin SDIO/DCS SCLK/DFS OEB PDWN External Voltage AVDD (default) AGND AVDD AGND (default) AVDD AGND (default) AVDD AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs in high impedance Outputs enabled Chip in power-down or standby Normal operation SPI ACCESSIBLE FEATURES Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The ADA9251 part-specific features are described in detail in Table 17. Table 16. Features Accessible Using the SPI Feature Mode Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, connect the CSB chip select to AVDD, which disables the serial port interface. Rev. 0 | Page 30 of 36 AD9251 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 17) has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); the program registers, including setup, control, and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 and Address 0x101). Table 17 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF register, has a hexadecimal default value of 0xE0. This means that in Address 0x18 Bit[7:5] = 1, and the remaining Bits[4:0] = 0. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to register 0xFF. The remaining registers, Register 0x100 and Register 0x101, are documented in the Memory Map Register Descriptions section following Table 17. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Channel-Specific Registers Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9251 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). Rev. 0 | Page 31 of 36 AD9251 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 SPI port 0 configuration (global) Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Comments The nibbles are mirrored so that LSB- or MSB-first mode registers correctly, regardless of shift mode Unique chip ID used to differentiate devices; read only Unique speed grade ID used to differentiate devices; read only 0x01 Chip ID (global) 8-bit chip ID bits [7:0] AD9251 = 0x23 0x02 Chip grade (global) Open Speed grade ID 6:4 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Open Open Open Open Device Index and Transfer Registers 0x05 Channel index Open Open Open ADC B default ADC A default 0xFF 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Bits are set to determine which device on chip receives the next write command; the default is all devices on chip Synchronously transfers data from the master shift register to the slave Determines various generic modes of chip operation Program Registers (May or May Not Be Indexed by Device Index) Open External pin function 0x08 Modes External 0x00 full powerpowerdown down 0x01 standby enable (local) (local) Open 0x09 Clock (global) Open Open Open Open 0x0B Clock divide (global) Open 00 = chip run 01 = full powerdown 10 = standby 11 = chip wide digital reset (local) Open Duty cycle stabilize Clock divider [2:0] Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x80 0x00 0x00 The divide ratio is the value plus 1 Rev. 0 | Page 32 of 36 AD9251 Addr (Hex) 0x0D Register Name Test mode (local) Bit 7 (MSB) Bit 6 User test mode (local) 00 = single 01 = alternate 10 = single once 11 = alternate once Bit 5 Reset PN long gen Bit 4 Reset PN short gen Bit 3 Bit 2 Bit 1 Output test mode [3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency Open BIST INIT Open BIST enable Bit 0 (LSB) Default Value (Hex) 0x00 Comments When set, the test data is placed on the output pins in place of normal data 0x0E BIST enable Open 0x00 0x10 0x14 Offset adjust (local) Output mode 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 00 = 3.3 V CMOS Output mux Output Open Output 10 = 1.8 V CMOS enable disable invert (interleaved) (local) (local) 0x00 0x00 When Bit 0 is set, the BIST function is initiated Device offset trim Configures the outputs and the format of the data 0x15 OUTPUT_ADJUST 0x16 OUTPUT_PHASE 3.3 V DCO drive strength 00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes DCO output polarity 0= normal 1= inverted (local) 1.8 V DCO drive strength 00 = 1 stripe 01 = 2 stripes 10 = 3 stripes (default) 11 = 4 stripes 00 = offset binary 01 = twos complement 10 = gray code 11 = offset binary (local) 1.8 V data 3.3 V data drive strength drive strength 00 = 1 stripe 00 = 1 stripe 01 = 2 stripes (default) 10 = 3 stripes 01 = 2 stripes (default) 10 = 3 stripes 11 = 4 stripes 11 = 4 stripes Input clock phase adjust [2:0] (Value is number of input clock cycles of phase delay) 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles DCO/Data delay[2:0] 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x22 Determines CMOS output drive strength properties 0x00 On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock; internal latching is unaffected This sets the fine output delay of the output clock but does not change internal timing 0x17 OUTPUT_DELAY Enable DCO delay Enable data delay 0x00 0x18 VREF Reserved =11 0x19 0x1A 0x1B 0x1C USER_PATT1_LSB USER_PATT1_MSB USER_PATT2_LSB USER_PATT2_MSB B7 B15 B7 B15 B6 B14 B6 B14 Internal VREF adjustment [2:0] 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.60 V p-p 100 = 2.0 V p-p B5 B4 B3 B13 B5 B13 B12 B4 B12 B11 B3 B11 0xE0 Select and/or adjust the VREF B2 B10 B2 B10 B1 B9 B1 B9 B0 B8 B0 B8 0x00 0x00 0x00 0x00 User-defined pattern, 1 LSB User-defined pattern, 1 MSB User-defined pattern, 2 LSB User-defined pattern, 2 MSB Rev. 0 | Page 33 of 36 AD9251 Addr (Hex) 0x24 Register Name MISR_LSB Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open Bit 2 Open Bit 1 Open Bit 0 (LSB) B0 Default Value (Hex) 0x00 Comments Least significant byte of MISR; read only Disable the OR pin for the indexed channel Assign an ADC to an output channel 0x2A Features Open Open Open Open Open Open Open OR OE (local) 0 = ADC A 1 = ADC B (local) 0x01 0x2E Output assign Open Open Open Open Open Open Open Ch A = 0x00 Ch B = 0x01 0x01 Digital Feature Control 0x100 Sync control (global) Open Open Open Open Open 0x101 USR2 Enable OEB Pin 47 (local) Open Open Open Enable GCLK detect Clock divider next sync only Run GCLK Clock divider sync enable Open Master sync enable Disable SDIO pulldown 0x88 Enables internal oscillator for clock rates < 5 MHz MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. USR2 (Register 0x101) Bit 7—Enable OEB Pin 47 Normally set high, this bit allows Pin 47 to function as the output enable. If it is set low, it disables Pin 47. Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync enable bit (Address 0x100, Bit 0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs. Bit 3—Enable GCLK Detect Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS. When a low encode rate is detected an internal oscillator, GCLK, is enabled ensuring the proper operation of several circuits. If set low the detector is disabled. Bit 2—Run GCLK This bit enables the GCLK oscillator. For some applications with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 and Bit 0 are high and the device is operating in continuous sync mode as long as Bit 2 of the sync control is low. Bit 0—Disable SDIO Pull-Down This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. Rev. 0 | Page 34 of 36 AD9251 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9251 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. Power and Ground Recommendations When connecting power to the AD9251, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD supply must be used, the AVDD and DRVDD domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9251. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 42. RBIAS The AD9251 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection for the AD9251; therefore, it must be connected to analog ground (AGND) on the customer’s PCB. To achieve the best electrical and thermal performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the AD9251 exposed paddle, Pin 0. Reference Decoupling Externally decoupled the VREF pin to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9251 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 35 of 36 AD9251 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 49 48 64 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 6.35 6.20 SQ 6.05 0.50 0.40 0.30 33 32 16 17 0.25 MIN 7.50 REF 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model AD9251BCPZ-80 1, 2 AD9251BCPZRL7-801, 2 AD9251BCPZ-651, 2 AD9251BCPZRL7-651, 2 AD9251BCPZ-401, 2 AD9251BCPZRL7-401, 2 AD9251BCPZ-201, 2 AD9251BCPZRL7-201, 2 AD9251-80EBZ1 AD9251-65EBZ1 AD9251-40EBZ1 AD9251-20EBZ1 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Evaluation Board Evaluation Board Evaluation Board 091707-C Package Option CP-64-4 CP-64-4 CP-64-4 CP-64-4 CP-64-4 CP-64-4 CP-64-4 CP-64-4 Z = RoHS Compliant Part. The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07938-0-7/09(0) Rev. 0 | Page 36 of 36