ADF4360-1BCPRL7

Integrated Synthesizer and VCO ADF4360-1 FEATURES GENERAL DESCRIPTION Output frequency range: 2050 MHz to 2450 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4360-1 is a fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-1 is designed for a center frequency of 2250 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF output of between 1025 MHz and 1225 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD CE RSET ADF4360-1 MUXOUT MULTIPLEXER 14-BIT R COUNTER REFIN LOCK DETECT CLK DATA MUTE 24-BIT FUNCTION LATCH 24-BIT DATA REGISTER LE CHARGE PUMP CP PHASE COMPARATOR VVCO VTUNE CC CN INTEGER REGISTER RFOUTA VCO CORE 13-BIT B COUNTER 5-BIT A COUNTER MULTIPLEXER N = (BP + A) RFOUTB LOAD LOAD AGND DGND DIVSEL = 1 DIVSEL = 2 ÷2 04414-001 PRESCALER P/P+1 OUTPUT STAGE CPGND Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADF4360-1 TABLE OF CONTENTS Specifications..................................................................................... 3 VCO ............................................................................................. 10 Timing Characteristics..................................................................... 5 Output Stage................................................................................ 11 Absolute Maximum Ratings............................................................ 6 Latch Structure ........................................................................... 12 Transistor Count........................................................................... 6 Power-Up..................................................................................... 16 ESD Caution.................................................................................. 6 Control Latch .............................................................................. 18 Pin Configuration and Function Descriptions............................. 7 N Counter Latch......................................................................... 19 Typical Performance Characteristics ............................................. 8 R Counter Latch ......................................................................... 19 Circuit Description........................................................................... 9 Applications..................................................................................... 20 Reference Input Section............................................................... 9 Direct Conversion Modulator .................................................. 20 Prescaler (P/P + 1)........................................................................ 9 Fixed Frequency LO................................................................... 21 A and B Counters ......................................................................... 9 Interfacing ................................................................................... 21 R Counter ...................................................................................... 9 PCB Design Guidelines for Chip-Scale Package.......................... 22 PFD and Charge Pump................................................................ 9 Output Matching ........................................................................ 22 MUXOUT and Lock Detect...................................................... 10 Outline Dimensions ....................................................................... 23 Input Shift Register..................................................................... 10 Ordering Guide .......................................................................... 23 REVISION HISTORY 12/04—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Specifications ................................................................ 3 Changes to the Timing Characteristics ......................................... 5 Changes to the Power-Up Section................................................ 16 Added Table 10 ............................................................................... 16 Added Figure 16.............................................................................. 16 Changes to Ordering Guide .......................................................... 23 Updated Outline Dimensions ....................................................... 23 6/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specifications ................................................................ 3 Changes to Table 6.......................................................................... 12 Changes to Table 7.......................................................................... 13 Changes to Table 9.......................................................................... 15 8/03—Revision 0: Initial Version Rev. B | Page 2 of 24 ADF4360-1 SPECIFICATIONS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source3 High Value Low Value RSET Range ICP 3-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VVCO AIDD4 DIDD4 IVCO4, 5 IRFOUT4 Low Power Sleep Mode4 RF OUTPUT CHARACTERISTICS5 VCO Output Frequency VCO Sensitivity Lock Time6 Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power Variation VCO Tuning Range B Version Unit Conditions/Comments 10/250 MHz min/max 0.7/AVDD 0 to AVDD 5.0 ±100 p-p min/max V max pF max µA max For f < 10 MHz, use a dc-coupled CMOS compatible square wave, slew rate > 21 V/µs. AC-coupled. CMOS compatible. 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.5 2 mA typ mA typ kΩ nA typ % typ % typ % typ 1.5 0.6 ±1 3.0 V min V max µA max pF max DVDD – 0.4 500 0.4 V min µA max V max 3.0/3.6 AVDD AVDD 10 2.5 24.0 3.5 – 11.0 7 V min/V max mA typ mA typ mA typ mA typ µA typ 2050/2450 57 400 6 15 −20 −35 −13/−6 ±3 1.25/2.5 MHz min/max MHz/V typ µs typ MHz/V typ kHz typ dBc typ dBc typ dBm typ dB typ V min/max With RSET = 4.7 kΩ. Rev. B | Page 3 of 24 1.25 V ≤ VCP ≤ 2.5 V. 1.25 V ≤ VCP ≤ 2.5 V. VCP = 2.0 V. CMOS output chosen. IOL = 500 µA. ICORE = 15 mA. RF output stage is programmable. ICORE = 15 mA. To within 10 Hz of final frequency. Into 2.00 VSWR load. Programmable in 3 dB steps. See Table 7. For tuned loads, see the Output Matching section. ADF4360-1 Parameter NOISE CHARACTERISTICS1, 5 VCO Phase-Noise Performance8 Synthesizer Phase-Noise Floor9 In-Band Phase Noise10, 11 RMS Integrated Phase Error12 Spurious Signals due to PFD Frequency11, 13 Level of Unlocked Signal with MTLD Enabled B Version Unit Conditions/Comments −110 −130 −141 −148 −172 −163 −147 −81 0.72 −70 −38 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Degrees typ dBc typ dBm typ @ 100 kHz offset from carrier. @ 1 MHz offset from carrier. @ 3 MHz offset from carrier. @ 10 MHz offset from carrier. @ 25 kHz PFD frequency. @ 200 kHz PFD frequency. @ 8 MHz PFD frequency. @ 1 kHz offset from carrier. 100 Hz to 100 kHz. 1 Operating temperature range is –40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance. 3 ICP is internally modified to maintain constant-loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32. 5 These characteristics are guaranteed for VCO Core Power = 15 mA. 6 Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 Using 50 Ω resistors to VVCO into a 50 Ω load. For tuned loads, see the Output Matching section. 8 The noise of the VCO is measured in open-loop conditions. 9 The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 10 The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 12500; Loop B/W = 10 kHz. 12 fREFIN = 10 MHz; fPFD = 1 MHz; N = 2400; Loop B/W = 25 kHz. 13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFOUT = 10 MHz @ 0 dBm. 2 Rev. B | Page 4 of 24 ADF4360-1 TIMING CHARACTERISTICS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width See the Power-Up section for the recommended power-up procedure for this device. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04414-002 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. B | Page 5 of 24 ADF4360-1 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance (Paddle Soldered) (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 150°C This device is a high performance RF integrated circuit with an ESD rating of