SSM2118TP

a FEATURES 117 dB Dynamic Range 0.006% Typical THD+N (@ 1 kHz, Unity Gain) 140 dB Gain Range No External Trimming Required Differential Inputs Complementary Gain Outputs Buffered Control Port I–V Converter On-Chip (SSM2018T) Differential Current Outputs (SSM2118T) Low External Parts Count Low Cost GENERAL DESCRIPTION Trimless Voltage Controlled Amplifiers SSM2018T/SSM2118T* FUNCTIONAL BLOCK DIAGRAMS VC SSM-2018T G VG +IN –IN GAIN CORE –I G 1–G V1–G –I 1–G The SSM2018T and SSM2118T represent continuing evolution of the Frey Operational Voltage Controlled Element (OVCE) topology that permits flexibility in the design of high performance volume control systems. Voltage (SSM2018T) and differential current (SSM2118T) output versions are offered, both laser-trimmed for gain core symmetry and offset. As a result, the SSM2018T is the first professional audio quality VCA to offer trimless operation. The SSM2118T is ideal for low noise summing in large VCA based systems. Due to careful gain core layout, the SSM2018T/SSM2118T combine the low noise of Class AB topologies with the low distortion of Class A circuits to offer an unprecedented level of sonic transparency. Additional features include differential inputs, a 140 dB gain range, and a high impedance control port. The SSM2018T provides an internal current-to-voltage converter; thus no external active components are required. The SSM2118T has fully differential current outputs that permit high noise-immunity summing of multiple channels. Both devices are offered in 16-pin plastic DIP and SOIC packages and guaranteed for operation over the extended industrial temperature range of –40°C to +85°C. VC SSM-2118T +I G G –I G +IN –IN 1–G V1–G GAIN CORE –I 1–G *Protected by U.S. Patent Nos. 4,471,320 and 4,560,947. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 SSM1018T/SSM2118T–SPECIFICATIONS [VS = ± 15 V, AV = 0 dB, RL = 100 kΩ, f = 1 kHz, 0 dBu = 0.775 V rms, simple VCA application circuit with 18 kΩ resistors, –VIN floating, and Class AB gain core bias (RB = 150 kΩ), –40°C < TA < +85°C, unless otherwise noted. Typical specifications apply at TA = +25°C.] Parameter AUDIO PERFORMANCE Noise Headroom Total Harmonic Distortion plus Noise 1 ELECTRICAL SPECIFICATIONS Conditions VIN = GND, 20 kHz Bandwidth Clip Point = 1% THD+N 2nd and 3rd Harmonics Only (+25°C to +85°C) AV = 0 dB, VIN = +10 dBu AV = +20 dB, VIN = –10 dBu AV = –20 dB, VIN = +10 dBu2 VCM = 0 V VCM = 0 V VCM = 0 V VCA Configuration VCP Configuration Min Typ –95 +22 0.006 0.013 0.013 0.25 1 10 4 ± 13 0.7 14 5 1.0 Max –93 Units dBu dBu % % % µA mV nA MΩ V MHz MHz V/µs mV V V kΩ µA MΩ mV/dB ppm/°C mV dB V mA dB 0.025 0.04 0.04 1 15 100 INPUT AMPLIFIER Bias Current Offset Voltage Offset Current Input Impedance Common-Mode Range Gain Bandwidth Slew Rate OUTPUT AMPLIFIER (SSM2018T) Offset Voltage Output Voltage Swing Minimum Load Resistance CONTROL PORT Bias Current Input Impedance Gain Constant Gain Constant Temperature Coefficient Control Feedthrough Maximum Attenuation POWER SUPPLIES Supply Voltage Range Supply Current Power Supply Rejection Ratio VIN = 0 V, VC = +4 V IOUT = 1.5 mA Positive Negative For Full Output Swing 15 +10 –10 +13 –14 9 0.36 1 1 –30 –3500 ±1 ±4 100 Device Powered in Socket > 60 sec 0 dB to –40 dB Gain Range VC = +4 V ±5 11 80 ± 18 15 NOTES 1 SSM2118T tested and characterized using OP275 as current-to-voltage converter, see figure next page. 2 Guaranteed by characterization data and testing at A V = 0 dB. Specifications subject to change without notice. –2– REV. A SSM2018T/SSM2118T ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C THERMAL CHARACTERISTICS PIN CONFIGURATIONS 16-Lead Plastic DIP 16-Lead Plastic DIP and SOL and SOL +I 1–G V+ –I G –I 1–G COMP 1 +IN –IN COMP 2 1 2 3 4 5 6 7 8 16 V1–G 15 BAL BAL V1–G +I1–G –I1–G COMP 1 +IN –IN COMP 2 1 2 3 4 5 6 7 8 16 V+ 15 14 –I G +I G 14 VG SSM2018T Thermal Resistance2 16-Pin Plastic DIP θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33°C/W 16-Pin SOIC θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27°C/W TRANSISTOR COUNT 13 TOP VIEW 12 (Not to Scale) 11 GND MODE VC SSM2118T 13 GND TOP VIEW 12 MODE (Not to Scale) 11 VC 10 V– 9 COMP 3 10 V– 9 COMP 3 ORDERING GUIDE Number of Transistors SSM2018T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SSM2118T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ESD RATINGS Model SSM2018TP SSM2018TS SSM2118TP SSM2118TS Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option* N-16 R-16 N-16 R-16 883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . . 500 V EIAJ Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 θJA is specified for worst-case conditions, i.e., θJA is specified for device in socket for P-DIP and device soldered in circuit board for SOIC package. 50pF 18k VOUT 1 V+ 2 3 4 1µF VIN+ VIN– 1µF 18k 47pF 18k 5 6 7 8 16 15 V– *N = Plastic DIP; R = SOL. FROM ADDITIONAL SSM2118Ts OPTIONAL TRIM GLOBAL SYMMETRY TRIM 50pF 500k 18k 47k 470k V+ 47k A2 50pF* VOUT 10k 18k 10k 1 V– 2 3 16 15 14 14 SSM2018T 13 12 11 10 9 150k V+ 3k 1k VCONTROL VIN+ VIN– 1µF 18k 47pF 1µF 18k 4 5 6 7 8 SSM2118T 13 12 11 V– 10 9 150k A1 A1, A2: OP275 3k VCONTROL 1µF 1µF 1k *FOR MORE THAN 2 SSM2118Ts SSM2018T Typical Application Circuit SSM2118T Typical Application Circuit CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2018T/SSM2118T features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A –3– SSM2018T/SSM2118T–Typical Characteristics 0.1 TA = +25°C VS = ±15V RF = 18kΩ 1 TA = +25°C VS = ±15V RF = 18kΩ AV = +20dB 0.1 THD + N – % THD + N – % 0.010 AV = –20dB 0.010 AV = 0dB 0.001 20 100 1k FREQUENCY – Hz 10k 20k 0.001 10m 0.1 AMPLITUDE – VRMS 1 2 Figure 1. SSM2018T THD + N Frequency (80 kHz Low-Pass Filter, for AV = 0 dB, VIN = 3 V rms; for AV = +20 dB, VIN = 0.3 V rms; for AV = –20 dB, VIN = 3 V rms) Figure 4. SSM2018T THD + N vs. Amplitude (Gain = +20 dB, fIN =1 kHz, 80 kHz Low-Pass Filter) 100 90 80 70 60 TA = +25°C AV = 0dB 300 UNITS VIN = 10dBu VS = ±15V 1.0 TA = +25°C VS = ±15V RF = 18kΩ 0.1 THD + N – % UNITS 50 40 30 20 10 0 0.000 0.005 0.010 0.015 0.020 0.025 0.01 0.001 –60 –40 DISTORTION – % –20 0 GAIN – dB 20 40 Figure 2. SSM2018T Distortion Distribution Figure 5. SSM2018T THD + N vs. Gain (fIN = 1 kHz; for –60 dB ≤ AV ≤ –20 dB, VIN = 10 V rms; for 0 dB ≤ AV ≤ +20 dB, VIN = 1 V rms) 1 TA = +25°C RF = 18kΩ VS = ±15V 0.1 TA = +25°C RF = 18kΩ 0.1 THD + N – % THD + N – % 0.01 0.010 0.001 0.1 1 AMPLITUDE – VRMS 10 20 0.001 0 ±3 ±6 ±9 ±12 ±15 ±18 SUPPLY VOLTAGE – Volts Figure 3. SSM2018T THD + N vs. Amplitude (Gain = 0 dB, fIN = 1 kHz, 80 kHz Low-Pass Filter) Figure 6. SSM2018T THD + N vs. Supply Voltage (AV = 0 dB, VIN = 1 V rms, fIN = 1 kHz, 80 kHz Low-Pass Filter) – 4– REV. A SSM2018T/SSM2118T 500 MAXIMUM OUTPUT SWING – VPEAK ±15 TA = +25°C VS = ±15V 400 ±12 RF = 18kΩ TA = +25°C VS = ±15V NOISE DENSITY – nV/√ Hz 300 ±9 ±6 200 ±3 100 0 10 100 1k FREQUENCY – Hz 10k 100k 0 100 1k 10k 100k LOAD RESISTANCE – Ω Figure 7. SSM2018T Noise Density vs. Frequency Figure 10. SSM2018T Maximum Output Swing vs. Load Resistance, (THD = 1 % max) 100 RF = 18kΩ TA = +25°C ±20 90 80 OUTPUT OFFSET – mV RL = ∞Ω OUTPUT VOLTAGE SWING – VPEAK TA = +25°C VS = ±15V 70 60 50 40 30 20 10 ±15 RL = 10kΩ ±10 ±5 0 0 ±5 ±10 ±15 ±20 0 –80 –60 –40 –20 GAIN – dB 0 20 40 SUPPLY VOLTAGE – Volts Figure 8. SSM2018T Maximum Output Swing vs. Supply Voltage (THD = 1% max) Figure 11. SSM2018T Output Offset vs. Gain MAXIMUM OUTPUT SWING – VPEAK ±15 RF = 18kΩ TA = +25°C VS = ±15V +10 TA = +25°C VS = ±15V +5 RL = ∞ GAIN – dB RL = 10k ±9 0 GAIN PHASE –5 0 –45 ±6 ±3 –10 –90 0 1k 10k FREQUENCY – Hz 100k –15 100 –135 1k 10k FREQUENCY – Hz 100k 1M Figure 9. SSM2018T Maximum Output Swing vs. Frequency (THD = 1 % max) Figure 12. SSM2018T Gain/Phase vs. Frequency REV. A –5– PHASE – Degrees ±12 SSM2018T/SSM2118T–Typical Characteristics 60 40 20 TA = +25°C VS = ±15V 1 TA = +25°C VS = ±15V 0.1 0 –20 –40 –60 –80 100 THD + N – % GAIN – dB 0.010 1k 10k 100k FREQUENCY – Hz 1M 10M 0.001 0.1 1 AMPLITUDE – VRMS 10 20 Figure 13. SSM2018T Gain vs. Frequency Figure 16. SSM2118T THD + N vs. Amplitude (Gain = 0 dB, fIN = 1 kHz, 80 kHz Low-Pass Filter) 0.1 TA = +25°C RF = 18kΩ AV = +20dB THD + N – % 1 TA = +25°C VS = ±15V AV = –20dB 0.1 0.010 AV = 0dB THD + N – % 0.010 0.001 20 100 1k FREQUENCY – Hz 10k 20k 0.001 10m 0.1 AMPLITUDE – VRMS 1 2 Figure 14. SSM2118T THD + N Frequency (80 kHz Low-Pass Filter, for AV = 0 dB, VIN = 1 V rms; for AV = +20 dB, VIN = 0.1 V rms; for AV = –20 dB, VIN = 10 V rms) Figure 17. SSM2118T THD + N vs. Amplitude (Gain = +20 dB, fIN = 1 kHz, 80 kHz Low-Pass Filter) 100 90 80 70 60 UNITS 1.0 TA = +25°C AV = 0dB 300 UNITS VIN = 10dBu VS = ±15V THD + N – % TA = +25°C VS = ±15V 0.1 50 40 30 20 10 0 0.000 0.005 0.010 0.015 0.020 0.025 0.01 0.001 –60 –40 –20 GAIN – dB 0 +20 +40 DISTORTION – % Figure 15. SSM2118T Distortion Distribution Figure 18. SSM2118T THD + N vs. Gain (fIN = 1 kHz; for –60 dB ≤ AV ≤ –20 dB, VIN = 10 V rms; for 0 dB ≤ AV ≤ +20 dB, VIN = 1 V rms) –6– REV. A SSM2018T/SSM2118T 0.1 TA = +25°C MAXIMUM OUTPUT SWING – VPEAK ±15 TA = +25°C VS = ±15V ±12 THD + N – % 0.01 ±9 ±6 ±3 0.001 0 ±3 ±6 ±9 ±12 ±15 ±18 0 1k SUPPLY VOLTAGE – Volts 10k FREQUENCY – Hz 100k Figure 19. SSM2118T THD + N vs. Supply Voltage (AV = 0 dB, VIN = 1 V rms, fIN = 1 kHz, 80 kHz Low-Pass Filter) Figure 22. SSM2118T Maximum Output Swing vs. Frequency (THD = 1 % max) 500 TA = +25°C VS = ±15V OUTPUT OFFSET CURRENT – µA 10 9 8 7 6 5 4 3 2 1 TA = +25°C VS = ±15V 400 NOISE DENSITY – nV/√ Hz 300 200 100 0 10 100 1k FREQUENCY – Hz 10k 100k 0 –80 –60 –40 –20 GAIN – dB 0 20 40 Figure 20. SSM2118T Noise Density vs. Frequency Figure 23. SSM2118T Output Offset Current vs. Gain ±20 TA = +25°C +10 TA = +25°C VS = ±15V +5 RL = ∞Ω OUTPUT VOLTAGE SWING – VPEAK ±20 GAIN – dB ±15 0 GAIN –5 PHASE 0 PHASE – Degrees ±10 –45 ±5 –10 –90 0 0 ±5 ±10 ±15 ±20 –15 100 –135 1k 10k FREQUENCY – Hz 100k 1M SUPPLY VOLTAGE – Volts Figure 21. SSM2118T Maximum Output Swing vs. Supply Voltage (THD = 1% max) Figure 24. SSM2118T Gain/Phase vs. Frequency REV. A –7– SSM2018T/SSM2118T 60 TA = +25°C VS = ±1.5V OP275 AS I/V CONV. 100 90 80 70 60 TA = +25°C 0V < VC < 1.2V FREQ = 0Hz 300 UNITS 40 20 GAIN – dB UNITS 0 –20 –40 –60 –80 100 50 40 30 20 10 0 –3.0 –2.0 –1.0 1.0 0 CONTROL FEEDTHROUGH – mV 2.0 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 25. SSM2118T Gain vs. Frequency Figure 28. SSM2018T Control Feedthrough Distribution 0.06 TA = +25°C VS = ±15V CONTROL FEEDTHROUGH – dB 0 0.05 VS = ±15V TA = +25°C VC = 100mVRMS –20 DISTORTION – % 0.04 0.03 VIN = 10dBu AV = –20dB AND VIN = –10dBu AV = 20dB –40 0.02 VIN = 10dBu AV = 0dB –60 0.01 –80 0 –40 –20 0 20 40 60 80 100 TEMPERATURE – °C –100 100 1k 10k FREQUENCY – Hz 100k Figure 26. SSM2018T and SSM2118T Distortion vs. Temperature Figure 29. SSM2018T and SSM2118T Control Feedthrough vs. Frequency –60 TA = +25°C VS = ±15V CONTROL FEEDTHROUGH – mV 3 VS = ±15V 0V < VC < 1.2V FREQ = 0Hz –70 2 OUTPUT NOISE – dBu –80 1 0 –90 –1 –100 –2 –110 –60 –40 –20 0 GAIN – dB 20 40 –3 –40 –20 0 20 40 60 TEMPERATURE – °C 80 100 Figure 27. SSM2018T and SSM2118T Output Noise vs. Gain (VIN = GND, 20 kHz Bandwidth) Figure 30. SSM2018T and SSM2118T Control Feedthrough vs. Temperature –8– REV. A SSM2018T/SSM2118T –20 VS = ±15V –20 0 VS = ±15V TA = +25°C GAIN CONSTANT – mV/dB –25 –30 CMRR – dB –40 –60 –35 –80 –40 –40 –20 0 20 40 TEMPERATURE – °C 60 80 100 –100 10 100 1k FREQUENCY – Hz 10k 100k Figure 31. SSM2018T and SSM2118T Gain Constant vs. Temperature Figure 34. SSM2018T and SSM2118T CMRR vs. Frequency –28 TA = +25°C VS = ±15V –29 15.0 TA = +25°C 12.5 + SLEW RATE GAIN CONSTANT – mV/dB SLEW RATE – V/µs 10.0 –30 7.5 –31 5.0 – SLEW RATE –32 2.5 –33 –80 0 –60 –40 –20 0 20 40 60 0 ±5 ±10 ±15 SUPPLY VOLTAGE – Volts GAIN – dB Figure 32. SSM2018T and SSM2118T Gain Constant Linearity vs. Gain Figure 35. SSM2018T and SSM2118T Slew Rate vs. Supply Voltage 0.1 0 TA = +25°C VS = ±15V AV = 0dB VIN = 100VRMS VS = ±15V TA = +25°C –20 0.0 GAIN – dB –0.1 PSRR – dB –40 + PSRR –0.2 –60 – PSRR –0.3 –80 –0.4 100 –100 10 1k 10k FREQUENCY – Hz 100k 100 1k FREQUENCY – Hz 10k 100k Figure 33. SSM2018T and SSM2118T Gain Flatness vs. Frequency Figure 36. SSM2018T and SSM2118T PSRR vs. Frequency REV. A –9– SSM2018T/SSM2118T APPLICATIONS The SSM2018T is a trimless Voltage Controlled Amplifier (VCA) for volume control in audio systems. The SSM2018T is identical to the original SSM2018 in functionality and pinout; however, it is the first professional quality audio VCA in the marketplace that does not require an external trimming potentiometer to minimize distortion. Instead, the SSM2018T is laser trimmed before it is packaged to ensure the specified THD and control feedthrough performance. This has a significant savings in not only the cost of external trimming potentiometers, but also the manufacturing cost of performing the trimming during production. The SSM2118T is identical to the SSM2018T except that differential current outputs are provided as opposed to a voltage output. This output configuration is ideal for bus summing applications where multiple audio signals are summed together. These signals often require long lead lengths or cable runs to reach the summing stage. Transmitting the signals in a differential current mode minimizes the chance for noise pickup and for line impedances to upset the balance of the system. The SSM2118T is also factory trimmed to minimize distortion and control feedthrough. Thus, no individual trim is required for each part. One global trim at the summing amplifier stage may be necessary to properly balance the resistors in this stage, as explained later. Basic VCA Configuration to run it in the noninverting single-ended mode. If either input is unused, the associated 18 kΩ resistor and coupling capacitor should be removed to prevent any additional noise. The common-mode rejection in balanced mode is typically 55 dB up to 1 kHz, decreasing at higher frequencies as shown in Figure 34. To ensure good CMRR in the balanced configuration, the input resistors must be balanced. For example, a 1% mismatch results in a CMRR of 40 dB. To achieve 55 dB, these resistors should have an absolute tolerance match of 0.1%. The output of the basic VCA is taken from Pin 14, which is the output of an internal amplifier. Notice that the second voltage output (Pin 16) is connected to the negative supply. This is normal and actually disables that output amplifier ensuring that it will not oscillate and cause interference problems. Shorting the output to the negative supply does not cause the supply current to increase. This amplifier is only used in the “OVCE” application explained later. The control port follows a 30 mV/dB control law. The application circuit shows a 3 kΩ and 1 kΩ resistor divider from a control voltage. The choice of these resistors is arbitrary and could be any values to properly scale the control voltage. In fact, these resistors could be omitted if the control voltage is already properly scaled. The 1 µF capacitor is in place to provide some filtering of the control signal. Although the control feedthrough is trimmed at the factory, the feedthrough increases with frequency (Figure 29). Thus, high frequency noise can feedthrough and add to the noise of the VCA. Filtering the control signal helps minimize this source of noise. Theory of Operation of the SSM2018T The primary application circuit for the SSM2018T is the basic VCA configuration, which is shown in Figure 37. This configuration uses differential current feedback to realize the VCA. A complete description of the internal circuitry of the VCA and this configuration is given in the Theory of Operation section below. The SSM2018T and SSM2118T are trimmed at the factory for operation in the basic VCA configuration with class AB biasing. Thus, for optimal distortion and control feedthrough performance, the same configuration and biasing should be used. All of the graphs for the SSM2018T in the data sheet have been measured using the circuit of Figure 37. 50pF 18k VOUT 1 V+ 2 3 4 1µF 18k VIN+ VIN– 1µF 18k 47pF 5 6 7 8 16 15 14 V– The SSM2018T has the same internal circuitry as the original SSM2018. The detailed diagram in Figure 38 shows the main components of the VCA. The essence of the SSM2018T is the gain core, which is comprised of two differential pairs (Q1–Q4). When the control voltage, VC, is adjusted, current through the gain core is steered to one side or the other of the two differential pairs. The tail current for these differential pairs is set by the mode bias of the VCA (Class A or AB), which is labeled as IM in the diagram. IM is then modulated by a current proportional to the input voltage, labeled IS. For a positive input voltage, more current is steered (by the “Splitter”) to the left differential pair, and the opposite is true for a negative input. To understand how the gain control works, a simple example is best. Take the case of a positive control voltage on Pin 11. Notice that the bases of Q2 and Q3 are connected to ground via a 200 Ω resistor. A positive control voltage produces a positive voltage on the bases of Q1 and Q4. Concentrating on the left most differential pair, this raises the base voltage of Q1 above that of Q2. Thus, more of the tail current is steered through Q1 than through Q2. The current from the collector of Q2 flows through the external 18 kΩ feedback resistor around amplifier A3. When this current is reduced, the output voltage is also reduced. Thus, a positive control voltage results in an attenuation of the input signal, which explains why the gain constant is negative. The collector currents of Q2 and Q3 produce the output voltage. The output of Q3 is mirrored by amplifier A1 to add to the overall output voltage. On the other hand, the collector currents of Q1 and Q4 are used for feedback to the differential inputs. Because Pins 6 and 4 are shorted together, any input voltage produces an input current which flows into Pin 4. The REV. A SSM2018T 13 12 11 10 9 RB 150k V+ 3k 1k VCONTROL 1µF Figure 37. SSM2018T Basic VCA Application Circuit In the simple VCA configuration, the SSM2018T inputs are at a virtual ground. Thus, 18 kΩ resistors are required to convert the input voltages to input currents. The schematic also shows ac coupling capacitors. These are inserted to minimize dc offsets generated by bias current through the resistors. Without the capacitors, the dc offset due to the input bias current is typically 5 mV. The input stage has the flexibility to run either inverting, noninverting, or balanced. The most common configuration is –10– SSM2018T/SSM2118T V+ COMP 2 8 COMP 1 VG 5 14 –I G 3 +I 1 1-G 2 15 BAL COMPENSATION NETWORK A3 A1 A2 A4 A4 4 –I 1-G 16 V 1-G –IN 7 1–G Q1 G Q2 G Q3 1–G Q4 1.8k GAIN CORE 11 V C +IN 6 Im+(Is ) 2 200 Im–( Is) 2 200 13 GND SPLITTER VREF 12 MODE V– 10 9 COMP 3 Im Figure 38. SSM2018T Detailed Functional Diagram same is true for the inverting input, which is connected to Pin 1. The overall feedback ensures that the current flowing through the input resistors is balanced by the collector currents in Q1 and Q4. Basic VCA Configuration for the SSM2118T The SSM2118T behaves very much in the same way as the SSM2018T except that it has differential current outputs instead of a voltage output. The basic VCA configuration is shown in Figure 39. A dual output amplifier is needed to replace the internal amplifiers in the SSM2018T. However, multiple SSM2118Ts can share the output amplifiers. The op amps are configured so that the SSM2118T’s output current is flowing into a virtual ground. This same virtual ground is presented to all the VCAs, allowing their currents to be summed without interaction. FROM ADDITIONAL SSM2118Ts GLOBAL SYMMETRY TRIM 50pF 500k 18k 47k V+ 1 V– 2 3 4 1µF 18k VIN+ VIN– 1µF 18k 47pF 5 6 7 8 16 15 14 10k 150k 50pF * 10k 18k 470k A global symmetry trim may be necessary, but since it is at the output amplifiers, only one trim is needed for any number of SSM2118Ts connected to the summing bus. This trim balances the resistors around the two amplifiers. If precision, matched resistors are used, the trim can be removed. However, to achieve 0.006% distortion, these resistors need to be matched to approximately 0.01%. If the choice is made to perform the trim, then one of two methods may be used. The first method minimizes the distortion of an audio signal with the SSM2118T in the circuit. To perform the trim, a 0 dBu, 1 kHz sine wave is applied to one of the VCAs, and the output distortion is monitored. As the symmetry trim is adjusted, the output distortion will vary. The optimal adjustment produces the lowest distortion over the entire trim range. The second method is to insert a common mode signal by connecting two 47 kΩ resistors (matched to 0.01%) to the inverting inputs of each amplifier, as shown in the Figure 39. The signal is typically a 0 dBu, 1 kHz sine wave, although other signals can be used. The output is monitored with an oscilloscope, and the potentiometer is adjusted to achieve a minimum output signal. The SSM2118T has the exact same input and gain core construction as the SSM2018T. Thus, any discussion of these portions of the SSM2018T apply equally to the SSM2118T. The main difference, which is apparent by comparing Figure 40 to Figure 38, is the removal of two output amplifiers, A1 and A3. Instead, the output currents come directly from the collectors of Q2 and Q3. Notice that the two external amplifiers in Figure 39 are configured the same as the internal amplifiers in the SSM2018T. Two important characteristics of these current outputs must be considered: the output compliance and the effects of capacitive loading. Normally, the outputs are connected to a virtual ground node at the summing stage, which is biased at ground. This bias point can be altered somewhat. The part maintains good distortion performance for an output compliance from OPTIONAL TRIM 47k A2 VOUT SSM2118T 13 12 11 V– 10 9 A1 A1, A2: OP275 3k VCONTROL 1µF 1k *FOR MORE THAN 2 SSM2118Ts Figure 39. SSM2118T Typical Bus Summing Application REV. A –11– SSM2018T/SSM2118T COMP 2 8 V+ 16 COMPENSATION NETWORK 4 A2 A4 A4 2 COMP 1 5 –I G 15 +IG 14 +I 1–G 3 1 BAL –I1–G V1–G –IN 7 1–G Q1 G Q2 G Q3 1–G Q4 1.8k GAIN CORE 11 VC +IN 6 Im+(Is ) 2 200 Im–( Is ) 2 200 13 GND SPLITTER VREF 12 MODE V– 10 9 COMP 3 Im Figure 40. SSM2118T Detailed Functional Diagram –0.1 V to +6.0 V. The negative compliance is much smaller because the gain core transistors (Q1 and Q3) begin to saturate when the collector potential is brought below their base potential. These outputs have high immunity to capacitive loads. In fact, the load on either or both outputs can be as large as 10 nF with no change in the distortion performance. For values above 10 nF, the distortion does start to increase. For example, a 100 nF load causes the distortion to increase from 0.006% to 0.02% at 1 kHz. The noise performance of a single SSM2118T with an OP275 output amplifier is shown in Figure 20. When multiple SSM2118T parts are operated in parallel, the noise does increase by a factor equal to the square root of the number of parts paralleled. For example, if five parts are in parallel, the total output noise is 100 nV√(Hz) × √5 = 220 nV/√Hz. Compensating the SSM2018T and SSM2118T employ a patented adaptive compensation circuit. The compensation capacitor is “Miller” connected between the base and collector of an internal transistor. By changing the gain of this transistor via the control voltage, the compensation is changed. Increasing the compensation capacitor causes the frequency response and slew rate to decrease, which will tend to cause high frequency distortion to increase. For the basic VCA circuit, 47 pF was chosen as the optimal value. The OVCE circuit described later uses a 220 pF capacitor. The reason for the increase is to compensate for the extra phase shift from the additional output amplifier used in the OVCE configuration. The compensation capacitor can be adjusted over a practical range from 47 pF to 220 pF, if desired. Below 47 pF, the parts may oscillate, and above 220 pF the frequency response is significantly degraded. Control Section Both parts employ the same compensation network. This network uses an adaptive compensation scheme that adjusts the optimum compensation level for a given gain. The control voltage not only adjusts the gain core steering, it also adjusts the compensation. The SSM2018T and SSM2118T have three compensation pins: COMP1, COMP2, and COMP3. COMP3 is normally left open. Grounding this pin actually defeats the adaptive compensation circuitry, giving the VCA a fixed compensation point. The only time that this is desirable is when the VCA has fixed feedback, such as the Voltage Controlled Panner (VCP) circuit shown later in the data sheet. Thus, for the Basic VCA circuit or the OVCE circuit, COMP3 should be left open. A compensation capacitor does need to be added between COMP1 and COMP2. Because the VCA operates over such a wide gain range, ideally the compensation should be optimized for each gain. When the VCA is in high attenuation, there is very little “loop gain,” and the part needs to have high compensation. On the other hand, at high gain, the same compensation capacitor would overcompensate the part and roll off the high frequency performance. Thus, the SSM2018T and SSM2118T As mentioned before, the control voltage on Pin 11 steers the current through the gain core transistors to set the gain. The output gain formula is as follows: V OUT = V IN × e(– aV C ) The exponential term arises from the standard Ebers-Moll equation describing the relationship of a transistor’s collector current as a function of the base-emitter voltage: I C = I S × e(V /V ). The factor “a” is a function of not only VT but also the scaling due to the resistor divider of the 200 Ω and 1.8 kΩ resistors shown in Figures 38 and 40. The resulting expression for “a” is as follows: a = 1/(10 × VT) which is approximately equal to four at room temperature. Substituting a = 4 in the above equation results in a –28.8 mV/dB control law at room temperature. BE T The –28.8 mV/dB number is slightly different from the data sheet specification of –30 mV/dB. The difference arises from the temperature dependency of the control law. The term VT is known as the thermal voltage, and it has a direct dependency –12– REV. A SSM2018T/SSM2118T on temperature: VT = kT/q (k = Boltzmann’s constant = 1.38E-23, q = electron charge = 1.6E-19, and T = absolute temperature in Kelvin). This temperature dependency leads to the –3500 ppm/°C drift of the control law. It also means that the control law changes as the part warms up. Thus, our specification for the control law states that the part has been powered up for 60 seconds. When the part is initially turned on, the temperature of the die is still at the ambient temperature (25°C for example), but the power dissipation causes the die to warm up. With ± 15 V supplies and a supply current of 11 mA, 330 mW is dissipated. This number is multiplied by θJA to determine the rise in the die’s temperature. In this case, the die increases from 25°C to approximately 50°C. A 25°C temperature change causes a 8.25% increase in the gain constant, resulting in a gain constant of 30 mV/dB. The graph in Figure 31 shows how the gain constant varies over the full temperature range. Proper Operating Mode for the SSM2018T and SSM2118T swing versus load resistance shows (Figure 10), to maintain less than 1% distortion, the output current should be limited to approximately ± 1.3 mA. If higher current drive is required, then the output should be buffered with a high quality op amp such as the OP176 or AD797. The internal amplifiers are compensated for unity gain stability and are capable of driving a capacitive load up to 4700 pF. Larger capacitive loads should be isolated from the output of the SSM2018T by the use of a 50 Ω series resistor. Upgrading SSM2018 Sockets The SSM2018T easily replaces the SSM2018 in the basic VCA configuration. The parts are pin for pin compatible allowing direct replacement. At the same time, the trimming potentiometers for symmetry and offset should be removed, as shown in Figure 41. Upgrading to the SSM2018T immediately saves the expense of the potentiometers and the time in production of trimming for minimum distortion and control feedthrough. V+ REMOVE FOR SSM2018T Both parts have the flexibility of operating in either Class A or Class AB. This is accomplished by adjusting the amount of current flowing in the gain core (IM in Figure 38). The traditional trade-off between the two classes is that Class A tends to have lower THD but higher noise than Class AB. However, by utilizing well matched gain core transistors, distortion compensation circuitry, and laser trimming, the SSM2018T and SSM2118T have excellent THD performance in Class AB. Thus, the parts offer the best of both worlds in having the low noise of Class AB with low THD. Because the parts operate optimally in Class AB, the distortion trim is performed for this class. To guarantee conformance to the data sheet THD specifications, both the SSM2018T and SSM2118T must be operated in Class AB. This does not mean that the parts cannot be operated in Class A, but the optimal THD trim point is different for the two classes. Using Class A operation results in a shift of THD performance from a typical value of 0.006% to 0.05% without trim. An external potentiometer could be added to change the trim back to its optimal point as shown in the OVCE application circuit, but this adds the expense and time in adjusting a potentiometer. The class of operation is set by selecting the proper value for RB shown in Figure 37. RB determines the current flowing into the MODE input (Pin 12). For class AB operation with ± 15 V supplies, RB should be 150 kΩ. This results in a current of 95 µA. For other supply voltages, adjust the value of RB such that current remains at 95 µA. This current follows the formula: I MODE = (V CC – 0.7 V ) RB OFFSET TRIM 10MΩ 100kΩ V– SYMMETRY TRIM 470kΩ 500kΩ 50pF 18kΩ VOUT 16 15 14 13 1 V+ 2 3 4 SSM2018T 5 12 11 RB V+ 3kΩ VCONTROL VIN+ VIN– 1µF 18kΩ 6 7 1µF 10 9 1µF 18kΩ 8 1kΩ NC V– 47pF RB: 150kΩ FOR CLASS AB NC = NO CONNECT Figure 41. Upgrading SSM2018 Sockets If the SSM2018 is used in the OVCE or VCP configuration, the SSM2018T can still directly replace it. However, the potentiometers cannot necessarily be removed, as explained in the OVCE and VCP sections. As explained above, the gain constant has a 3500 ppm/°C temperature drift due to the inherent nature of the control port. Over the full temperature range of –40°C to +85°C, the drift causes the gain to change by 7 dB if the part is in a gain of ± 20 dB. If the application requires that the gain constant be the same over a wide temperature range, then external temperature compensation should be employed. The simplest form of compensation is a temperature compensating resistor (TCR), such as the PT146 from Precision Resistor Co. These elements are different from a standard thermistor in that they are linear over temperature to better match the linear drift of the gain constant. Temperature Compensation of the Gain Constant The factor of 0.7 V arises from the fact that the dc bias on Pin 12 is a diode drop above ground. Output Drive The SSM2018T is buffered by an internal op amp to provide a low impedance output. This output is capable of driving to within 1.2 V of either rail at 1% distortion for a 100 kΩ load. (Note: This 100 kΩ load is in parallel with the feedback resistor of 18 kΩ, so the effective load is 15.3 kΩ.) For better than 0.01% distortion, the output should remain about 3.5 V away from either rail as shown in Figure 3. As the graph of output REV. A –13– SSM2018T/SSM2118T 1µF 2kΩ 1kΩ* 3500ppm/°C 1kΩ* 3500ppm/°C VC (PIN 11) SSM2018T OR SSM2118T *PRECISION RESISTOR CO. 10601 75TH ST. NORTH LARGO, FL 34647 (813) 541-5771 CONTROL VOLTAGE such that full scale produces 80 dB of attenuation. The resistor divider can be adjusted to provide other attenuation ranges. If a parallel interface is needed, then the DAC8562 may be used, or for a dual DAC, the AD8582. 50pF 18kΩ VOUT NC +15V 0.1µF 1 2 3 4 16 15 14 13 Figure 42. Two TCRs Compensate for Temperature Drift of Gain Constant 50pF NC 18kΩ CONTROL VOLTAGE R1 10kΩ R3 10kΩ +15V OP176 –15V R5 9kΩ R2 10kΩ R4 1kΩ VC (PIN 11) SSM2018T OR SSM2118T 1kΩ* 3500ppm/°C 5 6 SSM2018T 150kΩ +15V 12 11 10 9 VIN NC 47pF 7 8 –15V NC 0.1µF +5V 0.1µF 1 CS CLR LD 2 6 5 3 4 7 NC = NO CONNECT R6 825Ω 8 R7 1kΩ CCON 1µF DAC8512 0V ≤ VC ≤ +2.24V Figure 43. Current Source Allows Temperature Compensation with One TCR SCLK SDI One of the resistors in the divider to the control port can be substituted with an appropriately chosen TCR to compensate the SSM2018T or the SSM2118T as shown in Figure 42. Because the resistor divider effectively cuts the temperature coefficient in half, two TCRs must be used. The combined drift of the two is 7000 ppm/°C, given an effective drift for to the control voltage of –3500 ppm/°C. Of course, a single TCR with the appropriate coefficient can be used. The 3500 ppm parts were chosen because they are a standard item and do not need to be special ordered. In many applications, an op amp is used to drive the control voltage. If this is the case, it may be more economical to use the op amp and a single TCR for temperature compensation. The op amp is configured as a Howland current source as shown in Figure 43. The current then flows through a single TCR to create the control voltage. Because the resistor divider is not present, the temp coefficient is equivalent to the TCR’s coefficient. Using this technique, the drift was reduced from –3500 ppm/°C to –150 ppm/°C, which results in a total compensated gain shift of 0.4 dB over the full temperature range at a gain of ± 20 dB. Digital Control of the Gain Figure 44. 12-Bit DAC Controls the VCA Gain Supply Considerations and Single Supply Operation The SSM2018T and SSM2118T have a wide operating supply range. Many of the graphs in this data sheet show the performance of the part from ± 5 V to ± 18 V. These graphs offer typical performance specifications and are a good indication of the parts capabilities. The minimum operating supply voltage is ± 4.5 V. Below this voltage, the parts are inoperable. Thus, to account for supply variations, the recommended minimum supply is ± 5 V. The circuits in the data sheet do not show supply decoupling for simplicity; however, to ensure best performance, each supply pin should be decoupled with a 0.1 µF ceramic (or other low resistance and inductance type) capacitor as close to the package as possible. This minimizes the chance of supply noise feeding through the part and causing excessive noise in the audio frequency range. The SSM2018T and SSM2118T can be operated in single supply mode as long as the circuit is properly biased. Figure 45 shows the proper configuration, which includes an amplifier to create a false ground node midway between the supplies. A high quality, wide bandwidth audio amplifier such as the OP176 or AD797 should be used to ensure a very low impedance ground over the full audio frequency range. The minimum operating supply for the SSM2018 is ± 5 V, which gives a minimum single supply of +10 V and ground. The performance of the circuit with +10 V is identical to graphs that show operation of the SSM2018T with ± 5 V supplies. A common method of controlling the gain of a VCA is to use a digital-to-analog converter to set the control voltage. Figure 44 shows a 12-bit DAC, the DAC8512, controlling the SSM2018T (or SSM2118T). The DAC8512 is a complete 12-bit converter in an 8-pin package. It includes an on board reference and a output amplifier to produce an output voltage from 0 V to +4.095 V, which is 1 mV/bit. Since the voltage is always positive, this circuit only provides attenuation. The resistor divider on the output of the DAC8512 is set to scale the output voltage –14– REV. A SSM2018T/SSM2118T 50pF 18k VOUT 1 V+ 2 3 4 1µF VIN+ VIN– 1µF 18k 47pF VIN Next the control feedthrough trim is done as follows: 1. Ground the input signal port and apply a 60 Hz sine wave to the control port. The sine wave should have its high and low peaks correspond to the highest gain to be used in the application and 30 dB of attenuation, respectively. For example, a range of +20 dB gain to 30 dB attenuation requires that the sine wave amplitude ranges between –560 mV and +840 mV on Pin 11. 3k 1k VC VG 16 15 14 SSM2018T 13 12 11 10 9 RB V+ VCONTROL 18k 5 6 7 8 2. Adjust the control feedthrough potentiometer to null the signal seen at the output. 1µF V+ 100k V+ OP176 V1–G 100k 10µF Figure 46. OVCE Follower/VCA Connection Figure 45. Single Supply Operation of SSM2018T Operational Voltage Controlled Element V+ CONTROL FEEDTHROUGH TRIM 100kΩ 10MΩ 500kΩ SYMMETRY TRIM 50pF 18kΩ VG 50pF 18kΩ V1–G 470kΩ The SSM2018T has considerable flexibility beyond the basic VCA circuit utilized throughout this data sheet. The name “Operational Voltage Controlled Element” comes from the fact that the part behaves much like an operational amplifier with a second voltage controlled output. The symbol for the OVCE connected as a unity gain follower/VCA is shown in Figure 46. The voltage output labeled V1–G is fed back to the inverting input just as for an op amp’s feedback. The VG output is amplified or attenuated depending upon the control voltage. Because the OVCE works just like an op amp, the feedback could just as easily have included resistors to add gain, or a filter network to add frequency shaping. The full circuit for the OVCE is shown in Figure 47. Notice that the amplifier whose output (Pin 16) was originally connected to VMINUS is now the output for feedback. As mentioned before, because the SSM2018T is trimmed for the basic VCA configuration, potentiometers are needed for the OVCE configuration to ensure the best THD and control feedthrough performance. If a symmetry trim is to be performed, it should precede the control feedthrough trim and be done as follows: 1. Apply a 1 kHz sine wave of +10 dBu to the input, with the control voltage set for unity gain. 2. Adjust the symmetry trim potentiometer to minimize distortion of the output signal. V– 1 V+ 16 15 14 2 3 4 5 6 SSM2018T 13 RB 12 11 1µF V+ 3kΩ VCONTROL 1kΩ INPUTS 7 8 220pF 10 9 V– NC RB: 30kΩ FOR CLASS A 150kΩ FOR CLASS AB NC = NO CONNECT Figure 47. OVCE Application Circuit REV. A –15– SSM2018T/SSM2118T Voltage Controlled Panner OUTLINE DIMENSIONS Dimensions shown in inches and (mm). An interesting circuit that is built with the OVCE building block is a voltage controlled panner. Figure 48 shows the feedback connection for the circuit. Notice that the average of both outputs is fed back to the input. Thus, the average must be equal to the input voltage. When the control voltage is set for gain at VG, this causes V1-G to attenuate (to keep the average the same). On the other hand, when VG is attenuated, V1-G is amplified. The result is that the control voltage causes the input to “pan” from one output to the other. The following expressions show how this circuit works mathematically: 16-Pin Plastic DIP (N-16) Package 16 PIN 1 1 0.840 (21.33) 0.745 (18.93) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 8 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 9 0.280 (7.11) 0.240 (6.10) V G = 2 K × V IN and V I –G = 2 (1 – K ) × V IN where K varies between 0 and 1 as the control voltage is changed from full attenuation to full gain respectively. When VC = 0, then K = 0.5 and VG = V1-G = VIN. Again, trimming is required for best performance. Pin 9 should be grounded. This is possible because the feedback is constant and the adaptive network is not needed. The VCP is the only application shown in this data sheet where Pin 9 is grounded. VC VIN VG 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.100 (2.54) BSC 16-Pin SOIC (R-16) Package 16 9 0.2992 (7.60) 0.2914 (7.40) V1–G 18kΩ 18kΩ PIN 1 1 8 0.4193 (10.65) 0.3937 (10.00) 0.4133 (10.50) 0.3977 (10.00) 0.1043 (2.65) 0.0926 (2.35) Figure 48. Basic VCP Connection 8° 0° 0.0291 (0.74) x 45 ° 0.0098 (0.25) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) –16– REV. A PRINTED IN U.S.A. C1937–5–7/94