A3983

A3983 DMOS Microstepping Driver with Translator Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Description The A3983 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A3983 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A3983. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3983 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A3983 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A3983 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a slow decay for the remainder of the off-time). This current decay Continued on the next page… Package: 24-pin TSSOP with exposed thermal pad (suffix LP) Not to scale Functional Block Diagram 0.22 μF VREG ROSC CP1 0.1 μF CP2 VDD Current Regulator OSC Charge Pump VCP 0.1 μF DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay SENSE1 Gate Drive RS1 VBB2 STEP DIR RESET MS1 MS2 PWM Latch Blanking Mixed Decay DAC Translator Control Logic DMOS Full Bridge OUT2A OUT2B ENABLE SLEEP SENSE2 RS2 VREF 26184.29B A3983 DMOS Microstepping Driver with Translator Description (continued) control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage Selection Guide Part Number A3983SLP-T A3983SLPTR-T Pb-free Yes Yes Package 24-pin TSSOP with exposed thermal pad 24-pin TSSOP with exposed thermal pad 62 pieces per tube 4000 pieces per 13-in. reel Packing lockout (UVLO), and crossover-current protection. Special poweron sequencing is not required. The A3983 is supplied in a low-profile (1.2 mm maximum height), 24-pin TSSOP with exposed thermal pad (suffix LP). It is lead (Pb) free, with 100% matte tin leadframe plating. Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Input Voltage Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature Symbol VBB IOUT VIN VSENSE VREF TA TJ(max) Tstg Range S Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Notes Rating 35 ±2 –0.3 to 7 0.5 4 –20 to 85 150 –55 to 150 Units V A V V V ºC ºC ºC THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Package LP; 4-layer PCB, based on JEDEC standard) Value Units 28 ºC/W *In still air. Additional thermal information available on Allegro Web site. 5.5 5.0 Maximum Power Dissipation, PD(max) Power Dissipation, PD (W) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 (R θJ A = 28 ºC /W ) 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3983 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Min. 8 0 3.0 – – – – – – – – – – VDD×0.7 VIN = VDD×0.7 – –20 –20 – 150 0.7 20 23 0 –3 – – – 100 – – 2.35 0.05 Typ.2 – – – 0.350 0.300 – – – – – – – – – – 3 V, then tOFF defaults to 30 μs. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of tOFF (μs) is approximately tOFF ≈ ROSC ⁄ 825 Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the DMOS outputs of the A3983 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the DMOS outputs and resets the translator to the Home state. Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μs), is approximately tBLANK ≈ 1 μs Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output DMOS FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A3983 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A3983 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side DMOS gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side DMOS gates. VREG (VREG). This internally-generated voltage is used to operate the sink-side DMOS outputs. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the DMOS outputs of the A3983 are disabled. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 thru 5. As the trip point is reached, the A3983 initially goes into a fast decay mode for 31.25% of the off-time. tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low DMOS RDS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Turning off synchronous rectification prevents the reversal of the load current when a zero-current level is detected. Enable Input (ENABLE). This input turns on or off all of the DMOS outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, MS1, and MS2, as well as the internal sequencing logic, all remain active, independent of the ENABLE input state. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3983 DMOS Microstepping Driver with Translator STEP 100.00 70.71 STEP 100.00 70.71 Slow Slow Mixed Slow Mixed Home Microstep Position Home Microstep Position –70.71 –100.00 100.00 70.71 Home Microstep Position –70.71 –100.00 100.00 70.71 Slow Slow Mixed Mixed Slow Mixed Slow Phase 2 IOUT2A Direction = H (%) 0.00 Slow –70.71 Phase 2 IOUT2B Direction = H (%) 0.00 –70.71 –100.00 –100.00 Figure 2. Decay Mode for Full-Step Increments STEP 100.00 92.39 70.71 Figure 3. Decay Modes for Half-Step Increments –38.27 –70.71 –92.39 –100.00 100.00 92.39 70.71 38.27 Phase 2 IOUT2B Direction = H (%) Slow Mixed Slow Mixed Slow Mixed 0.00 –38.27 –70.71 –92.39 –100.00 Figure 4. Decay Modes for Quarter-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 Slow 0.00 Mixed Slow Mixed Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) Slow 0.00 Phase 1 IOUT1A Direction = H (%) Mixed 0.00 7 A3983 DMOS Microstepping Driver with Translator STEP 100.00 92.39 83.15 70.71 55.56 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 Phase 2 IOUT2B Direction = H (%) 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 Mixed Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 19.51 0.00 –19.51 Slow Mixed Slow Mixed Mixed Slow Figure 5. Decay Modes for Eighth-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A3983 DMOS Microstepping Driver with Translator Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step # Half Step # 1 1/4 Step # 1 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 1/8 Step # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Phase 1 Current [% ItripMax] Phase 2 Current [% ItripMax] (%) 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –98.08 –100.00 –98.08 –92.39 –83.15 –70.71 –55.56 –38.27 –19.51 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 (%) 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –98.08 –100.00 –98.08 –92.39 –83.15 –70.71 –55.56 –38.27 –19.51 Step Angle (º) 0.0 11.3 22.5 33.8 45.0 56.3 67.5 78.8 90.0 101.3 112.5 123.8 135.0 146.3 157.5 168.8 180.0 191.3 202.5 213.8 225.0 236.3 247.5 258.8 270.0 281.3 292.5 303.8 315.0 326.3 337.5 348.8 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A3983 DMOS Microstepping Driver with Translator Package LP CP1 CP2 VCP VREG MS1 MS2 RESET ROSC SLEEP 1 2 3 4 5 6 7 8 9 24 GND 23 ENABLE 22 OUT2B 21 VBB2 20 SENSE2 PAD 19 OUT2A 18 OUT1A 17 SENSE1 16 VBB1 15 OUT1B 14 DIR 13 GND VDD 10 STEP 11 REF 12 Terminal List Table Number Name Package LP CP1 CP2 VCP VREG MS1 MS2 RESET ROSC SLEEP VDD STEP REF GND DIR OUT1B VBB1 SENSE1 OUT1A OUT2A SENSE2 VBB2 OUT2B ENABLE NC PAD 1 2 3 4 5 6 7 8 9 10 11 12 13, 24 14 15 16 17 18 19 20 21 22 23 – – Charge pump capacitor terminal Charge pump capacitor terminal Reservoir capacitor terminal Regulator decoupling terminal Logic input Logic input Logic input Timing set Logic input Logic supply Logic input Gm reference voltage input Ground* Logic input DMOS Full Bridge 1 Output B Load supply Sense resistor terminal for Bridge 1 DMOS Full Bridge 1 Output A DMOS Full Bridge 2 Output A Sense resistor terminal for Bridge 2 Load supply DMOS Full Bridge 2 Output B Logic input No connection Exposed pad for enhanced thermal dissipation* Description *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 A3983 DMOS Microstepping Driver with Translator LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0.10 24 4° ±4 +0.05 0.15 –0.06 0.45 0.65 B 3.00 A 4.40 ±0.10 6.40 ±0.20 0.60 ±0.15 (1.00) 3.00 6.10 1 2 4.32 0.25 SEATING PLANE 0.65 1.20 MAX 0.15 MAX C SEATING PLANE GAUGE PLANE 1.65 C 4.32 PCB Layout Reference View 24X 0.10 C +0.05 0.25 –0.06 For reference only (reference JEDEC MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Copyright ©2005-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11