HFA3983

HFA3983 TM Data Sheet March 2000 File Number 4635.4 2.4GHz Power Amplifier and Detector The HFA3983 is a 2.4GHz monolithic SiGe Power Amplifier designed to operate in the ISM Band. It features two low voltage single supply stages. Cascaded, they deliver a 18dBm (Typ.) of an output power for the typical DSSS signal (ACPR, 1st Side Lobe < -30dBc, 2nd Side Lobe < -50dBc). In addition, the device includes a 2.4GHz detector which is accurate over a 15dB of dynamic range with (±)1dB. Therefore, an accurate ALC function can be implemented. The HFA3983 is housed in a 28 lead exposed paddle EPTSSOP package well suited for PCMCIA board applications. Features • Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.6V • Output Power . . . . . . . . . . . 18dBm (Typ) at ACPR, DSSS, 1st Side Lobe < -30dBc, 2nd Side Lobe < -50dBc • Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . .30dB (Typ.) • Detector Linear Input Power Range . . . . . . . . . . . . . .15dB • Detector Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0dB Applications • EEE802.11 1 and 2Mbps Standard • Systems Targeting IEEE802.11, 11Mbps Standard • Wireless Local Area Networks • PCMCIA Wireless Transceivers • ISM Systems Including Automatic Level Control (ALC) Simplified Block Diagram DS_VCC • TDMA Packet Protocol Radios Ordering Information PART NUMBER RF_IN RF_OUT TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE PKG. NO. HFA3983IV HFA3983IV96 28 Ld EPTSSOP M28.173A Tape and Reel PEAK DETECTOR Pinout BIAS LOG HFA3983 (EPTSSOP) TOP VIEW INDEX AREA DS_REXT PE DET_VOUT OS_REXT GND VCC PE GND VCC OS_REXT DS_REXT DS_VCC GND GND RF_OUT GND GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PACKAGE PINOUT SUBJECT TO CHANGE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC GND DET_VOUT GND GND GND RF_IN GND GND GND GND GND GND GND 4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. Further information is attainable upon NDA Agreement. NDA available on CD ROM or by contacting centapp@intersil.com. HFA3983 Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 9, 10 11 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 22 23, 24, 25 26 27 28 NAME GND VCC PE GND VCC OS_REXT DS_REXT DS_VCC GND RF_OUT GND RF_IN GND DET_VOUT GND VCC DC and RF Ground. Power supply. Digital input control pin to enable the operation of the Power Amplifier. Enable logic level is High. DC and RF Ground. Power supply. Output stage bias resistor, biasing scheme independent of absolute temperature. Driver stage bias resistor, biasing scheme independent of absolute temperature. Driver stage power supply. DC and RF Ground. RF Output of the Power Amplifier. DC and RF Ground. RF Input of the Power Amplifier. DC and RF Ground. Detector output. DC and RF Ground. Power supply. DESCRIPTION As part of the Prism II WLAN chip set, the HFA3983 works seamlessly with the chip set components to give you a highly integrated, cost effective 11Mb/s WLAN solution in the 2.4 to 2.5GHz ISM band. The HFA3983 is fabricated in the fastest SiGe BiCMOS process available, allowing superior RF performance, normally found only in GaAs ICs. Cost effective functions, normally requiring external components, are integrated into one IC. The HFA3983 integrates the following functions in one compact 28 pin EPTSSOP: Two Stage, 30dB Gain RFPA, Logarithmic power detect function (15dB Dynamic Range), CMOS level compatible Power Up/Down function, Single Supply, 2.7V to 3.6V Operation. The HFA3983 contains a highly linear RFPA designed to deliver 18dBm and meet an ACPR specification of -30dBc in the 2.4 to 2.5GHz ISM band. The performance of this two stage RFPA can be optimized by adjusting the bias current in each stage with a dedicated resistor. No external positive or negative power supplies are required to set the bias currents. The on chip bias network provides the optimum bias current temperature compensation when low TC external resistors are used. To get the best performance from the HFA3983, the output stage matching network can be tailored using external components. The HFA3983 power detect function provides a DC output voltage that is proportional to the logarithm of the output power. For an output power of 18dBm, the detector is accurate to within a dB. The slope of the detector output voltage is 100mV/dB over a 15dB dynamic range. A simple application of the detector is to provide in-line monitoring of the output power using a DC voltmeter. No longer is a power meter or spectrum analyzer required. A more value added application would use the HFA3861 Baseband Processor to dynamically monitor the HFA3983 output power and to control transmit power by adjusting the AGC of the HFA3783 IF Quadrature Modem to provide the best possible error free data transfer rate for any given environment. Closed loop power control is very important feature which compensates for variability in the transmit chain (radio to radio, channel to channel, over temperature...). The HFA3983 power up/down feature integrates the power down capability onto the IC and requires no external components, thus freeing up board space and reducing external component count and cost. When the CMOS compatible PE (power enable) pin is driven low, the total supply current drops to under 200µA in, typically, 230nS. When the PE pin is driven high, the full HFA3983 output power is available in a few hundred nanoseconds. In summary, the HFA3983 RFPA provides a highly cost effective solution for the PA function by integrating many features that would require significant development time, drive up the total bill of materials cost and consume precious board space. It interfaces seamlessly with the other Prism II ICs to provide a highly integrated, cost effective 11Mb/s WLAN solution in the 2.4 to 2.5GHz ISM band. 4-2 HFA3983 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . . -0.3 to VCC +0.3V VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Thermal Information Thermal Resistance (Typical, Note 1) θJC (oC/W) EPTSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . 15 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Moisture Sensitive Level (See Tech Brief 363) . . . . . . . . 72 Hrs (L4) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.6V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJC is measured with the component mounted on an evaluation PC board in free air with the exposed paddle soldered to an infinite heatsink. General DC Electrical Specifications PARAMETER Supply Voltage Total Power Amplifier Supply Current at 3.3V, 18dBm Output RF Detector Supply Current Power Down Supply Current Power Up/ Down Speed CMOS Low Level Input Voltage CMOS High Level Input Voltage (VDD = 3.3V) CMOS Threshold Voltage CMOS High or Low Level Input Current TEMP. (oC) Full 25 25 Full Full Full Full Full Full MIN 2.7 0.7*VDD -10 TYP 180 200 230 0.5*VDD MAX 3.6 5 0.3*VDD 3.6 +10 UNITS V mA mA µA ns V V V µA Power Amplifier AC Electrical Specifications VCC = 3.3V, f = 2.45GHz, Unless Otherwise Specified. Typical Application Circuit (external input and output matching networks) has been used. TEST CONDITIONS TEMP. (oC) Full Full Full 25 MIN 2400 28 TYP 30 MAX 2500 32 7 2.00:1 3.00:1 UNITS MHz dB dB - PARAMETER RF Frequency Range Power/Voltage Gain Noise Figure Input 50Ω VSWR Output 50Ω VSWR Output matching network optimized for P1dB compression ACPR, DSSS, 1st Side Lobe