A4982

A4982 DMOS Microstepping Driver with Translator and Overcurrent Protection Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Thin profile QFN and TSSOP packages Thermal shutdown circuitry Short-to-ground protection Shorted load protection Low current Sleep mode, < 10 μA No smoke no fire (NSNF) compliance (ET package) Description The A4982 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A4982 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The ET package meets customer requirements for no smoke no fire (NSNF) designs by adding no-connect pins between critical output, sense, and supply pins. So, in the case of a pin-to-adjacent-pin short, the device does not cause smoke or fire. Additionally, the device does not cause smoke or fire when any pin is shorted to ground or left open. The translator is the key to the easy implementation of the A4982. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4982 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. During stepping operation, the chopping control in the A4982 automatically selects the current decay mode, Slow or Mixed. Packages: with exposed thermal pad 5 mm × 5 mm × 0.90 mm (ET package) 24-pin TSSOP with exposed thermal pad (LP Package) 32-contact QFN Approximate size Continued on the next page… Typical Application Diagram VDD 0.22 μF VREG ROSC VDD 5 kΩ Microcontroller or Controller Logic SLEEP STEP MS1 MS2 DIR ENABLE RESET VREF GND GND OUT2A OUT2B SENSE2 CP1 CP2 VCP 0.1 μF 0.1 μF 0.22 μF VBB1 VBB2 OUT1A 100 μF A4982 OUT1B SENSE1 4982-DS A4982 DMOS Microstepping Driver with Translator and Overcurrent Protection Description (continued) In Mixed decay mode, the device is set initially to a fast decay for a proportion of the fixed off-time, then to a slow decay for the remainder of the off-time. Mixed decay current control results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4982 is supplied in two surface mount package, the ET, a 5 mm × 5 mm, 0.90 mm nominal overall package height QFN package, and the LP package, a 24-pin TSSOP. Both packages have exposed pads for enhanced thermal dissipation, and are lead (Pb) free (suffix –T), with 100% matte tin plated leadframes. Selection Guide Part Number A4982SETTR-T A4982SLPTR-T Package 32-pin QFN with exposed thermal pad 24-pin TSSOP with exposed thermal pad Packing 1500 pieces per 7-in. reel 4000 pieces per 13-in. reel Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Input Voltage Logic Supply Voltage VBBx to OUTx Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature VSENSE VREF TA TJ(max) Tstg Range S Symbol VBB IOUT VIN VDD Notes Rating 35 ±2 –0.3 to 5.5 –0.3 to 5.5 35 0.5 5.5 –20 to 85 150 –55 to 150 Units V A V V V V V ºC ºC ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4982 DMOS Microstepping Driver with Translator and Overcurrent Protection Functional Block Diagram 0.22 F VREG ROSC CP1 0.1 F CP2 VDD Current Regulator OSC Charge Pump VCP 0.1 F DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay OCP SENSE1 Gate Drive Control Logic OCP STEP DIR RESET MS1 MS2 Translator DMOS Full Bridge VBB2 RS1 OUT2A OUT2B ENABLE SLEEP DAC PWM Latch Blanking Mixed Decay SENSE2 RS2 VREF Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4982 DMOS Microstepping Driver with Translator and Overcurrent Protection Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Min. 8 0 3.0 – – – – – – – – – – VDD0.7 VIN = VDD0.7 – –20 –20 – – 5 0.7 20 23 0 –3 – – – 100 2.1 – – 2.7 – Typ.2 – – – 320 320 – – – – – – – – – –