AOZ8105CI

AOZ8105CI Ultra-Low Capacitance TVS Diode General Description Features The AOZ8105CI is a transient voltage suppressor array designed to protect high speed data lines such as HDMI and Gigabit Ethernet from damaging ESD events.  ESD protection for high-speed data lines: This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. – IEC 61000-4-5 (Lightning) 3A (8/20µs) The AOZ8105CI provides a typical line to line capacitance of 0.35pF and low insertion loss up to 3GHz providing greater signal integrity making it ideally suited for HDMI 1.3 applications, such as Digital TVs, DVD players, set-top boxes and mobile computing devices. The AOZ8105CI comes in RoHS compliant, tiny SOT-23-6 package and is rated -40°C to +85°C junction temperature range. – IEC 61000-4-2, level 4 (ESD) immunity test – ±30kV (air discharge) and ±24kV (contact discharge) – Human Body Model (HBM) ±24kV  Array of surge rated diodes with internal TVS diode  Small package saves board space  Protects four I/O lines  Low capacitance between I/O lines: 0.35pF  Low clamping voltage  Low operating voltage: 5.0V Applications  HDMI ports  Monitors and flat panel displays  Set-top box  USB 2.0 power and data line protection  Video graphics cards  Digital Video Interface (DVI)  10/100/1000 Ethernet  Notebook computers Typical Application Vcc I/O1 I/O2 I/O3 I/O4 Figure 1. HDMI Ports Rev. 4.1 September 2021 www.aosmd.com Page 1 of 11 AOZ8105CI Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ8105CI -40°C to +85°C SOT-23-6 Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration CH1 1 6 CH4 VN 2 5 VP CH2 3 4 CH3 SOT23-6 (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating Storage Temperature (TS) -65°C to +150°C ESD Rating per IEC61000-4-2, contact (1) ±24kV ESD Rating per IEC61000-4-2, air(1) ESD Rating per Human Body Model ±30kV (2) ±24kV Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k. Maximum Operating Ratings Parameter Rating Junction Temperature (TJ) Rev. 4.1 September 2021 -40°C to +125°C www.aosmd.com Page 2 of 11 AOZ8105CI Electrical Characteristics TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C. Symbol VRWM VBR Parameter Reverse Working Voltage Conditions Between VP and VN Min. (4) Reverse Breakdown Voltage IT = 1mA, between VP and VN IR Reverse Leakage Current VRWM = 5V, between VP and VN VF Diode Forward Voltage IF = 15mA VCL Cj 0.70 IPP = 1A, tp = 100ns, any I/O pin to Ground Channel Clamp Voltage Positive Transients Negative Transient IPP = 5A, tp = 100ns, any I/O pin to Ground(5) VR = 0V, f = 1MHz, any I/O pin to Ground(6) VP = 5.0V, VR = 2.5V, f = 1MHz, any I/O pins to Ground Channel Input Capacitance Matching Units 5.5 V V 0.85 1 µA 1 V (5) Channel Clamp Voltage Positive Transients Negative Transient Channel Input Capacitance Max. 6.6 VR = 0V, f = 1MHz, between I/O pins(6) Cj Typ. (3) VR = 0V, f = 1MHz, between I/O pins 12 -1.4 V V 16.5 -2.8 V V 0.35 pF 0.80 0.9 pF 0.43 0.5 pF 0.03 pF Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. 6. Measure performed with no external capacitor on VP . Rev. 4.1 September 2021 www.aosmd.com Page 3 of 11 AOZ8105CI Typical Operating Characteristics Negative Transmission Line Pulse (tp = 100ns, tr = 0.2ns) 30 0 25 -5 20 -10 TLP Current (A) TLP Current (A) Positive Transmission Line Pulse (tp = 100ns, tr = 0.2ns) 15 10 5 -20 -25 -30 0 -35 -14 -5 0 5 10 15 20 25 -12 -10 -8 -6 -4 -2 TLP Voltage (V) TLP Voltage (V) IEC61000-4-5 Positive Surge 8/20µs IEC61000-4-5 Negative Surge 8/20µs 16 0 14 -1 Clamping Voltage (V) Clamping Voltage (V) -15 12 10 8 6 4 0 -2 -3 -4 -5 -6 2 -7 0 0 1.5 2 2.5 3 -3 IPP (A) -2.5 -2 -1.5 -1 IPP (A) Typical Variation of CIN vs. VR (f = 1MHz, T = 25°C) Normalized Input Capacitance (pF) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 Reverse Voltage (V) Rev. 4.1 September 2021 www.aosmd.com Page 4 of 11 AOZ8105CI Application Information VGA Ports The AOZ8105CI TVS is designed to protect four high speed data lines from ESD and transient over-voltage by clamping them to a fixed voltage. When the voltages on the protected lines exceed the limit, the internal steering diode are forward bias will conduct the harmful transient away from the sensitive circuitry. As system frequency increases, printed circuit board layout becomes more complex. A successful high speed board must integrate the device and traces while avoiding signal transmission problems associated with HDMI data speed. With VGA ports back-drive current is a concern for system instability, start ups and power loss. The back-drive current occurs when two systems are connected through a cable and one system is OFF and another system is ON. In this case the system that is ON is the monitor. The monitor can inject current into the system that is turned OFF via the cable. To inhibit the back-drive current from happening, an integrated diode is designed into the AOZ8105CI to prevent current from going into the system that is turned OFF. Figure 2 shows the schematics where the back-drive current is flowing in a system that is turned OFF. Mother Board Video Monitor VGA 5V+ 6 System 5V 4 5 VGA 5V BAV 70 1 2 3 Cable 100Ω 100kΩ DDCA_SDA Scaler DDCA_SDA Figure 2. Back-Drive Current Path ESD Protection Sync VGA 5V Blue 6 5 4 Video Scaler 15 Pin DSUB Connector Red Green Blue Sync SCL SDA VSync HSync Dig Gnd Red Gnd Blue Gnd Green Gnd 1 2 Red 3 Green CLK VGA 5V SDA 6 5 4 1 2 VSYNC Red Green Blue Sync SCL SDA VSync HSync 3 HSYNC Figure 3. ESD Design for VGA Ports in which Two AOZ8105CI are Used Rev. 4.1 September 2021 www.aosmd.com Page 5 of 11 AOZ8105CI PCB Layout Example for VGA Port Figure 4 shows an example for a VGA port with two AOZ8105CI being used. Place the AOZ8105CI device as close to the connector as possible. Use ground plane wherever to ensure maximum performance of the device. possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8105CI device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8105CI ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8105CI is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8105CI is design to simply drop onto the IO lines of a High Definition Multimedia Interface (HDMI) design without having to divert the signal lines that may add more parasitic inductance. Figure 4. PCB Layout Example for VGA Port High Speed HDMI PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8105CI devices should be located as close as possible to the noise source. The placement of the AOZ8105CI devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8105CI devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest Rev. 4.1 September 2021 It is crucial that the layout is successful for a HDMI design PCB board. Some of the problems associated with high speed design are matching impedance of the traces and to minimize the crosstalk between parallel traces. This application note is to provide you as much information to successfully design a high speed PCB using Alpha & Omega devices. The HDMI video signals are transmitted on a very high speed pair of traces and any amount of capacitance, inductance or even bends in a trace can cause the impedance of a differential pair to drop as much as 40. This is not desirable because HDMI ports must maintain a 100 ±15% on each of the four pairs of its differential lines per HDMI Compliance Test Specifications. The HDMI CTS specifies that the impedance on the differential pair of a receiver must be measured using a Time Domain Reflectometry method with a pulse rise time of www.aosmd.com Page 6 of 11 AOZ8105CI ≤200pS. The TDR measurements of the PCB traces allows to locate and model discontinuities cause by the geometrical features of a bend and by the frequencydependant losses of the trace itself. These fast edge rates can contribute to noise and crosstalk, depending on the traces and PCB dielectric construction material. Typical value of W = 12.6 mil, h = 10mils, D = 10mils, t = 1.4mils and r = 4.0 with the equation below for a microstrip impedance yields: Material selection is another aspect that determines good characteristic impedance in the lines. Different material will give you different results. The dielectric material will have the dielectric constant (r). Zo = 61.73 Where Q1, Q2 = charges, r = distance between charges (m), F = force(N),  = permittivity of dielectric (F/m). Q1 Q F = --------------22 4r 5.98  h 87 Zo = -------------------------- = ln  ----------------------  0.8W + t  r + 1.41 (3) By solving for Zo you can calculate the differential impedance with the equation below. D – 0.96 ----  h Zdiff = 2  Zo  1 – 0.48e    Zdiff = 100.77 (4) (1) Each PCB substrate has a different relative dielectric constant. The dielectric constant is the permittivity of a relative that of empty space. Where r = dielectric constant,  = permittivity, and o = permittivity of empty space.  r = ---o (2) The dielectric constant affects the impedance of a transmission line and can propagate faster in materials that have a lower r . The frequency in your design will depend on the material being used. With equation 1 you can determine the type of material to use. If higher frequency is required other board material maybe considered. GETEK is another material that can be used in high speed boards. They have a typical r between 3.6 to 4.0. The most common type of dielectric material used for PCB is FR-4. Typical dielectric constant for FR-4 is between 4.0 to 4.5. Most PCB manufacture will be able to give you the exact value of the FR-4 dielectric constant. Once you determined the dielectric constant of the board material you can start to calculate the impedance of each trace. Below are the formulas for a microstrip layout. This impedance is dependant on the width of the microstrip (W) the thickness (t) of the trace and the height (h) of the FR4 material, and (D) trace edge to edge spacing. W D W Adjust the trace width, height, distance between the traces and FR4 thickness to obtain the desired 100 differential impedance. The general rule of thumb is to route the traces as short as possible, use differential routing strategies whenever feasible and match the length and bends to each of the differential traces. The graphs below show the differential impedance with varying trace width without the package part on it. Each of the graphs and board layout represent changing trace width from 100 to 160 in increment of 20. Figure 6. 100 Differential Impedance Max 103, Min 97 t Trace εr Dielectric Material H Ground Figure 5. Dimensions of Microstrip Layout Figure 7. 120 Differential Impedance Max 110, Min 102 Rev. 4.1 September 2021 www.aosmd.com Page 7 of 11 AOZ8105CI X Zo = 61Ω Zo = 61Ω Z1 C(TVS) Figure 11. Impedance Compensation Figure 8. 140 Differential Impedance Max 102, Min 92 Z K = -----1Z2 (5) Z 0 C TVS K X =  ---------------------  ----------------    2  K –1 (6) Z0 is the normal 61 differential impedance on the trace. Z1 is the need impedance to compensate for the added C(TVS) K is defined as the unloaded impedance of the adjusted trace. X is the length of the trace needed for the compensation. Figure 9. 160 Differential Impedance Max 123, Min 109  is the propagation delay time required for a signal to travel from one point to another. This value should be less than 200pS. Differentail Impedance (Ω) 140 120 Max. 100 Min. 80 60 40 20 0 50 55 60 65 70 75 80 Common Mode Impedance (Ω) Figure 10. Differential Impedance By adding a TVS onto the traces it can have a large effect on the impedance of the line. This addition of a capacitance added to a 100 differential transmission line without any compensation may decrease the impedance as much as 20 or more. Below is a formula to calculate the length for the compensation of C(TVS). Rev. 4.1 September 2021 From the above method the designer should layout the boards with a 50 common mode trace. The result should give you approximately 100 differential impedance. Z1 is the impedance that you choose in order to compensate the TVS capacitance. Based on Z1 value, we can get the length of the segment from the above equations. With the value of Z1 = 98, Zo = 61, C(TVS) = 0.7 and  = 180. The X(mils) equates to 250 mils. Page 9 has a series of graph that represent changing width and length of the trace from 100 to 160 in increment of 20 with a package solder onto the board. As you can observe from the graphs, a small incremental capacitance that is added to the differential lines can significantly decrease the differential impedance. Thus violated the HDMI specification of 100±15%. www.aosmd.com Page 8 of 11 AOZ8105CI Figure 12. 100Ω Differential Impedance with Package on it Max. 97Ω, Min. 80Ω Figure 14. 140Ω Differential Impedance with Package on it Max. 102Ω, Min. 92Ω Figure 13. 120Ω Differential Impedance with Package on it Max. 99Ω, Min. 86Ω Figure 15. 160Ω Differential Impedance with Package on it Max. 101Ω, Min. 95Ω From Figure 15 we are able to get the best result from using all of the equation above. With the value of Z1 = 98, Z0 = 61, C(TVS) = 0.7,  = 180. The X(mils) equates to 250 mils to give the best compensated Rev. 4.1 September 2021 differential impedance on the traces for the added capacitance from the AOZ8105CI. www.aosmd.com Page 9 of 11 AOZ8105CI Table 1. AOZ8105CI SOT-23-6 Evaluation Board Specifications Number of layers 100Ω Differential 4 Copper Trace Thickness 1.4 mils Dielectric Constant r 4 Overall Board Thickness 62 mils Dielectric thickness between top and ground layer 10 mils Conclusion 160Ω Differential 250 mils Total Distance Figure 16. Recommended Layout for SOT-23 Package Rev. 4.1 September 2021 This application section discusses ESD protection while maintaining the differential impedance of a HMDI sink device. Since the TVS add capacitance we must design the board to meet the HDMI requirements. This application note is a guideline to calculate and layout the PCB. Different board manufacture and process will fluctuate and will cause the final board to vary slightly. You must carefully plan out a successful high speed HDMI PCB. Factor such as PCB stack up, ground bounce, crosstalk and signal reflection can interfere with a signal. The layout, trace routing, board materials and impedance calculation discussed in this application note can help you design a more effective PCB. www.aosmd.com Page 10 of 11 AOZ8105CI LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. Alpha and Omega Semiconductor does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 4.1 September 2021 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 11 of 11