AMMC-6430-W50

AMMC - 6430 25 - 33 GHz Power Amplifier Data Sheet Chip Size: 2500 x 1750 µm (100 x 69 mils) Chip Size Tolerance: ± 10µm (±0.4 mils) Chip Thickness: 100 ± 10µm (4 ± 0.4 mils) Pad Dimensions: 100 x 100 µm (4 ± 0.4 mils) Description The AMMC-6430 MMIC is a broadband nearly 1W power amplifier designed for use in transmitters that operate in various frequency bands between 25GHz and 33GHz. This MMIC optimized for linear operation with an output third order intercept point (OIP3) of 37dBm. At 30GHz it provides 29dBm of output power (P-1dB) and 17dB of gain. The device has input and output matching circuitry for use in 50 Ω environments. The AMMC-6430 also inte grates a temperature compensated RF power detection circuit that enables power detection of 0.3V/W. DC bias is simple and the device operates on widely available 5.5V for current supply (negative voltage only needed for Vg). It is fabricated in a PHEMT process for exceptional power and gain performance. For improved reliability and moisture protection, the die is passivated at the active areas. Features • Wide frequency range: 25 - 33 GHz • High gain: 17 dB • Power: @30 GHz, P-1dB=29 dBm • Highly linear: OIP3=37dBm • Integrated RF power detector • 5.5 Volt, -0.7 Volt, 900mA operation Applications • Microwave Radio systems • Satellite VSAT and DBS systems • LMDS & Pt-Pt mmW Long Haul • 802.16 & 802.20 WiMax BWA • WLL and MMDS loops • Commercial grade military • Can be driven by AMMC-6345, increasingluding overall gain. AMMC-6430 Absolute Maximum Ratings[1] Symbol Vd Vg Id Pin Tch Tstg Parameters/Conditions Positive Drain Voltage Gate Supply Voltage Drain Current CW Input Power Operating Channel Temp. Storage Case Temp. Units V V mA dBm °C °C -65 -3 Min. Max. 7 0.5 1500 23 +150 +150 +300 Tmax Maximum Assembly Temp (60 sec max) °C Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. Note: These devices are ESD sensitive. The following precautions are strongly recommended. Ensure that an ESD approved carrier is used when dice are transported from one destination to another. Personal grounding is to be worn at all times when handling these devices AMMC-6430 DC Specifications/Physical Properties [1] Symbol Id Parameters and Test Conditions Drain Supply Current (under any RF power drive and temperature) (Vd=5.0 V, Vg set for Id Typical) Gate Supply Operating Voltage (Id(Q) = 900 (mA)) Thermal Resistance[2] (Backside temperature, Tb = 25°C) Units mA Min. Typ. 900 Max. 1000 Vg qch-b V °C/W -0.9 -0.7 9 -0.55 Notes: 1. Ambient operational temperature TA=25°C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (θch-b) = 10°C/W at Tchannel (Tc) = 107°C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data. AMMC-6430 RF Specifications [3, 4, 5] TA= 25°C, Vd=5.5V, Id(Q)=900 mA, Zo=50 Ω Symbol Gain P-1dB P-3dB OIP3 Parameters and Test Conditions Small-signal Gain[4] Output Power at 1dB Gain Compression Output Power at 3dB Gain Compression Third Order Intercept Point; Df=100MHz; Pin=-20dBm Input Return Loss[4] Output Return Loss[4] Min. Reverse Isolation Units dB dBm dBm dBm Minimum 14 27 Typical 17 28.5 29 37 Maximum Sigma 0.5 0.38 0.35 0.8 RLin RLout Isolation dB dB dB -15 -15 -43 0.92 0.63 1.8 Notes: 3. Small/Large -signal data measured in wafer form TA = 25°C. 4. 100% on-wafer RF test is done at frequency = 27, 29, and 32 GHz. Statistics based on 1500 part sample 5. Specifications are derived from measurements in a 50 Ω test environment. Aspects of the amplifier performance may be improved over a more narrow bandwidth by application of additional conjugate, linearity, or power matching. LSL LSL LSL 1 1. 1 1. 1 1. 1 1. 18 18.  8 9  8 Gain at 29 GHz P-1dB at 29 GHz P-1dB at 33 GHz Typical distribution of Small Signal Gain and Output Power @P-1dB. Based on 1500 part sampled over several production lots.  AMMC-6430 Typical Performances (TA = 25°C, Vd =5.5 V, ID = 900 mA, Zin = Zout = 50 Ω) NOTE: These measurements are in a 50 Ω test environment. Aspects of the amplifier performance may be improved over a more narrow bandwidth by application of additional conjugate, linearity, or power matching.  S1[dB] S1[dB] 0 10 0 - S11[dB] S[dB]  P-1 PAE 0 P-1 [dBm], PAE [%] Return Loss [dB] -10 S1[dB] S1 [dB] 1 -10 -1 -0 -  10 -0  0 1 0 1 0  0 Frequency [GHz]  -0 0 -0 1 0  0 Frequency [GHz]  0 10    8 0  Frequency [GHz]   Figure 1. Typical Gain and Reverse Isolation Figure 2. Typical Return Loss (Input and Output) Figure 3. Typical Output Power (@P-1dB) and PAE 10   0 Pout(dBm)  Po[dBm], and, PAE[%] 0  0 1 10  PAE[%] Id(total) 10 8  110 Noise Figure [dB] IP [dBm] 8   100    90 0   8 0  Frequency [GHz]   0   8 0 Frequency [GHz]   0 -10 - 0  10 Pin [dBm] 1 0 80 Figure 4. Typical Noise Figure Figure 5. Typical Output 3rd Order Intercept Pt. Figure 6. Typical Output Power, PAE, and Total Drain Current versus Input Power at30GHz 0 S11_0 S11_-0 S11_8 0 S_0 S_-0 S_8 0 S1_0 S1_-0 S1_8 - -  S11[dB] -10 S[dB] S1[dB] -10 0 -1 -1 1 -0 -0 - 1 0  0 Frequency[GHz]  0 - 1 0  0 Frequency[GHz]  0 10 1 0  0 Frequency[GHz]  0 Figure 7. Typical S11 over temperature Figure 8. Typical S22 over temperature Figure 9. Typical Gain over temperature  Ids [mA]  0  0 8 P-1 [dBm]    0  P-1_8deg P-1_0deg P-1_-0deg  8 0  Frequency [GHz]   Figure 10. Typical One dB Compression over temperature Typical Scattering Parameters [1], (TA = 25°C, Vd =5.5 V, ID = 900 mA, Zin = Zout = 50 Ω) S11 Freq GHz 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 dB -5.91 -6.57 -7.18 -7.75 -8.35 -9.21 -9.81 -10.49 -10.90 -11.38 -13.19 -14.34 -15.81 -17.43 -17.52 -21.12 -26.33 -24.36 -19.96 -19.75 -25.24 -26.81 -23.34 -22.06 -18.80 -17.57 -21.76 -23.11 -18.05 -15.25 -14.11 Mag 0.51 0.47 0.44 0.41 0.38 0.35 0.32 0.30 0.29 0.27 0.22 0.19 0.16 0.13 0.13 0.09 0.05 0.06 0.10 0.10 0.05 0.05 0.07 0.08 0.11 0.13 0.08 0.07 0.13 0.17 0.20 Phase S21 dB Mag 0.01 0.01 0.01 0.01 0.02 0.02 0.02 0.09 0.36 1.11 2.48 3.89 5.63 6.97 6.96 6.72 6.59 6.52 6.53 6.83 7.28 7.31 7.11 6.51 6.12 4.97 3.40 2.08 1.12 0.62 0.33 Phase -150.08 177.71 159.58 144.22 127.82 131.62 174.87 -173.40 146.31 86.03 12.36 -59.81 -128.14 160.79 96.24 39.34 -11.71 -61.96 -110.13 -159.96 145.89 92.90 34.67 -21.77 -80.57 -147.31 147.08 87.01 33.30 -13.03 -54.38 165.15 -38.73 148.07 -38.15 132.45 -38.84 116.37 -38.40 102.02 -35.23 89.97 76.63 65.83 53.72 38.47 26.38 19.22 11.11 8.99 -4.76 -14.59 -16.19 37.91 25.90 16.45 8.60 19.45 52.06 55.38 38.20 22.77 12.34 58.33 65.65 48.45 38.60 -35.73 -35.32 -21.06 -8.97 0.91 7.87 11.79 15.01 16.86 16.85 16.54 16.37 16.28 16.29 16.69 17.24 17.27 17.04 16.27 15.73 13.93 10.64 6.34 0.98 -4.18 -9.56 S12 dB -46.83 -47.99 -45.28 -44.76 -48.37 -48.26 -44.88 -48.33 -49.40 -46.28 -50.99 -48.99 -49.75 -49.86 -46.73 -45.27 -40.96 -42.37 -40.26 -42.17 -40.05 -44.07 -41.80 -41.87 -45.35 -44.88 -43.93 -39.80 -39.89 -39.87 -41.33 Mag 4.56E-03 3.99E-03 5.44E-03 5.78E-03 3.82E-03 3.86E-03 5.70E-03 3.83E-03 3.39E-03 4.85E-03 2.82E-03 3.55E-03 3.26E-03 3.21E-03 4.61E-03 5.45E-03 8.96E-03 7.62E-03 9.71E-03 7.79E-03 9.95E-03 6.26E-03 8.13E-03 8.07E-03 5.40E-03 5.70E-03 6.36E-03 1.02E-02 1.01E-02 1.02E-02 8.59E-03 Phase -163.93 161.86 162.25 127.45 114.36 99.54 76.35 66.69 62.63 90.04 85.49 59.91 65.89 101.47 79.40 80.30 82.13 68.87 49.68 47.32 32.17 27.80 27.52 29.56 9.23 28.68 69.74 47.20 23.04 16.72 38.69 S22 dB -4.57 -5.15 -5.83 -7.10 -5.96 -6.74 -7.98 -9.74 -12.08 -15.37 -20.54 -33.57 -27.13 -20.75 -17.92 -19.27 -23.28 -29.28 -23.52 -22.46 -24.92 -31.37 -27.49 -20.47 -19.49 -18.86 -18.79 -19.84 -20.37 -19.65 -19.65 Mag 0.59 0.55 0.51 0.44 0.50 0.46 0.40 0.33 0.25 0.17 0.09 0.02 0.04 0.09 0.13 0.11 0.07 0.03 0.07 0.08 0.06 0.03 0.04 0.09 0.11 0.11 0.12 0.10 0.10 0.10 0.10 Phase 164.28 144.68 125.30 109.48 93.30 66.48 42.81 19.70 -2.59 -23.98 -43.76 -36.06 58.91 56.63 20.33 -3.94 -27.01 -9.02 26.76 16.30 -25.48 -70.15 124.04 87.29 57.42 45.83 42.27 33.52 37.79 38.29 41.26 Note: 1. Data obtained from on-wafer measurements.  Biasing and Operation The recommended quiescent DC bias condition for optimum efficiency, performance, and reliability is Vd=5 volts with Vg set for Id=950 mA. Minor improvements in performance are possible depending on the application. The drain bias voltage range is 3 to 5.5V. A single DC gate supply connected to Vg will bias all gain stages. Muting can be accomplished by setting Vg and /or Vg to the pinch-off voltage Vp. An optional output power detector network is also provided. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power emerging from the RF output port. The detected voltage is given by : V = ( ref − Vdet )− Vofs V Assembly Techniques The backside of the MMIC chip is RF ground. For microstrip applications the chip should be attached directly to the ground plane (e.g. circuit carrier or heatsink) using electrically conductive epoxy [1] For best performance, the topside of the MMIC should be brought up to the same height as the circuit surrounding it. This can be accomplished by mounting a gold plate metal shim (same length and width as the MMIC) under the chip which is of correct thickness to make the chip and adjacent circuit the same height. The amount of epoxy used for the chip and/or shim attachment should be just enough to provide a thin fillet around the bottom perimeter of the chip or shim. The ground plain should be free of any residue that may jeopardize electrical or mechanical attachment. The location of the RF bond pads is shown in Figure 12. Note that all the RF input and output ports are in a GroundSignal configuration. RF connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. A single bond wire is normally sufficient for signal connections, however double bonding with 0.7 mil gold wire or use of gold mesh [2] is recommended for best performance, especially near the high end of the frequency band. Thermosonic wedge bonding is preferred method for wire attachment to the bond pads. Gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams and a ultrasonic power of roughly 55 dB for a duration of 76 +/- 8 mS. The guided wedge at an untrasonic power level of 64 dB can be used for 0.7 mil wire. The recommended wire bond stage temperature is 150 +/- 2C. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. The chip is 100um thick and should be handled with care. This MMIC has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up the die with a vacuum on die center). This MMIC is also static sensitive and ESD precautions should be taken. Notes: [1] Ablebond 84-1 LM1 silver epoxy is recommended. [2] Buckbee-Mears Corporation, St. Paul, MN, 800-262-3824 where Vref is the voltage at the DET _ R port, Vdet is a voltage at the DET _ O port, and Vofs is the zero-input-power offset voltage. There are three methods to calculate : 1. Vofs can be measured before each detector measure- ment (by removing or switching off the power source and measuring ). This method gives an error due to temperature drift of less than 0.01dB/50°C. 2. Vofs can be measured at a single reference temperature. The drift error will be less than 0.25dB. 3. Vofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate at any temperature. This method gives an error close to the method #1. The RF ports are AC coupled at the RF input to the first stage and the RF output of the final stage. No ground wired are needed since ground connections are made with plated through-holes to the backside of the device.  DET_R Vg Vd DQ DET_O RFout RFin Three stage 0.W power amplifier Figure 11. AMMC-6430 Schematic Figure 12. AMMC-6430 Bonding pad locations  V g ( Optional ) 0.1µF 8 pF Vd 0.1µF Vg Vd DET_O RFOutput AMMC-0 Vd RFInput RFI RFO DET_R Vg 0.1µF 8 pF Vd 0.1µF Notes: 1. 1µF capacitors on gate and drain lines not shown required. . Vg connection is recommended on both sides for devices operating at or above P1dB. Vg Figure 13. AMMC-6430 Assembly diagram Vd 0.35 0.3 Det_R - Det_O [V] 0.25 0.2 0.15 0.1 0.05 0 5 10 15 20 25 Pout[dBm] 30 35 1 Ordering information: AMMC-6430-W10 = 10 devices per tray AMMC-6430-W50 = 50 devices per tray 0.1 0.01 0.001 Figure 14. AMMC-6430 Typical Detector Voltage and Output Power, Freq=30 GHz For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. 5989-3936EN - April 12, 2006  Det_R - Det_O [V]