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SN74LVC1G123
SCES586D – JULY 2004 – REVISED JUNE 2015
SN74LVC1G123 Single Retriggerable Monostable Multivibrator
With Schmitt-Trigger Inputs
1 Features
3 Description
•
The SN74LVC1G123 device is a single retriggerable
monostable multivibrator designed for 1.65-V to 5.5-V
VCC operation.
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Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 8 ns at 3.3 V
Supports Mixed-Mode Voltage Operation on
All Ports
Supports Down Translation to VCC
Schmitt-Trigger Circuitry on A and B Inputs for
Slow Input Transition Rates
Edge Triggered From Active-High or Active-Low
Gated Logic Inputs
Retriggerable for Very Long Output Pulses, Up to
100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
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AV Receivers
Blu-ray Players and Home Theaters
DVD Recorders and Players
Desktop PCs or Notebook PCs
Digital Radio and Internet Radio Players
Digital Video Cameras (DVC)
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices
Network Attached Storage (NAS)
Personal Digital Assistant (PDA)
Server PSU
Solid-State Drive (SSD): Client and Enterprise
Video Analytics Servers
Wireless Headsets, Keyboards, and Mice
This monostable multivibrator features output pulseduration control by three methods. In the first method,
the A input is low, and the B input goes high. In the
second method, the B input is high, and the A input
goes low. In the third method, the A input is low, the
B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting
external resistance and capacitance values. The
external timing capacitor must be connected between
Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and VCC. To obtain
variable pulse durations, connect an external variable
resistance between Rext/Cext and VCC. The output
pulse duration also can be reduced by taking CLR
low.
Pulse triggering occurs at a particular voltage level
and is not directly related to the transition time of the
input pulse. The A and B inputs have Schmitt triggers
with sufficient hysteresis to handle slow input
transition rates with jitter-free triggering at the
outputs.
Device Information(1)
PART NUMBER
SN74LVC1G123
PACKAGE
BODY SIZE (NOM)
SSOP (8)
2.95 mm × 2.80 mm
VSSOP (8)
2.30 mm × 2.00 mm
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
7
A
B
CLR
1
6
2
5
3
Rext/Cext
Cext
Q
R
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G123
SCES586D – JULY 2004 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Timing Requirements ................................................
Switching Characteristics, CL = 15 pF, –40°C to
85°C ...........................................................................
6.8 Switching Characteristics, CL = 50 pF, –40°C to
85°C ...........................................................................
6.9 Switching Characteristics, CL = 50 pF, –40°C to
125°C .........................................................................
6.10 Operating Characteristics........................................
6.11 Typical Characteristics ............................................
7
8
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 16
7
7
7
7
8
Parameter Measurement Information .................. 9
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2013) to Revision D
Page
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Typical
Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Removed duplicate Timing Requirements table .................................................................................................................... 6
Changes from Revision B (January 2007) to Revision C
Page
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Updated document to new TI data sheet format. ................................................................................................................... 1
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Updated Features ................................................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 4
•
Added Thermal Information table. .......................................................................................................................................... 5
2
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SN74LVC1G123
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SCES586D – JULY 2004 – REVISED JUNE 2015
5 Pin Configuration and Functions
DCT Package
8-Pin SSOP
Top View
DCU Package
8-Pin VSSOP
Top View
A
1
8
VCC
B
2
7
Rext/Cext
CLR
3
6
Cext
GND
4
5
Q
A
B
CLR
GND
1
2
3
8
7
6
4
5
VCC
Rext/Cext
Cext
Q
See mechanical drawings for dimensions.
YZP Package
8-Pin DSBGA
Bottom View
GND
CLR
B
A
4 5
3 6
2 7
1 8
Q
Cext
Rext/Cext
VCC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
1
I
Falling edge sensitive input; requires B and CLR to be held high.
B
2
I
Rising edge sensitive input; requires A to be held low and CLR to be held high.
CLR
3
I
Clear, Active Low; also can operate as rising edge sensitive input if A is held low and B is held high.
GND
4
—
Ground
Q
5
O
Output
Cext
6
—
Connects only to the external capacitor
Rext/Cext
7
—
Connects to the external capacitor and resistor
VCC
8
—
Power
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SCES586D – JULY 2004 – REVISED JUNE 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
+2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
+1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
1.5
Low-level input voltage
VI
Input voltage
VO
Output voltage
1.7
0.7 × VCC
0.35 × VCC
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
VCC = 2.3 V
IOH
High-level output current
VCC = 3 V
VCC = 4.5 V
(1)
4
V
2
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
0.3 × VCC
0
5.5
V
0
VCC
V
–4
–8
–16
mA
–24
–32
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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SCES586D – JULY 2004 – REVISED JUNE 2015
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
8
16
VCC = 3 V
External timing resistance
TA
Operating free-air temperature
(2)
mA
24
VCC = 4.5 V
Rext (2)
UNIT
32
VCC = 2 V
5
VCC ≥ 3 V
1
kΩ
–40
125
°C
Rext/Cext is an I/O and must not be connected directly to GND or VCC.
6.4 Thermal Information
SN74LVC1G123
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
DCT (SSOP)
DCU (VSSOP)
YZP (DSBGA)
8 PINS
8 PINS
8 PINS
220
227
102
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.65 V to
5.5 V
IOH = –100 µA
VOH
VCC
VCC – 0.1
VCC – 0.1
1.2
1.2
1.9
1.9
2.4
2.4
2.3
2.3
3.8
3.8
3V
MAX
IOL = 100 µA
1.65 V to
5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
3V
B = GND,
A, B, CLR
VI = 5.5 V or GND
Ioff
A, B, Q, CLR
VI or VO = 5.5 V
ICC
Quiescent
VI = VCC or GND,
VI = VCC or GND,
A = CLR = VCC
UNIT
V
4.5 V
Rext/Cext (2)
4.5 V
0.55
0.55
1.65 V to
5.5 V
±0.25
±0.25
±1
±1
V
µA
0
±10
±10
µA
5.5 V
20
20
µA
1.65 V
165
165
2.3 V
220
220
3V
280
280
4.5 V
650
650
975
975
IO = 0
Rext/Cext = 0.5 VCC
5.5 V
(1)
(2)
TYP (1)
IOH = –32 mA
IOL = 32 mA
CI
MIN
2.3 V
IOL = 24 mA
Active state
–40°C TO 125°C
MAX
1.65 V
IOL = 16 mA
ICC
TYP (1)
IOH = –8 mA
IOH = –24 mA
II
MIN
IOH = –4 mA
IOH = –16 mA
VOL
–40°C TO 85°C
VI = VCC or GND
3.3 V
3
µA
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This test is performed with the terminal in the OFF-state condition.
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6.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8)
–40°C TO 125°C
PARAMETER
VCC = 1.8 V
± 0.15 V
TEST CONDITIONS
MIN
twIN
Pulse duration
TYP
MIN
TYP
VCC = 3.3 V
± 0.3 V
MIN
TYP
VCC = 5 V
± 0.5 V
MIN
CLR
8
4
3
2.5
A or B trigger
8
4
3
2.5
Rext = 1 kΩ
trr
VCC = 2.5 V
± 0.2 V
Pulse retrigger time
Rext = 5 kΩ
UNIT
TYP
ns
Cext = 100 pF
5.5
4.5
ns
Cext = 100 µF
1.4
1.1
µs
Cext = 100 pF
75
45
ns
Cext = 100 µF
1.8
1.4
µs
VCC
R
Rext/Cext
C
Cext
Figure 1. Required Timing Circuit
trr
A
B
CLR
Rext/Cext
Q
tw
tw
tw + trr
Figure 2. Input/Output Timing Diagram
6
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6.7 Switching Characteristics, CL = 15 pF, –40°C to 85°C
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 8)
–40°C TO 85°C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
CLR
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
7
18.5
52
4
17
3
11.5
2
7.6
5
12.4
34
3
11.5
2
8
1.5
5.5
7
17.4
54
4
15.5
3
10.5
2
7
A or B
tpd
VCC = 2.5 V
± 0.2 V
Q
CLR trigger
ns
6.8 Switching Characteristics, CL = 50 pF, –40°C to 85°C
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 9)
–40°C TO 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC = 1.8 V
± 0.15 V
MAX
MIN
MAX
MIN
MAX
MIN
MAX
57
3
18.5
2
12.5
1.5
8.2
4
11.6
36.5
2
12.5
1.5
8.6
1.5
6
5
17.3
59
2.5
17
2
11.5
1.5
7.5
Cext = 28 pF,
Rext = 2 kΩ
225
600
190
220
170
200
150
180
ns
Cext = 0.01 μF,
Rext = 10 kΩ
100
110
100
110
100
110
100
110
µs
Cext = 0.1 μF,
Rext = 10 kΩ
1
1.1
1
1.1
1
1.1
1
1.1
ms
CLR trigger
(1)
(2)
Q
UNIT
18.6
Q
twOUT (2)
VCC = 5 V
± 0.5 V
6
MIN
CLR
VCC = 3.3 V
± 0.3 V
(1)
A or B
tpd
VCC = 2.5 V
± 0.2 V
TYP
ns
TA = 25°C
tw = Duration of pulse at Q output
6.9 Switching Characteristics, CL = 50 pF, –40°C to 125°C
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 9)
–40°C TO 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC = 1.8 V
± 0.15 V
MIN
A or B
tpd
CLR
Q
CLR trigger
twOUT (2)
(1)
(2)
Q
TYP
(1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
6
58
3
19.5
2
13.2
1.5
8.7
4
37
2
13.5
1.5
9.2
1.5
6.5
5
60
2.5
18
2
12
1.5
8
ns
Cext = 28 pF,
Rext = 2 kΩ
225
600
190
220
170
200
150
180
ns
Cext = 0.01 µF,
Rext = 10 kΩ
100
110
100
110
100
110
100
110
µs
Cext = 0.1 µF,
Rext = 10 kΩ
1
1.1
1
1.1
1
1.1
1
1.1
ms
TA = 25°C
tw = Duration of pulse at Q output
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
A = low, B = high,
CLR = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
TYP
35
37
Rext = 1 kΩ,
No Cext
Rext = 5 kΩ,
No Cext
VCC = 5 V
UNIT
pF
41
40
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6.11 Typical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
108
107
109
VCC = 1.8 V
TA = 25°C
tw − Output Pulse Duration − ns
tw − Output Pulse Duration − ns
109
106
105
104
103
RL =
5 kΩ
10 kΩ
100 kΩ
200 kΩ
102
101
1
10
102
103
104
105
VCC = 3.3 V
TA = 25°C
108
107
106
105
104
RL =
1 kΩ
5 kΩ
10 kΩ
100 kΩ
200 kΩ
103
102
101
1
10
106
102
tw − Output Pulse Duration Constant − K
tw − Output Pulse Duration − ns
VCC = 5 V
TA = 25°C
107
106
105
RL =
1 kΩ
5 kΩ
10 kΩ
100 kΩ
200 kΩ
103
102
101
1
10
102
103
104
105
106
Figure 4. Output Pulse Duration
vs External Timing Capacitance
109
104
104
Cext − External Timing Capacitance − pF
Cext − External Timing Capacitance − pF
Figure 3. Output Pulse Duration
vs External Timing Capacitance
108
103
105
106
1.3
1.25
1000 pF
1.2
1.15
1.1
0.01 µ F
1.05
1
0.1 µ F
0.95
0.9
0
1
Cext − External Timing Capacitance − pF
2
3
4
5
6
VCC − Supply Voltage − V
Figure 5. Output Pulse Duration
vs External Timing Capacitance
Figure 6. Output Pulse Duration Constant
vs Supply Voltage
Minimum Retrigger Time − µs
10
0.01 µF
1
1000 pF
100 pF
0.1
10 pF
0.01
1.65
2.3
3
3.3
4.5
5
5.5
VCC − Supply Voltage − V
Figure 7. Minimum Retrigger Time
vs Supply Voltage
8
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 8. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 9. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC
operation.
This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A
input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In
the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected
between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between
Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates
with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or highlevel-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or B
inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
The SN74LVC1G123 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
8.2 Functional Block Diagram
7
A
B
CLR
1
6
2
5
3
Rext/Cext
Cext
Q
R
8.3 Feature Description
This part is available in the Texas Instruments NanoFree™ package. It supports 5-V VCC operation and accepts
inputs up to 5.5 V. The max tpd is 8 ns at 3.3 V. It supports mixed-mode voltage operation on all ports.
Down translation can be achieved to VCC from up to 5.5 V.
Schmitt-trigger circuitry on A and B inputs allows for slow input transition rates. The device can be edge triggered
from active-high or active-low gated logic inputs. It can support up to 100% duty cycle from retriggering.
Clear can be used to terminate the output pulse early.
Glitch-free power-up reset is on all outputs.
Ioff supports live insertion, partial-power-down mode, and back-drive protection.
Latch-up performance exceeds 100 mA per JESD 78, Class II.
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8.4 Device Functional Modes
Table 1 lists the functional modes for the SN74LVC1G123.
Table 1. Function Table
INPUTS
(1)
12
CLR
A
B
OUTPUTS
Q
L
X
X
L
X
H
X
L (1)
X
X
L
L (1)
H
L
↑
H
↓
H
↑
L
H
These outputs are based on the assumption that the indicated
steady-state conditions at the A and B inputs have been set up long
enough to complete any pulse started before the setup.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G123 can be used for many applications. The application shown here is a switch debounce
circuit. Many switches produce multiple triggers when pressed, and the debounce circuit turns the many triggers
into one. This circuit takes advantage of the retrigger capability of the SN74LVC1G123 in that the output pulse
length only has to be longer than the longest individual bounce (typically less than 1 ms).
9.2 Typical Application
SN74LVC1G123
VCC
RPU
VCC
1
A
VCC
8
2
B
Rext/Cext
7
3
CLR
Cext
6
4
GND
Q
5
VCC
R
S1
C
OUTPUT
Figure 10. Typical Application of the SN74LVC1G123
9.2.1 Design Requirements
1. Recommended Input Conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Inputs and outputs are overvoltage tolerant, allowing them to go as high as 4.6 V at any valid VCC.
2. Recommended Output Conditions:
– Load current should not exceed values listed in Recommended Operating Conditions.
9.2.2 Detailed Design Procedure
The values for VCC, RPU, R, and C must be selected for proper operation.
VCC is selected at 1.8 V. This value is usually driven by the logic voltage of the system, but is arbitrary in this
case.
RPU is selected at 10 kΩ.
R and C are selected via the plots in Application Curves and are based on the time desired for the output pulse.
In this case, the output pulse will be 1 ms. Since the supply voltage has been selected at 1.8 V, Figure 11 is
used to determine the R and C values required. First convert the desired pulse width (tw), 1 ms, to ns. This yields
106 ns. Next follow that line across to see which R and C values intersect it.
R is selected at 10 kΩ because that line intersects nicely with 106 ns and 105 pF, making the selection of C at 0.1
µF easy.
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Table 2. Application Specific Values
PARAMETER
VALUE
VCC
1.8 V
RPU
10 kΩ
tw
1 ms
R (Rext)
10 kΩ
C (Cext)
0.1 µF
In addition to the shown components, a 0.1-µF decoupling capacitor from VCC to ground should be placed as
close as possible to the device.
9.2.3 Application Curves
108
107
109
VCC = 1.8 V
TA = 25°C
tw − Output Pulse Duration − ns
tw − Output Pulse Duration − ns
109
106
105
104
103
RL =
5 kΩ
10 kΩ
100 kΩ
200 kΩ
102
101
1
10
102
103
104
105
VCC = 3.3 V
TA = 25°C
108
107
106
105
104
RL =
1 kΩ
5 kΩ
10 kΩ
100 kΩ
200 kΩ
103
102
101
1
10
106
102
tw − Output Pulse Duration Constant − K
tw − Output Pulse Duration − ns
VCC = 5 V
TA = 25°C
107
106
105
RL =
1 kΩ
5 kΩ
10 kΩ
100 kΩ
200 kΩ
103
102
101
1
10
102
103
104
105
14
106
106
1.3
1.25
1000 pF
1.2
1.15
1.1
0.01 µ F
1.05
1
0.1 µ F
0.95
0.9
0
1
Cext − External Timing Capacitance − pF
Figure 13. Output Pulse Duration
vs External Timing Capacitance
105
Figure 12. Output Pulse Duration
vs External Timing Capacitance
109
104
104
Cext − External Timing Capacitance − pF
Cext − External Timing Capacitance − pF
Figure 11. Output Pulse Duration
vs External Timing Capacitance
108
103
2
3
4
5
6
VCC − Supply Voltage − V
Figure 14. Output Pulse Duration Constant
vs Supply Voltage
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Minimum Retrigger Time − µs
10
0.01 µF
1
1000 pF
100 pF
0.1
10 pF
0.01
1.65
2.3
3
3.3
4.5
5
5.5
VCC − Supply Voltage − V
Figure 15. Minimum Retrigger Time
vs Supply Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 16 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
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11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 16. Trace Example
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74LVC1G123DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23
(R, Z)
Samples
74LVC1G123DCTRG4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23
(R, Z)
Samples
74LVC1G123DCTTE4
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23
(R, Z)
Samples
74LVC1G123DCTTG4
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23
(R, Z)
Samples
74LVC1G123DCURE4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23R
Samples
74LVC1G123DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23R
Samples
74LVC1G123DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23R
Samples
SN74LVC1G123DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23
(R, Z)
Samples
SN74LVC1G123DCTT
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C23
(R, Z)
Samples
SN74LVC1G123DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(22FT, C23Q, C23R)
Samples
SN74LVC1G123DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C23J, C23Q, C23R)
Samples
SN74LVC1G123YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(D87, D8N)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Oct-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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