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SN74LVC1G139
SCES602E – AUGUST 2004 – REVISED JANUARY 2018
SN74LVC1G139 2-to-4 Line Decoder
1 Features
3 Description
•
This SN74LVC1G139 2-to-4 line decoder is designed
for 1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 4.9 ns at 3.3 V and 15 pF
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
AV Receivers
Solid State Drives (SSDs): Client and Enterprise
TVs: LCD, Digital, and High-Definition (HD)
Tablets: Enterprise
Video Analytics: Server
The SN74LVC1G139 2-line to 4-line decoder is
designed to be used in high-performance memorydecoding or data-routing applications requiring very
short propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When used
with high-speed memories using a fast enable circuit,
the delay times of these decoders and the enable
time of the memory usually are less than the typical
access time of the memory. This means that the
effective system delay introduced by the decoder is
negligible.
NanoStar and NanoFree package technology is a
major breakthrough in device packaging concepts,
using the die as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC1G139DCT
PACKAGE
SM8 (8)
BODY SIZE (NOM)
2.95 mm × 2.80 mm
SN74LVC1G139DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC1G139YZP
1.91 mm × 0.91 mm
DSBGA (8)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
A
1
3
Y3
Select
Inputs
B
2
5
Y2
Data
Outputs
6
7
Y1
Y0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G139
SCES602E – AUGUST 2004 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specification...........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics.......................................... 7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
9.1 Overview ................................................................. 10
9.2 Functional Block Diagram ....................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
13.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2014) to Revision E
•
Updated the YZP package drawing........................................................................................................................................ 3
Changes from Revision C (December 2005) to Revision D
•
Page
Page
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision B (December 2005) to Revision C
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Updated Features. .................................................................................................................................................................. 1
•
Removed Ordering Information table. .................................................................................................................................... 1
2
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SCES602E – AUGUST 2004 – REVISED JANUARY 2018
5 Pin Configuration and Functions
DCT Package
8-Pin SM8
Top View
DCU Package
8-Pin VSSOP
Top View
A
1
8
VCC
B
2
7
Y0
Y3
3
6
Y1
GND
4
5
Y2
A
B
Y3
GND
1
2
3
8
7
6
4
5
VCC
Y0
Y1
Y2
YZP Package
8-Pin DSBGA
Bottom View
1
2
D
GND
Y2
C
Y3
Y1
B
B
Y0
A
A
VCC
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DCT, DCU
YZP
A
1
A1
I
Adress input, bit 0
B
2
B1
I
Adress input, bit 1
Y3
3
C1
O
Output 3, low when B is high and A is high
GND
4
D1
—
Ground
Y2
5
D2
O
Output 2, low when B is high and A is low
Y1
6
C2
O
Output 1, low when B is low and A is high
Y0
7
B2
O
Output 0, low when B is low and A is low
VCC
8
A2
—
Power pin
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6 Specification
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply Voltage, VCC
–0.5
6.5
V
Input Voltage, VI
–0.5
6.5
V
Voltage applied to any output in the high-impedance or power-off state, VO (2)
–0.5
6.5
V
Voltage applied to any output in the high or low state, VO (2) (3)
–0.5
VCC + 0.5
V
Input clamp current, IIK
VI < 0
–50
mA
Output clamp current, IOK
VO < 0
–50
mA
Continuous output current, IO
±50
mA
Continuous current through VCC or GND, ICC
±100
mA
Junction temperature, TJ
150
°C
150
°C
Storage temperature, Tstg
(1)
(2)
(3)
-65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
MIN
MAX
Operating
1.65
5.5
Data retention only
1.5
VCC = 1.65 V to 1.95 V
VIH
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
2
VCC = 4.5 V to 5.5 V
VIL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
15
VCC = 5 V ± 0.5 V
(1)
mA
–24
ns/V
10
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or Floating
CMOS Inputs application report.
6.4 Thermal Information
SN74LVC1G139
THERMAL METRIC
(1)
DCT (SM8)
DCU (VSSOP)
YZP (DSBGA)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
194
195
106
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
124
74
1.6
°C/W
RθJB
Junction-to-board thermal resistance
106
74
11
°C/W
ψJT
Junction-to-top characterization parameter
48
6.7
3.1
°C/W
ψJB
Junction-to-board characterization parameter
105
73
11
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA, VCC = 1.65 V to 5.5 V
High-level output
voltage
VOH
Low-level output
voltage
VOL
TYP (1)
MIN
MAX
UNIT
VCC – 0.1
IOH = –4 mA, VCC= 1.65 V
1.2
IOH = –8 mA, VCC = 2.3 V
1.9
IOH = –16 mA, VCC = 3 V
2.4
IOH = –24 mA, VCC = 3 V
2.3
IOH = –32 mA, VCC = 4.5 V
3.8
V
IOL = 100 µA, VCC = 1.65 V to 5.5 V
0.1
IOL = 4 mA, VCC = 1.65 V
0.45
IOL = 8 mA, VCC = 2.3 V
0.3
IOL = 16 mA, VCC = 3 V
0.4
IOL = 24 mA, VCC = 3 V
0.55
IOL = 32 mA, VCC = 4.5 V
0.55
V
II
Inflection-point
current
A or B inputs:
VI = 5.5 V or GND, VCC = 0 to 5.5 V
±1
µA
Ioff
Off-state current
VI or VO = 5.5 V, VCC = 0
±5
µA
ICC
Supply current
VI = 5.5 V or GND, IO = 0, VCC = 1.65 V to 5.5 V
10
µA
ΔICC
Supply current
change
One input at VCC – 0.6 V, other inputs at VCC or GND, VCC = 3 V to
5.5 V
500
µA
Ci
Input capacitance VI = VCC or GND, VCC = 3.3 V
(1)
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Table 2
tpd
Propagation
delay time
A or B-to-Y
See Table 3
MIN
MAX
VCC = 1.8 V ± 0.15 V
2.7
15.3
VCC = 2.5 V ± 0.2 V
1.5
7.5
VCC = 3.3 V ± 0.3 V
0.9
4.9
VCC = 5 V ± 0.5 V
0.8
3.6
VCC = 1.8 V ± 0.15 V
3
16.7
VCC = 2.5 V ± 0.2 V
1.6
8.2
VCC = 3.3 V ± 0.3 V
1.2
5.9
VCC = 5 V ± 0.5 V
1.1
4.2
UNIT
ns
6.7 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd (1)
(1)
6
Power dissipation
capacitance
f = 10 MHz
MIN
TYP
VCC = 1.8 V
31
VCC = 2.5 V
34
VCC = 3.3 V
36
VCC = 5 V
39
MAX
UNIT
pF
Two outputs switching.
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7 Typical Characteristics
8
Long tpLH
Propagation Delay (nS)
7
Long tpHL
6
Short tpHL
5
Short tpLH
4
3
2
1
0
1.5
2.0
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
C001
(1) Short is 2 inverter path. Long is 3 inverter path.
Figure 1. Propagation Delay vs VCC
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8 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators that have the following characteristics:
• PRR ≤ 10 MHz
• ZO = 50 Ω
NOTE
All parameters and waveforms are not applicable to all devices.
2 x VCCO
S1
RL
Open
Output Pin
Under Test
GND
CL(1)
(1)
RL
CL includes probe and jig capacitance.
Figure 2. Load Circuit
Table 1. Loading Conditions for Parameter
TEST
S1
tPLH (1), tPHL (1)
Open
tPLZ (2), tPZL (3)
VLOAD
tPHZ
(1)
(2)
(3)
(2)
, tPZH
(3)
GND
tPLH and tPHL are the same as tpd.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
Table 2. Loading Conditions for VCC – Case 1
VCC
INPUTS
VM
VLOAD
CL
RL
VΔ
≤ 2 ns
VCC / 2
2 × VCC
15 pF
1 MΩ
0.15 V
VCC
≤ 2 ns
VCC / 2
2 × VCC
15 pF
1 MΩ
0.15 V
3V
≤ 2.5 ns
1.5 V
6V
15 pF
1 MΩ
0.3 V
VCC
≤ 2.5 ns
VCC / 2
2 × VCC
15 pF
1 MΩ
0.3 V
RL
VΔ
VI
tr/tf
1.8 V ± 0.15 V
VCC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
Table 3. Loading Conditions for VCC – Case 2
VCC
8
INPUTS
VM
VLOAD
CL
≤ 2 ns
VCC / 2
2 × VCC
30 pF
1 MΩ
0.15 V
≤ 2 ns
VCC / 2
2 × VCC
30 pF
500 MΩ
0.15 V
1.5 V
6V
30 pF
500 MΩ
0.3 V
VCC / 2
2 × VCC
30 pF
500 MΩ
0.3 V
VI
tr/tf
1.8 V ± 0.15 V
VCC
2.5 V ± 0.2 V
VCC
3.3 V ± 0.3 V
3V
≤ 2.5 ns
5 V ± 0.5 V
VCC
≤ 2.5 ns
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tw
VI
Input
VM
VM
0V
Figure 3. Voltage Waveforms: Pulse Duration
VI
VM
Input
VM
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPLH
tPHL
VOH
VM
Output
VM
VOL
(1)
The outputs are measured one at a time, with one transition per measurement.
Figure 4. Voltage Waveforms: Propagation Delay Times Inverting And Noninverting Outputs
VI
VM
Timing Input
0V
tsu
th
VI
Data Input
VM
VM
0V
Figure 5. Voltage Waveforms: Setup and Hold Times
VI
Output
Control
VM
VM
0V
tPLZ
tPZL
VLOAD / 2
Output Waveform 1(1)
S1 at VLOAD
VM
VOL + V¨
tPHZ
tPZH
Output Waveform 2(2)
S1 at GND
VOL
VOH ± V¨
VOH
VM
§0V
(1)
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
(2)
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
(3)
The outputs are measured one at a time, with one transition per measurement.
Figure 6. Voltage Waveforms: Enable and Disable Times, Low- and High-Level Enabling
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9 Detailed Description
9.1 Overview
The LVC1G139 device decodes the 2-bit input to one of the four outputs. The B input is the most significant bit
and the Y outputs are active low. The propagation delays are very short and well matched (see Figure 1). Supply
voltage from 1.65-V to 5.5-V is supported.
9.2 Functional Block Diagram
A
1
3
Y3
Select
Inputs
B
2
5
Y2
Data
Outputs
6
7
Y1
Y0
9.3 Feature Description
NanoStar and NanoFree package technology is a major breakthrough in device packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
9.4 Device Functional Modes
Table 4 lists the functional modes of the SN74LVC1G139 device.
Table 4. Function Table
INPUTS
10
OUTPUTS
B
A
Y0
Y1
Y2
Y3
L
L
L
H
H
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LVC1G139 device is a 2-of-4 decoder and demultiplexer. This device decodes the 2-bit address on
inputs A (bit 0) and B (bit 1) then provides a logic low on the matching address output. It can produce 24 mA of
drive current at 3.3 V, making it ideal for driving multiple outputs.
10.2 Typical Application
This is an address line decoder using a 16-bit bus example; address bus lines 14 and 15 are decoded and drive
four active low chip selects. Each output covers 16K address space mapped by the address bus lines 0 through
13.
GND
SN74LVC1G139
PF
VCC
Address line 14
1 A
VCC 8
Address line 15
2 B
Y0 7
Chip Select 0
Chip Select 3
3 Y3
Y1 6
Chip Select 1
GND Plane
4 GND
Y2 5
Chip Select 2
Figure 7. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the
high drive will also create faster edges into light loads so routing and load conditions should be considered to
prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Rise time and fall time specifications (Δt/ΔV) are shown in the Recommended Operating Conditions table.
– Specified high (VIH) and low voltage (VIL) levels are shown in the Recommended Operating Conditions
table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
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Typical Application (continued)
10.2.3 Application Curve
9
VCC=5V
8
VCC=3.3V
7
VCC=2.5V
ICC (mA)
6
VCC=1.8V
5
4
3
2
1
0
0
5
10
15
20
25
30
Frequency (MHz)
35
40
C001
Figure 8. ICC vs Frequency
Load is 15 pF
11 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals, then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. Parallel multiple bypass capacitors are allowed to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor must be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 9 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 9. Layout Diagram
12
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2004–2018, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G139
13
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74LVC1G139DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
(R, Z)
74LVC1G139DCUTG4
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39R
SN74LVC1G139DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
(R, Z)
SN74LVC1G139DCTT
ACTIVE
SM8
DCT
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
C39
(R, Z)
SN74LVC1G139DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C39J, C39Q, C39R)
SN74LVC1G139DCUT
ACTIVE
VSSOP
DCU
8
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(C39J, C39Q, C39R)
SN74LVC1G139YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
DFN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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