74LVC2G132DCURG4

SN74LVC2G132 www.ti.com SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 Dual 2-Input NAND Gate With Schmitt-Trigger Inputs Check for Samples: SN74LVC2G132 FEATURES DESCRIPTION • This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation. 1 2 • • • • • • • • • • • Available in Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.3 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection Support Translation Down (5V to 3.3V and 3.3V to 1.8V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCT PACKAGE (TOP VIEW) The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DCU PACKAGE (TOP VIEW) 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 1A 1B 2Y GND 1 8 2 7 3 6 4 5 YZP PACKAGE (BOTTOM VIEW) VCC 1Y 2B 2A GND 2Y 1B 1A 4 5 3 6 2 7 1 8 2A 2B 1Y VCC See mechanical drawings for dimensions. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated SN74LVC2G132 SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table (Each Gate) INPUTS B OUTPUT Y L L H L H H H L H H H L A Logic Diagram (Positive Logic) 1A 1 7 1Y 2 1B 5 2A 3 2Y 6 2B Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) 2 Package thermal impedance (4) DCT package 220 DCU package 227 YZP package 102 Storage temperature range –65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 SN74LVC2G132 www.ti.com SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 Recommended Operating Conditions (1) VCC Supply voltage VI Input voltage VO Output voltage IOH High-level output current Operating Data retention only MIN MAX 1.65 5.5 1.5 5.5 V 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V –8 –16 VCC = 3 V –32 4 VCC = 2.3 V 8 16 VCC = 3 V (1) Operating free-air temperature mA 24 VCC = 4.5 V TA mA –24 VCC = 1.65 V Low-level output current V 0 VCC = 4.5 V IOL UNIT 32 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 3 SN74LVC2G132 SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT– Negative-going input threshold voltage ΔVT Hysteresis (VT+ – VT–) VCC VOH 1.16 0.79 1.16 1.56 1.11 1.56 3V 1.5 1.87 1.5 1.87 4.5 V 2.16 2.74 2.16 2.74 5.5 V 2.61 3.33 2.61 3.33 1.65 V 0.39 0.62 0.39 0.62 2.3 V 0.58 0.87 0.58 0.87 3V 0.84 1.14 0.84 1.14 4.5 V 1.41 1.79 1.41 1.79 5.5 V 1.87 2.29 1.87 2.29 1.65 V 0.37 0.62 0.37 0.62 2.3 V 0.48 0.77 0.48 0.77 3V 0.56 0.87 0.56 0.87 4.5 V 0.71 1.04 0.71 1.04 0.71 1.11 0.71 1.11 VCC – 0.1 VCC – 0.1 1.2 1.2 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3V 3.8 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 0.4 0.4 0.55 0.65 0.55 0.65 4.5 V Ioff VI or VO = 5.5 V ICC VI = VCC or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND CI VI = VCC or GND V V V 3.8 3V VI = 5.5 V or GND UNI T V IOH = –32 mA IOL = 32 mA 4 MAX 1.11 1.65 V IOL = 24 mA (1) TYP (1) 0.79 IOH = –8 mA IOL = 16 mA A or B inputs MIN IOH = –4 mA IOH = –24 mA II –40°C to 125°C MAX 2.3 V 1.65 V to 5.5 V IOH = –16 mA VOL TYP (1) 1.65 V 5.5 V IOH = –100 μA –40°C to 85°C MIN V 1.65 V to 5.5 V ±1 ±1 μA 0 ±10 ±10 μA 1.65 V to 5.5 V 10 10 μA 3 V to 5.5 V 500 500 μA 3.3 V 3.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 SN74LVC2G132 www.ti.com SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) SN74LVC2G132 –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 4 16 2.5 7 2 5.3 1.5 4.4 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC2G132 –40°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 4 16 3 7.5 2 6 2 5 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) SN74LVC2G132 –40°C to 125°C PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 4 17 3 8.5 2 7 2 6 ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 17 18 18 20 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 UNIT pF 5 SN74LVC2G132 SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 www.ti.com Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 SN74LVC2G132 www.ti.com SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 7 SN74LVC2G132 SCES547D – FEBRUARY 2004 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision C (January 2007) to Revision D Page • Updated document to new TI data sheet format. ................................................................................................................. 1 • Removed Ordering Information table. ................................................................................................................................... 1 • Added ESD warning. ............................................................................................................................................................ 2 • Updated operating temperature range. ................................................................................................................................. 3 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G132 PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74LVC2G132DCTRG4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C3B (R, Z) Samples 74LVC2G132DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C3BR Samples 74LVC2G132DCUTG4 ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM C3BR Samples SN74LVC2G132DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C3B (R, Z) Samples SN74LVC2G132DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (3B, C3BJ, C3BR) CZ Samples SN74LVC2G132DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C3BJ, C3BR) Samples SN74LVC2G132YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (D57, D5N) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of