ADC122S706
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SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013
ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter
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FEATURES
DESCRIPTION
•
The ADC122S706 is a dual 12-bit, 500 kSPS to 1
MSPS simultaneous sampling Analog-to-Digital (A/D)
converter. The analog inputs on both channels are
sampled simultaneously to preserve their relative
phase information to each other. The converter is
based on a successive-approximation register
architecture where the differential nature of the
analog inputs is maintained from the internal trackand-hold circuits throughout the A/D converter to
provide excellent common-mode signal rejection. The
ADC122S706 features an external reference that can
be varied from 1.0V to VA.
1
2
•
•
•
•
•
•
True Simultaneous Sampling Differential
Inputs
Guaranteed Performance from 500 kSPS to 1
MSPS
External Reference
Wide Input Common-Mode Voltage Range
Single or Dual High-Speed Serial Data Outputs
Operating Temperature Range of −40°C to
+105°C
SPI™/QSPI™/MICROWIRE/DSP Compatible
Serial Interface
APPLICATIONS
•
•
•
•
•
•
•
Motor Control
Power Meters/Monitors
Multi-Axis Positioning Systems
Instrumentation and Control Systems
Data Acquisition Systems
Medical Instruments
Direct Sensor Interface
KEY SPECIFICATIONS
•
•
•
•
•
•
•
Conversion Rate: 500 kSPS to 1 MSPS
INL: ±1 LSB (Max)
DNL: ±0.95 LSB (Max)
SNR: 71 dBc (Min)
THD: -72 dBc (Min)
ENOB: 11.25 Bits (Min)
Power Consumption at 1 MSPS
– Converting, VA = 5V, VD = 3V: 20 mW (Typ)
– Converting, VA = 5V, VD = 5V: 25 mW (Typ)
– Power-Down: 3 µW (Typ)
The ADC122S706 offers dual high-speed serial data
outputs that are binary 2's complement and are
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE, and many common DSP
serial interfaces. Channel A's conversion result is
outputted on DOUTA while Channel B's conversion
result is outputted on DOUTB. This feature makes the
ADC122S706 an excellent replacement for systems
using two distinct ADCs in a simultaneous sampling
application. The serial clock (SCLK) and chip select
bar (CS) are shared by both channels. For lower
power consumption, a single serial data output mode
is externally selectable.
The ADC122S706 may be operated with independent
analog (VA) and digital (VD) supplies. VA can range
from 4.5V to 5.5V and VD can range from 2.7V to VA.
With the ADC122S706 operating with a VA of 5V and
a VD of 3V, the power consumption at 1 MSPS is
typically 25 mW. Operating in power-down mode, the
power consumption of the ADC122S706 decreases to
3 µW. The differential input, low power consumption,
and small size make the ADC122S706 ideal for direct
connection to sensors in motor control applications.
Operation is guaranteed over the industrial
temperature range of −40°C to +105°C and clock
rates of 8 MHz to 16 MHz. The ADC122S706 is
available in a 14-lead TSSOP package.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
ADC122S706
SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013
www.ti.com
Connection Diagram
1
14
CS
CHA+
2
13
SCLK
CHA-
3
12
DOUTB
GND
4 ADC122S706 11
DOUTA
CHB-
5
10
CHB+
6
9
GND
VA
7
8
DUAL
VREF
VD
Block Diagram
SAR
CHA+
S/H
CHA-
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
SERIAL
INTERFACE
SAR
VREF
CHBS/H
CHB+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
2
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PIN DESCRIPTIONS
Pin No.
Symbol
Description
1
VREF
Voltage Reference Input. A voltage reference between 1V and VA must be applied to this
input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.
A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for
enhanced performance.
2
CHA+
Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential
signal applied to Channel A.
3
CHA−
Inverting Input for Channel A. CHA− is the negative analog input for the differential signal
applied to Channel A.
4
GND
Ground. GND is the ground reference point for all signals applied to the ADC122S706.
5
CHB−
Inverting Input for Channel B. CHB− is the negative analog input for the differential signal
applied to Channel B.
6
CHB+
Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential
signal applied to Channel B.
7
VA
8
DUAL
Applying a logic high to this pin causes the conversion result of Channel A to be output on
DOUTA and the conversion result of Channel B to be output on DOUTB. Grounding this pin
causes the conversion result of Channel A and B to be output on DOUTA, with the result of
Channel A being output first. DOUTB is in a high impedance state when DUAL is grounded.
9
GND
Ground. GND is the ground reference point for all signals applied to the ADC122S706.
10
VD
Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to
this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in
parallel with a bulk capacitor value of 1.0 µF to 10 µF.
Digital Power Supply input. A voltage source between 2.7V and VA must be applied to this
input. VD must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel
with a bulk capacitor value of 1.0 µF to 10 µF.
DOUTA
Serial Data Output for Channel A. With DUAL at a logic high state, the conversion result for
Channel A is provided on DOUTA. The serial data output word is comprised of 4 null bits and
12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of
SCLK and is generally valid on the rising edges. With DUAL at a logic low state, the
conversion result of Channel A and B is outputted on DOUTA.
12
DOUTB
Serial Data Output for Channel B. With DUAL at a logic high state, the conversion result for
Channel B is provided on DOUTB. The serial data output word is comprised of 4 null bits and
12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of
SCLK and is generally valid on the rising edges. With DUAL at a logic low state, DOUTB is in
a high impedance state.
13
SCLK
Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
14
CS
11
Chip Select Bar. CS is active low. The ADC122S706 is in Normal Mode when CS is LOW
and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.
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Absolute Maximum Ratings (1) (2) (3)
Analog Supply Voltage VA
−0.3V to 6.5V
Digital Supply Voltage VD
−0.3V to (VA +0.3V) max 6.5V
−0.3V to (VA +0.3V)
Voltage on Any Pin to GND
Input Current at Any Pin (4)
Package Input Current
±10 mA
(4)
±50 mA
See (5)
Power Consumption at TA = 25°C
Human Body Model
ESD Susceptibility
(6)
2500V
Machine Model
250V
Charge Device Model
1000V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited
to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to five.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC122S706 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Such conditions should always be avoided.
Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged
through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an
automated assembler) then rapidly being discharged.
Operating Ratings (1) (2)
−40°C ≤ TA ≤ +105°C
Operating Temperature Range
Supply Voltage, VA
+4.5V to +5.5V
Supply Voltage, VD
+2.7V to VA
Reference Voltage, VREF
1.0V to VA
Input Common-Mode Voltage, VCM
See Figure 46
Digital Input Pins Voltage Range
0 to VD
Clock Frequency
8 MHz to 16 MHz
−VREF to +VREF
Differential Analog Input Voltage
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance (1) (2)
(1)
(2)
4
Package
θJA
14-lead TSSOP
121°C / W
Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.
Reflow temperature profiles are different for lead-free packages.
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ADC122S706 Converter Electrical Characteristics (1)
The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 to 16 MHz, DUAL = VD, fIN
= 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units (2)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
INL
DNL
OE
GE
Integral Non-Linearity
±0.5
Integral Non-Linearity Matching
0.02
Differential Non-Linearity
±0.4
Differential Non-Linearity Matching
0.02
Offset Error
0.2
Offset Error Matching
0.1
Positive Gain Error
−2
Positive Gain Error Matching
0.2
Negative Gain Error
Bits
±1
LSB (max)
±0.95
LSB (max)
±3
LSB (max)
LSB
LSB
LSB
±5
LSB (max)
±8
LSB (max)
LSB
3
Negative Gain Error Matching
12
0.2
LSB
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
Signal-to-Noise Plus Distortion Ratio
fIN = 100 kHz, −0.1 dBFS
72.5
69.5
dBc (min)
SNR
Signal-to-Noise Ratio
fIN = 100 kHz, −0.1 dBFS
73.2
71
dBc (min)
THD
Total Harmonic Distortion
fIN = 100 kHz, −0.1 dBFS
−83
−72
dBc (max)
SFDR
Spurious-Free Dynamic Range
fIN = 100 kHz, −0.1 dBFS
84
72
dBc (min)
ENOB
Effective Number of Bits
fIN = 100 kHz, −0.1 dBFS
11.8
11.25
bits (min)
FPBW
−3 dB Full Power Bandwidth
Output at 70.7%FS
with FS Input
ISOL
Channel-to-Channel Isolation
fIN < 1 MHz
Differential Input
26
MHz
Single-Ended Input
22
MHz
−90
dBc
ANALOG INPUT CHARACTERISTICS
VIN
Differential Input Range
IDCL
DC Leakage Current
CINA
Input Capacitance
CMRR
Common Mode Rejection Ratio
VREF
Reference Voltage Range
VIN = VREF or VIN = -VREF
−VREF
V (min)
+VREF
V (max)
±1
µA (max)
In Track Mode
20
In Hold Mode
3
pF
−90
dB
See Specification Definitions
pF
1.0
V (min)
VA
V (max)
DIGITAL INPUT CHARACTERISTICS
VIH
Input High Voltage
2.4
V (min)
VIL
Input Low Voltage
0.8
V (max)
IIN
Input Current (3)
CIND
Input Capacitance
VIN = 0V or VA
±1
µA (max)
2
4
pF (max)
ISOURCE = 200 µA
VD − 0.02
VD − 0.2
V (min)
ISOURCE = 1 mA
VD − 0.09
ISINK = 200 µA
0.01
ISINK = 1 mA
0.08
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
VOL
Output Low Voltage
IOZH, IOZL TRI-STATE Leakage Current
Force 0V or VA
COUT
Force 0V or VA
TRI-STATE Output Capacitance
Output Coding
(1)
(2)
(3)
2
V
0.4
V (max)
±1
µA (max)
4
pF (max)
V
Binary 2'S Complement
Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
The digital input pin, DUAL, has a leakage current of ±5 µA.
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ADC122S706 Converter Electrical Characteristics(1) (continued)
The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 to 16 MHz, DUAL = VD, fIN
= 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units (2)
POWER SUPPLY CHARACTERISTICS
VA
Analog Supply Voltage
VD
Digital Supply Voltage
IVA
(Conv)
V (min)
5.5
V (max)
2.7
V (min)
VA
V (max)
Analog Supply Current, Continuously
Converting (Dual Data Output Mode)
fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz,
VA = 5V, DUAL = VD
3.3
4.2
mA (max)
Analog Supply Current, Continuously
Converting (Single Data Output
Mode)
fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz,
VA = 5V, DUAL = 0V
1.8
2.9
mA (max)
fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz,
VD = 5V, DUAL = 5V
1.7
2.0
mA (max)
fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz,
VD = 3V, DUAL = 3V
1.0
1.3
mA (max)
fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz,
VD = 5V, DUAL = 0V
0.9
1.2
mA (max)
fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz,
VD = 3V, DUAL = 0V
0.6
0.7
mA (max)
Reference Current, Continuously
Converting (Dual Data Output Mode)
fSCLK = 16 MHz, fS = 1 MSPS, VREF = 2.5V,
DUAL = VD
90
105
µA (max)
Reference Current, Continuously
Converting (Single Data Output
Mode)
fSCLK = 16 MHz, fS = 500 kSPS, VREF = 2.5V,
DUAL = 0V
45
60
µA (max)
1
µA (max)
Digital Supply Current, Continuously
Converting (Dual Data Output Mode)
IVD
(Conv)
Digital Supply Current, Continuously
Converting (Single Data Output
Mode)
IVREF
(Conv)
4.5
IVA (PD)
Analog Supply Current, Power Down
Mode (CS high)
fSCLK = 16 MHz, VA = 5.0V
10
fSCLK = 0, VA = 5.0V (4)
0.5
IVD (PD)
Digital Supply Current, Power Down
Mode (CS high)
fSCLK = 16 MHz, VD = 5.0V
10
IVREF
(PD)
Reference Current, Power Down
Mode (CS high)
fSCLK = 16 MHz
0.05
fSCLK = 0 (4)
Power Consumption, Continuously
Converting (Dual Data Output Mode)
PWR
(Conv)
Power Consumption, Continuously
Converting (Single Data Output
Mode)
fSCLK = 0
(4)
0.1
µA
µA
0.2
µA (max)
0.05
0.1
µA (max)
fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz,
VA = VD = 5V, VREF = 2.5V, DUAL = VD
25
31.3
mW (max)
fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz,
VA = 5V, VD = 3V, VREF = 2.5V, DUAL = VD
20
25.2
mW (max)
fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz,
VA = VD = 5V, VREF = 2.5V, DUAL = 0V
13.6
20.6
mW (max)
fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz,
VA = 5V, VD = 3V, VREF = 2.5V, DUAL = 0V
10.9
16.8
mW (max)
6.5
µW (max)
PWR
(PD)
Power Consumption, Power Down
Mode (CS high)
fSCLK = 16 MHz, VA = VD = 5.0V, VREF = 2.5V
100
fSCLK = 0, VA = VD = 5.0V, VREF = 2.5V
3.1
PSRR
Power Supply Rejection Ratio
See the Specification Definitions
−85
µA
µW
dB
AC ELECTRICAL CHARACTERISTICS
fSCLK
Maximum Clock Frequency
20
16
MHz (min)
fSCLK
Minimum Clock Frequency
0.8
8
MHz (max)
fS
Maximum Sample Rate (5)
1.25
1
MSPS (min)
tACQ
Track/Hold Acquisition Time
3
SCLK cycles
tCONV
Conversion Time
12
SCLK cycles
tAD
Aperture Delay
(4)
(5)
6
6
ns
Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/16.
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ADC122S706 Timing Specifications (1)
The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 MHz to 16 MHz, CL = 25
pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units
5
11
ns (min)
1/ fSCLK
1/ fSCLK - 3
ns (max)
4
7
ns (min)
1/ fSCLK
1/ fSCLK - 3
ns (max)
VD = +2.7V to 3.6V
22
39
ns (max)
VD = +4.5V to 5.5V
9
20
ns (max)
9
6
ns (min)
VD = +2.7V to 3.6V
24
39
ns (max)
VD = +4.5V to 5.5V
20
26
ns (max)
10
20
ns (max)
25
ns (min)
25
ns (min)
VD = +2.7V to 3.6V
tCSSU
CS Setup Time prior to an SCLK rising edge
VD = +4.5V to 5.5V
(1)
(2)
tEN
DOUT Enable Time after the falling edge of CS
tDH
DOUT Hold time after an SCLK Falling edge
tDA
DOUT Access time after an SCLK Falling edge
tDIS
DOUT Disable Time after the rising edge of CS (2)
tCH
SCLK High Time
tCL
SCLK Low Time
tr
DOUT Rise Time
7
ns
tf
DOUTFall Time
7
ns
Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
tDIS is the time for DOUT to change 10%.
Timing Diagrams
tACQ
tCONV
tPD
CS
1
2
3
4
5
6
tCH
7
8
9
10
11
12
13
14
15
16
SCLK
tEN
DOUTA
tDIS
tCL
4 Leading Zeroes
DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB4
DB3
DB2
DB1
DB0
Channel A Data
DOUTB
4 Leading Zeroes
DB11 DB10 DB9
DB8
DB7
DB6
DB5
Channel B Data
Figure 1. ADC122S706 Single Conversion Timing Diagram (DUAL Data Output Mode)
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tACQ
tCONV
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DOUTA
DB11 DB10 DB9
4 Leading Zeroes
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Channel A Data
tPower Down
CS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCLK
DOUTA
DB11 DB10 DB9
4 Leading Zeroes
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Channel B Data
Figure 2. ADC122S706 Single Conversion Timing Diagram (SINGLE Data Output Mode)
tPD
tCONV
tACQ
tACQ
tCONV
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
SCLK
DOUTB
DB11 DB10 DB9
DB8
DB7
DB6 DB5
DB4
DB3 DB2
DB1
MSB
DOUTA
DB0
DB11 DB10 DB9
LSB
MSB
DB0
DB11 DB10 DB9
LSB
MSB
DB8
HI-Z
DB11 DB10 DB9
DB8
DB7
DB6 DB5
DB4
DB3 DB2
DB1
DB8
HI-Z
MSB
Figure 3. ADC122S706 Continuous Conversion Timing Diagram (DUAL Data Output Mode)
2.4V
DOUT
SCLK
0.8V
VIL
tDA
tf
tr
2.4V
DOUT
0.8V
tDH
Figure 4. DOUT Rise and Fall Times
SCLK
1
Figure 5. DOUT Hold and Access Times
2
CS
VIH
tCSSU
90%
90%
DOUT
CS
10%
tDIS
90%
DOUT
10%
10%
Figure 6. Valid CS Assertion Times
8
Figure 7. Voltage Waveform for tDIS
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Specification Definitions
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is
acquired or held for conversion.
COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed
from 2V to 3V.
CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)
(1)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC122S706 is
guaranteed not to have any missing codes.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from negative full scale to the next code and −VREF + 0.5 LSB.
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from
code 000h to 001h and 1/2 LSB.
POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions to positive full scale and VREF minus 1.5 LSB.
POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in supply voltage is rejected.
PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in
dB. For the ADC122S706, VA is changed from 4.5V to 5.5V.
PSRR = 20 LOG (ΔOffset / ΔVA)
(2)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding d.c.
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SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the
output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as
THD = 20 ‡ log10
A f 22 +
+ A f 62
A f 12
(3)
where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the
first 5 harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion.
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Typical Performance Characteristics
VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise
stated.
DNL - 1 MSPS
INL - 1 MSPS
Figure 8.
Figure 9.
DNL vs. VA
INL vs. VA
Figure 10.
Figure 11.
DNL vs. VREF
INL vs. VREF
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise
stated.
12
DNL vs. SCLK FREQUENCY
INL vs. SCLK FREQUENCY
Figure 14.
Figure 15.
DNL vs. TEMPERATURE
INL vs. TEMPERATURE
Figure 16.
Figure 17.
SINAD vs. VA
THD vs. VA
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise
stated.
SINAD vs. VREF
THD vs. VREF
Figure 20.
Figure 21.
SINAD vs. SCLK FREQUENCY
THD vs. SCLK FREQUENCY
Figure 22.
Figure 23.
SINAD vs. INPUT FREQUENCY
THD vs. INPUT FREQUENCY
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise
stated.
14
SINAD vs. TEMPERATURE
THD vs. TEMPERATURE
Figure 26.
Figure 27.
VA CURRENT vs. VA
VA CURRENT vs. SCLK FREQ
Figure 28.
Figure 29.
VA CURRENT vs. TEMPERATURE
VREF CURRENT vs. SCLK FREQ
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise
stated.
VREF CURRENT vs. TEMP
VD CURRENT vs. SCLK FREQ
Figure 32.
Figure 33.
VD CURRENT vs. TEMP
VA CURRENT vs. VA (SINGLE DOUT)
Figure 34.
Figure 35.
VA CURRENT vs. SCLK FREQ (SINGLE DOUT)
VA CURRENT vs. TEMP (SINGLE DOUT)
Figure 36.
Figure 37.
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Typical Performance Characteristics (continued)
VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise
stated.
16
VREF CURRENT vs. SCLK (SINGLE DOUT)
VREF CURRENT vs. TEMP (SINGLE DOUT)
Figure 38.
Figure 39.
VD CURRENT vs. SCLK (SINGLE DOUT)
VD CURRENT vs. TEMP (SINGLE DOUT)
Figure 40.
Figure 41.
CMRR vs. CM RIPPLE FREQ
SPECTRAL RESPONSE - 1 MSPS
Figure 42.
Figure 43.
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FUNCTIONAL DESCRIPTION
The ADC122S706 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is
based on a successive-approximation register (SAR) architecture where the differential nature of the analog
inputs is maintained from the internal track-and-hold circuits throughout the A/D converter. The analog inputs on
both channels are sampled simultaneously to preserve their relative phase information to each other. The
architecture and process allow the ADC122S706 to acquire and convert dual analog signals at sample rates up
to 1 MSPS while consuming very little power.
The ADC122S706 operates from independent analog and digital supplies. The analog supply (VA) can range
from 4.5V to 5.5V and the digital supply (VD) can range from 2.7V to VA. The ADC122S706 utilizes an external
reference. The external reference can be any voltage between 1V and VA. The value of the reference voltage
determines the range of the analog input, while the reference input current depends upon the conversion rate.
Analog inputs are presented at the inputs of Channel A and Channel B. Upon initiation of a conversion, the
differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from the
internal circuitry while a conversion is in progress.
The ADC122S706 requires an external clock. The duty cycle of the clock is essentially unimportant, provided the
minimum clock high and low times are met. The minimum clock frequency is set by internal capacitor leakage.
Each conversion requires 16 SCLK cycles to complete. If less than 12 bits of conversion data are required, CS
can be brought high at any point during the conversion.
The ADC122S706 offers dual high-speed serial data outputs that are binary 2's complement and are compatible
with several standards, such as SPI™, QSPI™, MICROWIRE, and many common DSP serial interfaces.
Channel A's conversion result is outputted on DOUTA while Channel B's conversion result is outputted on DOUTB.
This feature makes the ADC122S706 an excellent replacement for systems using two distinct ADCs in a
simultaneous sampling application. The serial clock (SCLK) and chip select bar (CS) are shared by both
channels. The digital conversion of channel A and B is clocked out by the SCLK input and is provided serially,
most significant bit first, at DOUTA and DOUTB, respectively. The digital data that is provided at DOUTA and DOUTB is
that of the conversion currently in progress. With CS held low after the conversion is complete, the ADC122S706
continuously converts the analog inputs. For lower power consumption, a single serial data output mode is
externally selectable. This feature makes the ADC122S706 an excellent replacement for two independent ADCs
that are part of a daisy chain configuration.
REFERENCE INPUT
The externally supplied reference voltage sets the analog input range. The ADC122S706 will operate with a
reference voltage in the range of 1V to VA.
Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the
reference voltage (VREF) is reduced, the range of acceptable analog input voltages is reduced. Assuming a
proper common-mode input voltage, the differential peak-to-peak input range is limited to twice VREF. See Input
Common Mode Voltage for more details. Reducing the value of VREF also reduces the size of the least significant
bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes
below the noise floor of the ADC122S706, the noise will span an increasing number of codes and overall
performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements
will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be
reduced by averaging the results of a number of consecutive conversions.
Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D
converter will increase in terms of LSB size as the reference voltage is reduced.
The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the
input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of
transient spikes that occur at a frequency dependent on the operating sample rate of the ADC122S706.
The reference current changes only slightly with temperature. See Figure 38 and Figure 39 in Typical
Performance Characteristics for additional details.
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ANALOG SIGNAL INPUTS
The ADC122S706 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus
CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters,
operation with a fully differential input signal or voltage will provide better performance than with a single-ended
input. However, the ADC122S706 can be presented with a single-ended input.
The current required to recharge the input sampling capacitor will cause voltage spikes at the + and − inputs. Do
not try to filter out these noise spikes. Rather, ensure that the transient settles out during the acquisition period
(three SCLK cycles after the fall of CS).
Differential Input Operation
With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be
obtained when DIFFINA or DIFFINB is greater than or equal to VREF − 1.5 LSB. A negative full scale code (1000
0000 0000b or 800h) will be obtained when DIFFINA or DIFFINB is greater than or equal to −VREF + 0.5 LSB.
This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will
determine any given output code. Figure 44 shows the ADC122S706 being driven by a full-scale differential
source.
VREF
2
VCM
VREF
VCM 2
VCM +
RS
+
SRC
CS
ADC122S706
-
RS
VREF
2
VCM
VREF
VCM 2
VCM +
Figure 44. Differential Input
Single-Ended Input Operation
For single-ended operation, the non-inverting inputs of the ADC122S706 can be driven with a signal that has a
maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting inputs
should be biased at a stable voltage that is halfway between these maximum and minimum values. In order to
utilize the entire dynamic range of the ADC122S706, the reference voltage is limited at VA / 2. This allows the
non-inverting inputs the maximum swing range of ground to VA. Figure 45 shows the ADC122S706 being driven
by a full-scale single-ended source.
VCM + VREF
VCM
VCM - VREF
RS
+
SRC
CS
ADC122S706
-
VCM
Figure 45. Single-Ended Input
Since the design of the ADC122S706 is optimized for a differential input, the performance degrades slightly when
driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and
dynamic characteristics such as SINAD typically degrades by 2 dB. Note that single-ended operation should only
be used if the performance degradation (compared with differential operation) is acceptable.
18
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Input Common Mode Voltage
The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used
for the ADC122S706. The ranges of VCM are depicted in Figure 46 and Figure 47. Equations for calculating the
minimum and maximum common mode voltages for differential and single-ended operation are shown in
Table 1.
6
6
Single-Ended Input
5
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
Differential Input
VA = 5.0V
3.75
2.5
1.25
0
-1
0.0
1.0
2.0 2.5 3.0
4.0
5
VA = 5.0V
3.75
2.5
1.25
0
-1
0.0
5.0
0.75
VREF (V)
1.25
1.75
2.5
VREF (V)
Figure 46. VCM range for Differential Input
operation
Figure 47. VCM range for single-ended operation
Table 1. Allowable VCM Range
Input Signal
Differential
Single-Ended
Minimum VCM
Maximum VCM
VREF / 2
VA − VREF / 2
VREF
VA − VREF
SERIAL DIGITAL INTERFACE
The ADC122S706 communicates via a synchronous serial interface as shown in Timing Diagrams. CS, chip
select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion
process and the timing of the serial data. DOUTA and DOUTB are the serial data output pins, where the conversion
results of Channel A and Channel B are sent as serial data streams, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC122S706's data
output pins are in a high impedance state when CS is high and are active when CS is low; thus CS acts as an
output enable. A timing diagram for a single conversion is shown in Figure 1.
During the first three cycles of SCLK, the ADC122S706 is in acquisition mode (tACQ), tracking the input voltage.
For the next twelve SCLK cycles (tCONV), the conversion is accomplished and the data is clocked out. SCLK
falling edges one through four clock out leading zeros while falling edges five through sixteen clock out the
conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the
ADC122S706 will re-enter acquisition mode on the falling edge of SCLK after the N*16th rising edge of SCLK
and re-enter the conversion mode on the N*16+4th falling edge of SCLK as shown in Figure 3. "N" is an integer
value.
The ADC122S706 can enter acquisition mode under three different conditions. The first condition involves CS
going low (asserted) with SCLK high. In this case, the ADC122S706 enters acquisition mode on the first falling
edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition,
the ADC122S706 automatically enters acquisition mode and the falling edge of CS is seen as the first falling
edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC122S706 enters
acquisition mode. While there is no timing restriction with respect to the falling edges of CS and the falling edge
of SCLK, see Figure 6 for setup and hold time requirements for the falling edge of CS with respect to the rising
edge of SCLK.
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CS Input
The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S706 is in
conversion mode when CS is low and power-down mode when CS is high. As a result, CS frames the
conversion window. The falling edge of CS marks the beginning of a conversion and the rising edge of CS marks
the end of a conversion window. Multiple conversions can occur within a given conversion frame with each
conversion requiring sixteen SCLK cycles. This is referred to as continuous conversion mode and is shown in
Figure 3 of Timing Diagrams.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the
5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
Timing Specifications.
SCLK Input
The SCLK (serial clock) serves two purposes in the ADC122S706. It is used by the ADC as the conversion clock
and it is used as the serial clock to output the conversion results. This SCLK input is CMOS compatible. Internal
settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum
clock frequency. The ADC122S706 offers guaranteed performance with the clock rates indicated in the electrical
table.
Data Output(s)
The ADC122S706 enables system designers two options for receiving converted data from the ADC122S706.
Data can be received from separate data output pins (DOUTA and DOUTB) or from a single data output line. These
options are controlled by the digital input pin DUAL. With the DUAL pin set to a logic high level, the dual highspeed serial outputs are enabled. Channel A's conversion result is outputted on DOUTA while Channel B's
conversion result is outputted on DOUTB. With the DUAL pin set to a logic low level, the conversion result of
Channel A and Channel B is outputted on DOUTA, with the result of Channel A being outputted before the result of
Channel B. The DOUTB pin is in a high impedance state during this condition. See Figure 1 and Figure 2 in Timing
Diagrams for more details on DUAL and SINGLE DOUT mode.
The output data format of the ADC122S706 is two’s complement, as shown in Table 2. This table indicates the
ideal output code for the given input voltage and does not include the effects of offset, gain error, linearity errors,
or noise. Each data bit is output on the falling edge of SCLK.
Table 2. Ideal Output Code vs. Input Voltage
Analog Input, (+IN) − (−IN)
2's Complement Binary Output
2's Comp. Hex Code
2's Comp. Dec Code
VREF − 1.5 LSB
0111 1111 1111
7FF
2047
+ 0.5 LSB
0000 0000 0001
001
1
− 0.5 LSB
0000 0000 0000
000
0
0V − 1.5 LSB
1111 1111 1111
FFF
−1
−VREF + 0.5 LSB
1000 0000 0000
800
−2048
While data is output on the falling edges of SCLK, receiving systems have the option of capturing the data on the
subsequent rising or falling edge of SCLK. The maximum specification for tDA (DOUT access time after an SCLK
falling edge) is provided for two power supply ranges. If the system is operating at the maximum clock frequency
of 16 MHz and a VD supply voltage of 3V, it would be necessary for the receiver to capture data on the
subsequent falling edge of SCLK in order to guarantee performance over the entire temperature range.
Operating at a VD supply voltage of 5V or an SCLK frequency less than 10 MHz allows data to be captured on
either edge of SCLK. If a receiving system is going to capture data on the subsequent falling edge of SCLK, it is
important to make sure that the minimum hold time after an SCLK falling edge (tDH) is acceptable. See Figure 5
for DOUT hold and access times.
DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th
falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new
conversion will begin when CS is taken LOW.
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Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC122S706:
−40°C ≤ TA ≤ +105°C
+4.5V ≤ VA ≤ +5.5V
+2.7V ≤ VD ≤ VA
1V ≤ VREF ≤ VA
8 MHz ≤ fSCLK ≤ 16 MHz
VCM: See Input Common Mode Voltage
POWER CONSUMPTION
The architecture, design, and fabrication process allow the ADC122S706 to operate at conversion rates up to 1
MSPS while consuming very little power. The ADC122S706 consumes the least amount of power while operating
in power down mode. For applications where power consumption is critical, the ADC122S706 should be
operated in power down mode as often as the application will tolerate. To further reduce power consumption,
stop the SCLK while CS is high.
Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 12-bit resolution, or where
an analog signal is being monitored until some condition occurs. For example, it may not be necessary to use the
full 12-bit resolution of the ADC122S706 as long as the signal being monitored is within certain limits. In some
circumstances, the conversion could be terminated after the first few bits. This will lower power consumption in
the converter since the ADC122S706 spends more time in power down mode and less time in the conversion
mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC122S706
output. This is possible because the ADC122S706 places the latest converted data bit on DOUT as it is
generated. If only 8-bits of the conversion result are needed, for example, the conversion can be terminated by
pulling CS high after the 8th bit has been clocked out.
Burst Mode Operation
Normal operation of the ADC122S706 requires the SCLK frequency to be sixteen times the sample rate and the
CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 500 kSPS, the ADC122S706 should be run with an SCLK frequency of 16 MHz and
a CS rate as slow as the system requires. When this is accomplished, the ADC122S706 is operating in burst
mode. The ADC122S706 enters into power down mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest possible time in power down mode. Since power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
Single DOUT mode
With the DUAL pin connected to a logic low level, the ADC122S706 is operating in single DOUT mode. In single
DOUT mode, the conversion result of Channel A and Channel B are both output on DOUTA (see Figure 2).
Operating in this mode causes the maximum conversion rate to be reduced to 500kSPS while operating with an
SCLK frequency of 16 MHz. This is a result of the conversion window changing from 16 clock cycles to 32 clock
cycles to receive the conversion result of Channel A and Channel B. Since the conversion of Channel A and
Channel B are still performed simultaneously, the ADC122S706 still enters a power down state on the 16th
falling edge of SCLK. The increased time spent in power down mode causes the power consumption of the
ADC122S706 to reduce nearly by a factor of two. See the Power Supply Characteristics Table for more details.
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POWER SUPPLY CONSIDERATIONS AND PCB LAYOUT
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for
settling, so it is important that any noise settles out before the conversion begins.
Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
ADC122S706 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF
capacitor should be used to bypass the ADC122S706 supply, with the 0.1 µF capacitor placed as close to the
ADC122S706 package as possible.
Since the ADC122S706 has both an analog and a digital supply pin, the user has three options. The first option
is to tie the analog and digital supply pins together and power them with the same power supply. This is the most
cost effective way of powering the ADC122S706 but it is also the least ideal. As stated previously, noise from the
digital supply pin can couple into the analog supply pin and adversely affect performance. The other two options
involve the user powering the analog and digital supply pins with separate supply voltages. These supply
voltages can have the same amplitude or they can be different. The only design constraint is that the digital
supply voltage be less than the analog supply voltage. This is not usually a problem since many applications
prefer a digital interface of 3V while operating the analog section of the ADC122S706 at 5V. Operating the digital
supply pin at 3V as apposed to 5V offers two advantages. It lowers the power consumption of the ADC122S706
and it decreases the noise created by charging and discharging the capacitance of the digital interface pins.
Voltage Reference
The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor
value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the
ADC122S706 draws very little current from the reference on average, there are higher instantaneous current
spikes at the reference input.
The reference input of the ADC122S706, like all A/D converters, does not reject noise or voltage variations. Keep
this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply
that is not rejected by the external reference circuitry will appear in the digital results. The use of an active
reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and
LM4140 series reference families are excellent choices for a reference source.
PCB Layout
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock lines
short as possible. Digital circuits create substantial supply and ground current transients. The logic noise
generated could have significant impact upon system noise performance. To avoid performance degradation of
the ADC122S706 due to supply noise, avoid using the same supply for the VA and VREF of the ADC122S706
that is used for digital circuitry on the board.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital
power plane. Furthermore, the GND pin on the ADC122S706 and all the components in the reference circuitry
and input signal chain that are connected to ground should be connected to the ground plane at a quiet point.
Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal
processor, or other high power digital device.
22
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ADC122S706
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SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013
APPLICATION CIRCUITS
The following figures are examples of the ADC122S706 in typical application circuits. These circuits are basic
and will generally require modification for specific circumstances.
Data Acquisition
Figure 48 shows a basic low cost, low power data acquisition circuit. The analog and digital supply pins are
powered by the system +5V supply and the 2.5V reference voltage is generated by the LM4040-2.5 shunt
reference.
+5V
+
2 k:
10 PF
ADC122S706
+
LM4040-2.5
VREF
VA
0.1 PF
0.1 PF
10 PF
VD
CHA+
Microcontroller
SCLK
DIFFINA
CHA- DOUTA
GND
CHB-
DOUTB
CSB
DIFFINB
CHB+
Figure 48. Low cost, low power Data Acquisition System
Current Sensing Application
Figure 49 shows an example of interfacing a pair of current transducers to the ADC122S706. The current
transducers convert an input current into a voltage that is converted by the ADC. Since the output voltage of the
current transducers are single-ended and centered around a common-mode voltage of 2.5V, the ADC122S706 is
configured with the output of the transducer driving the non-inverting inputs and the common-mode output
voltage of the transducer driving the inverting input. The output of the transducer has an output range of ±2V
around the common-mode voltage of 2.5V. As a result, a series reference voltage of 2.0V is connected to the
ADC122S706. This will allow all of the codes of the ADC122S706 to be available for the application. This
configuration of the ADC122S706 is referred to as a single-ended application of a differential ADC. All of the
elements in the application are conveniently powered by the same +5V power supply, keeping circuit complexity
and cost to a minimum.
+5V
+
10 PF
LM4132-2.0
+
VREF
10 PF
ADC122S706
VA
0.1 PF
0.1 PF
VD
IIN
IOUT
2.5V + 2.0V
OUT
IIN +5V
IOUT VCM
GND
SCLK
CHA+
ADC
2.5V
Serial
Interface
GND
IIN
IOUT
DOUTA
CHA-
2.5V
VCM
IIN +5V
IOUT OUT
GND
CSB
CHBADC
2.5V + 2.0V
DOUTB
CHB+
DUAL
+5V
LTSR-15NPs
Figure 49. Interfacing the ADC122S706 to a Current Transducer
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23
ADC122S706
SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013
www.ti.com
Bridge Sensor Application
Figure 50 shows an example of interfacing the ADC122S706 to a pair of bridge sensors. The application
assumes that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC
and thus optimize the performance of the entire signal path. The amplification stage for each ADC input consists
of a pair of opamps from the LMP7704. The amplification stage offers the benefit of high input impedance and
potentially high amplification. On the other hand, it offers no common-mode rejection of noise coming from the
bridge sensors. The application circuit assumes the bridge sensors are powered from the same +5V power
supply voltage as the analog supply pin on the ADC122S706. This has the benefit of providing the ideal
common-mode input voltage for the ADC122S706 while keeping design complexity and cost to a minimum. The
LM4132-4.1, a 4.1V series reference, is used as the reference voltage in the application.
+5V
+5V = VA,VD
+
-
470 pF
100 k:
ADC122S706
180 :
ADC_A
2 k:
100 k:
+
Bridge
Sensor
180 :
SCLK
DOUTA
AV = 100 V/V
Serial Interface
LMP7704
+5V
DOUTB
CSB
+
-
470 pF
100 k:
180 :
ADC_B
2 k:
100 k:
+
Bridge
Sensor
180 :
VREF
AV = 100 V/V
LM4132-4.1
+
0.1 PF
4.7 PF
+5V
+
4.7 PF
Figure 50. Interfacing the ADC122S706 to Bridge Sensors
24
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Product Folder Links: ADC122S706
ADC122S706
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SNAS408A – NOVEMBER 2007 – REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ADC122S706CIMT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
2S706
CIMT
ADC122S706CIMTX/NOPB
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
2S706
CIMT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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