ADC122S706EB

ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter November 16, 2007 ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter General Description The ADC122S706 is a dual 12-bit, 500 kSPS to 1 MSPS simultaneous sampling Analog-to-Digital (A/D) converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other. The converter is based on a successive-approximation register architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter to provide excellent commonmode signal rejection. The ADC122S706 features an external reference that can be varied from 1.0V to VA. The ADC122S706 offers dual high-speed serial data outputs that are binary 2's complement and are compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. Channel A's conversion result is outputted on DOUTA while Channel B's conversion result is outputted on DOUTB. This feature makes the ADC122S706 an excellent replacement for systems using two distinct ADCs in a simultaneous sampling application. The serial clock (SCLK) and chip select bar (CS) are shared by both channels. For lower power consumption, a single serial data output mode is externally selectable. The ADC122S706 may be operated with independent analog (VA) and digital (VD) supplies. VA can range from 4.5V to 5.5V and VD can range from 2.7V to VA. With the ADC122S706 operating with a VA of 5V and a VD of 3V, the power consumption at 1 MSPS is typically 25 mW. Operating in powerdown mode, the power consumption of the ADC122S706 decreases to 3 µW. The differential input, low power consumption, and small size make the ADC122S706 ideal for direct connection to sensors in motor control applications. Operation is guaranteed over the industrial temperature range of −40°C to +105°C and clock rates of 8 MHz to 16 MHz. The ADC122S706 is available in a 14-lead TSSOP package. Features ■ ■ ■ ■ ■ ■ ■ True Simultaneous Sampling Differential Inputs Guaranteed performance from 500 kSPS to 1 MSPS External Reference Wide Input Common-Mode Voltage Range Single or Dual High-Speed Serial Data Outputs Operating Temperature Range of −40°C to +105°C SPI™/QSPI™/MICROWIRE™/DSP compatible Serial Interface Key Specifications ■ ■ ■ ■ ■ ■ ■ ■ Conversion Rate 500 kSPS to 1 MSPS INL ±1 LSB (max) DNL ±0.95 LSB (max) SNR 71 dBc (min) THD -72 dBc (min) ENOB 11.25 bits (min) Power Consumption at 1 MSPS 20 mW (typ) — Converting, VA = 5V, VD = 3V 25 mW (typ) — Converting, VA = 5V, VD = 5V 3 µW (typ) — Power-Down Applications ■ ■ ■ ■ ■ ■ ■ Motor Control Power Meters/Monitors Multi-Axis Positioning Systems Instrumentation and Control Systems Data Acquisition Systems Medical Instruments Direct Sensor Interface Connection Diagram 30017105 TRI-STATE® is a trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2007 National Semiconductor Corporation 300171 www.national.com ADC122S706 Ordering Information Order Code ADC122S706CIMT ADC122S706CIMTX ADC122S706EB Temperature Range −40°C to +105°C −40°C to +105°C Description 14-Lead TSSOP Package, 1000 Units Tape & Reel 14-Lead TSSOP Package, 3500 Units Tape & Reel Evaluation Board Top Mark 2S706 2S706 Block Diagram 30017102 www.national.com 2 ADC122S706 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description Voltage Reference Input. A voltage reference between 1V and VA must be applied to this input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for enhanced performance. Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential signal applied to Channel A. Inverting Input for Channel A. CHA− is the negative analog input for the differential signal applied to Channel A. Ground. GND is the ground reference point for all signals applied to the ADC122S706. Inverting Input for Channel B. CHB− is the negative analog input for the differential signal applied to Channel B. Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential signal applied to Channel B. Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF. Applying a logic high to this pin causes the conversion result of Channel A to be output on DOUTA and the conversion result of Channel B to be output on DOUTB. Grounding this pin causes the conversion result of Channel A and B to be output on DOUTA, with the result of Channel A being output first. DOUTB is in a high impedance state when DUAL is grounded. Ground. GND is the ground reference point for all signals applied to the ADC122S706. Digital Power Supply input. A voltage source between 2.7V and VA must be applied to this input. VD must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF. Serial Data Output for Channel A. With DUAL at a logic high state, the conversion result for Channel A is provided on DOUTA. The serial data output word is comprised of 4 null bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of SCLK and is generally valid on the rising edges. With DUAL at a logic low state, the conversion result of Channel A and B is outputted on DOUTA. Serial Data Output for Channel B. With DUAL at a logic high state, the conversion result for Channel B is provided on DOUTB. The serial data output word is comprised of 4 null bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling edges of SCLK and is generally valid on the rising edges. With DUAL at a logic low state, DOUTB is in a high impedance state. Serial Clock. SCLK is used to control data transfer and serves as the conversion clock. Chip Select Bar. CS is active low. The ADC122S706 is in Normal Mode when CS is LOW and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS. 1 VREF 2 3 4 5 6 CHA+ CHA− GND CHB− CHB+ 7 VA 8 DUAL 9 10 GND VD 11 DOUTA 12 DOUTB 13 14 SCLK CS 3 www.national.com ADC122S706 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage VA Digital Supply Voltage VD Voltage on Any Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Charge Device Model Junction Temperature Storage Temperature −0.3V to 6.5V −0.3V to (VA +0.3V) max 6.5V −0.3V to (VA +0.3V) ±10 mA ±50 mA See (Note 4) 2500V 250V 1000V +150°C −65°C to +150°C Operating Ratings (Notes 1, 2) −40°C ≤ TA ≤ +105°C Supply Voltage, VA +4.5V to +5.5V Supply Voltage, VD +2.7V to VA Reference Voltage, VREF 1.0V to VA Input Common-Mode Voltage, VCM See Figure 10 (Sect 2.3) Digital Input Pins Voltage Range 0 to VD Clock Frequency 8 MHz to 16 MHz Differential Analog Input Voltage −VREF to +VREF Operating Temperature Range Package Thermal Resistance Package 14-lead TSSOP θJA 121°C / W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) (Note 8) The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 to 16 MHz, DUAL = VD, fIN = 100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C. Symbol Parameter Conditions Typical Limits Units (Note 7) Bits LSB (max) LSB ±0.95 ±3 ±5 ±8 LSB (max) LSB LSB (max) LSB LSB (max) LSB LSB (max) LSB 69.5 71 −72 72 11.25 dBc (min) dBc (min) dBc (max) dBc (min) bits (min) MHz MHz dBc −VREF +VREF VIN = VREF or VIN = -VREF In Track Mode In Hold Mode 20 3 ±1 V (min) V (max) µA (max) pF pF ADC122S706 Converter Electrical Characteristics STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL OE Integral Non-Linearity Integral Non-Linearity Matching Differential Non-Linearity Differential Non-Linearity Matching Offset Error Offset Error Matching Positive Gain Error GE Positive Gain Error Matching Negative Gain Error Negative Gain Error Matching DYNAMIC CONVERTER CHARACTERISTICS SINAD SNR THD SFDR ENOB Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits fIN = 100 kHz, −0.1 dBFS fIN = 100 kHz, −0.1 dBFS fIN = 100 kHz, −0.1 dBFS fIN = 100 kHz, −0.1 dBFS fIN = 100 kHz, −0.1 dBFS Differential Output at 70.7%FS with Input FS Input Single-Ended Input fIN < 1 MHz 72.5 73.2 −83 84 11.8 26 22 −90 ±0.5 0.02 ±0.4 0.02 0.2 0.1 −2 0.2 3 0.2 12 ±1 FPBW −3 dB Full Power Bandwidth ISOL Channel-to-Channel Isolation ANALOG INPUT CHARACTERISTICS VIN IDCL CINA Differential Input Range DC Leakage Current Input Capacitance www.national.com 4 ADC122S706 Symbol CMRR VREF Parameter Common Mode Rejection Ratio Reference Voltage Range Conditions See the Specification Definitions for the test condition Typical −90 Limits Units (Note 7) dB 1.0 VA 2.4 0.8 VIN = 0V or VA 2 ISOURCE = 200 µA ISOURCE = 1 mA ISINK = 200 µA ISINK = 1 mA Force 0V or VA Force 0V or VA 2 VD − 0.02 VD − 0.09 0.01 0.08 ±1 4 0.4 ±1 4 VD − 0.2 V (min) V (max) V (min) V (max) µA (max) pF (max) V (min) V V (max) V µA (max) pF (max) DIGITAL INPUT CHARACTERISTICS VIH VIL IIN CIND Input High Voltage Input Low Voltage Input Current (Note 11) Input Capacitance DIGITAL OUTPUT CHARACTERISTICS VOH VOL IOZH, IOZL COUT Output High Voltage Output Low Voltage TRI-STATE Leakage Current TRI-STATE Output Capacitance Output Coding POWER SUPPLY CHARACTERISTICS VA VD Analog Supply Voltage Digital Supply Voltage Analog Supply Current, Continuously Converting (Dual Data Output Mode) Analog Supply Current, Continuously Converting (Single Data Output Mode) Digital Supply Current, Continuously Converting (Dual Data Output Mode) IVD (Conv) Digital Supply Current, Continuously Converting (Single Data Output Mode) Reference Current, Continuously Converting (Dual Data Output Mode) Reference Current, Continuously Converting (Single Data Output Mode) Analog Supply Current, Power Down Mode (CS high) Digital Supply Current, Power Down Mode (CS high) Reference Current, Power Down Mode (CS high) fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz, VA = 5V, DUAL = VD fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz, VA = 5V, DUAL = 0V fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz, VD = 5V, DUAL = 5V fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz, VD = 3V, DUAL = 3V fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz, VD = 5V, DUAL = 0V fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz, VD = 3V, DUAL = 0V fSCLK = 16 MHz, fS = 1 MSPS, VREF = 2.5V, DUAL = VD fSCLK = 16 MHz, fS = 500 kSPS, VREF = 2.5V, DUAL = 0V fSCLK = 16 MHz, VA = 5.0V fSCLK = 0, VA = 5.0V (Note 8) fSCLK = 16 MHz, VD = 5.0V fSCLK = 0 (Note 8) fSCLK = 16 MHz fSCLK = 0 (Note 8) 3.3 1.8 1.7 1.0 0.9 0.6 90 45 10 0.5 10 0.1 0.05 0.05 0.1 0.2 1 4.5 5.5 2.7 VA 4.2 2.9 2.0 1.3 1.2 0.7 105 60 V (min) V (max) V (min) V (max) mA (max) mA (max) mA (max) mA (max) mA (max) mA (max) µA (max) µA (max) µA µA (max) µA µA (max) µA µA (max) Binary 2'S Complement IVA (Conv) IVREF (Conv) IVA (PD) IVD (PD) IVREF (PD) 5 www.national.com ADC122S706 Symbol Parameter Conditions fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz, VA = VD = 5V, VREF = 2.5V, DUAL = VD fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100 kHz, VA = 5V, VD = 3V, VREF = 2.5V, DUAL = VD fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz, VA = VD = 5V, VREF = 2.5V, DUAL = 0V fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100 kHz, VA = 5V, VD = 3V, VREF = 2.5V, DUAL = 0V Typical Limits Units (Note 7) mW (max) 25 31.3 Power Consumption, Continuously Converting (Dual Data Output Mode) PWR (Conv) Power Consumption, Continuously Converting (Single Data Output Mode) 20 25.2 mW (max) 13.6 20.6 mW (max) 10.9 16.8 mW (max) PWR (PD) PSRR fSCLK = 16 MHz, VA = VD = 5.0V, VREF = Power Consumption, Power Down Mode 2.5V (CS high) fSCLK = 0, VA = VD = 5.0V, VREF = 2.5V Power Supply Rejection Ratio See the Specification Definitions for the test condition 100 3.1 −85 6.5 µW µW (max) dB AC ELECTRICAL CHARACTERISTICS fSCLK fSCLK fS tACQ tCONV tAD Maximum Clock Frequency Minimum Clock Frequency Maximum Sample Rate Track/Hold Acquisition Time Conversion Time Aperture Delay 6 20 0.8 1.25 16 8 1 3 12 MHz (min) MHz (max) MSPS (min) SCLK cycles SCLK cycles ns www.national.com 6 ADC122S706 (Note 8) The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 MHz to 16 MHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions VD = +2.7V to 3.6V tCSSU CS Setup Time prior to an SCLK rising edge VD = +4.5V to 5.5V tEN tDH tDA tDIS tCH tCL tr tf DOUT Enable Time after the falling edge of CS DOUT Hold time after an SCLK Falling edge DOUT Access time after an SCLK Falling edge DOUT Disable Time after the rising edge of CS (Note 10) SCLK High Time SCLK Low Time DOUT Rise Time DOUT Fall Time 7 7 VD = +2.7V to 3.6V VD = +4.5V to 5.5V VD = +2.7V to 3.6V VD = +4.5V to 5.5V Typical 5 1/ fSCLK 4 1/ fSCLK 22 9 9 24 20 10 Limits 11 1/ fSCLK - 3 7 1/ fSCLK - 3 39 20 6 39 26 20 25 25 Units ns (min) ns (max) ns (min) ns (max) ns (max) ns (max) ns (min) ns (max) ns (max) ns (max) ns (min) ns (min) ns ns ADC122S706 Timing Specifications Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC122S706 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 6: Reflow temperature profiles are different for lead-free packages. Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/16. Note 10: tDIS is the time for DOUT to change 10%. Note 11: The digital input pin, DUAL, has a leakage current of ±5 µA. 7 www.national.com ADC122S706 Timing Diagrams 30017101 FIGURE 1. ADC122S706 Single Conversion Timing Diagram (DUAL Data Output Mode) 30017142 FIGURE 2. ADC122S706 Single Conversion Timing Diagram (SINGLE Data Output Mode) www.national.com 8 ADC122S706 30017104 FIGURE 3. ADC122S706 Continuous Conversion Timing Diagram (DUAL Data Output Mode) 30017106 FIGURE 4. DOUT Rise and Fall Times 30017112 FIGURE 7. Voltage Waveform for tDIS 30017111 FIGURE 5. DOUT Hold and Access Times 30017110 FIGURE 6. Valid CS Assertion Times 9 www.national.com ADC122S706 Specification Definitions APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is acquired or held for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. CMRR = 20 LOG ( Δ Common Input / Δ Output Offset) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC122S706 is guaranteed not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from negative full scale to the next code and −VREF + 0.5 LSB. NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error. OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 000h to 001h and 1/2 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and VREF minus 1.5 LSB. POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the ADC122S706, VA is changed from 4.5V to 5.5V. PSRR = 20 LOG (ΔOffset / ΔVA) SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. www.national.com 10 ADC122S706 Typical Performance Characteristics DNL - 1 MSPS VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. INL - 1 MSPS 30017121 30017122 DNL vs. VA INL vs. VA 30017123 30017124 DNL vs. VREF INL vs. VREF 30017118 30017119 11 www.national.com ADC122S706 Typical Performance Characteristics DNL vs. SCLK FREQUENCY VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. INL vs. SCLK FREQUENCY 30017125 30017126 DNL vs. TEMPERATURE INL vs. TEMPERATURE 30017129 30017130 SINAD vs. VA THD vs. VA 30017133 30017132 www.national.com 12 ADC122S706 Typical Performance Characteristics SINAD vs. VREF VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. THD vs. VREF 30017137 30017136 SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY 30017141 30017140 SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY 30017149 30017148 13 www.national.com ADC122S706 Typical Performance Characteristics SINAD vs. TEMPERATURE VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. THD vs. TEMPERATURE 30017172 30017171 VA CURRENT vs. VA VA CURRENT vs. SCLK FREQ 30017174 30017155 VA CURRENT vs. TEMPERATURE VREF CURRENT vs. SCLK FREQ 30017154 30017152 www.national.com 14 ADC122S706 Typical Performance Characteristics VREF CURRENT vs. TEMP VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. VD CURRENT vs. SCLK FREQ 30017151 30017156 VD CURRENT vs. TEMP VA CURRENT vs. VA (SINGLE DOUT) 30017158 30017175 VA CURRENT vs. SCLK FREQ (SINGLE DOUT) VA CURRENT vs. TEMP (SINGLE DOUT) 30017176 30017177 15 www.national.com ADC122S706 Typical Performance Characteristics VREF CURRENT vs. SCLK (SINGLE DOUT) VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated. VREF CURRENT vs. TEMP (SINGLE DOUT) 30017178 30017179 VD CURRENT vs. SCLK (SINGLE DOUT) VD CURRENT vs. TEMP (SINGLE DOUT) 30017157 30017159 CMRR vs. CM RIPPLE FREQ SPECTRAL RESPONSE - 1 MSPS 30017173 30017114 www.national.com 16 ADC122S706 Functional Description The ADC122S706 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is based on a successive-approximation register (SAR) architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other. The architecture and process allow the ADC122S706 to acquire and convert dual analog signals at sample rates up to 1 MSPS while consuming very little power. The ADC122S706 operates from independent analog and digital supplies. The analog supply (VA) can range from 4.5V to 5.5V and the digital supply (VD) can range from 2.7V to VA. The ADC122S706 utilizes an external reference. The external reference can be any voltage between 1V and VA. The value of the reference voltage determines the range of the analog input, while the reference input current depends upon the conversion rate. Analog inputs are presented at the inputs of Channel A and Channel B. Upon initiation of a conversion, the differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry while a conversion is in progress. The ADC122S706 requires an external clock. The duty cycle of the clock is essentially unimportant, provided the minimum clock high and low times are met. The minimum clock frequency is set by internal capacitor leakage. Each conversion requires 16 SCLK cycles to complete. If less than 12 bits of conversion data are required, CS can be brought high at any point during the conversion. The ADC122S706 offers dual high-speed serial data outputs that are binary 2's complement and are compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. Channel A's conversion result is outputted on DOUTA while Channel B's conversion result is outputted on DOUTB. This feature makes the ADC122S706 an excellent replacement for systems using two distinct ADCs in a simultaneous sampling application. The serial clock (SCLK) and chip select bar (CS) are shared by both channels. The digital conversion of channel A and B is clocked out by the SCLK input and is provided serially, most significant bit first, at DOUTA and DOUTB, respectively. The digital data that is provided at DOUTA and DOUTB is that of the conversion currently in progress. With CS held low after the conversion is complete, the ADC122S706 continuously converts the analog inputs. For lower power consumption, a single serial data output mode is externally selectable. This feature makes the ADC122S706 an excellent replacement for two independent ADCs that are part of a daisy chain configuration. 1.0 REFERENCE INPUT The externally supplied reference voltage sets the analog input range. The ADC122S706 will operate with a reference voltage in the range of 1V to VA. Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the reference voltage (V REF) is reduced, the range of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage, the differential peak-to-peak input range is limited to twice VREF. See Section 2.3 for more details. Reducing the value of VREF also reduces the size of the least significant bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes below the noise floor of the ADC122S706, the noise will span an increasing number of codes and overall performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D converter will increase in terms of LSB size as the reference voltage is reduced. The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of transient spikes that occur at a frequency dependent on the operating sample rate of the ADC122S706. The reference current changes only slightly with temperature. See the curves, “Reference Current vs. SCLK Frequency” and “Reference Current vs. Temperature” in the Typical Performance Curves section for additional details. 2.0 ANALOG SIGNAL INPUTS The ADC122S706 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. However, the ADC122S706 can be presented with a single-ended input. The current required to recharge the input sampling capacitor will cause voltage spikes at the + and − inputs. Do not try to filter out these noise spikes. Rather, ensure that the transient settles out during the acquisition period (three SCLK cycles after the fall of CS). 2.1 Differential Input Operation With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be obtained when DIFFINA or DIFFINB is greater than or equal to VREF − 1.5 LSB. A negative full scale code (1000 0000 0000b or 800h) will be obtained when DIFFINA or DIFFINB is greater than or equal to −VREF + 0.5 LSB. This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will determine any given output code. Figure 8 shows the ADC122S706 being driven by a full-scale differential source. 30017180 FIGURE 8. Differential Input 17 www.national.com ADC122S706 2.2 Single-Ended Input Operation For single-ended operation, the non-inverting inputs of the ADC122S706 can be driven with a signal that has a maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting inputs should be biased at a stable voltage that is halfway between these maximum and minimum values. In order to utilize the entire dynamic range of the ADC122S706, the reference voltage is limited at VA / 2. This allows the non-inverting inputs the maximum swing range of ground to VA. Figure 9 shows the ADC122S706 being driven by a full-scale single-ended source. 30017162 FIGURE 11. VCM range for single-ended operation TABLE 1. Allowable VCM Range 30017181 Input Signal Differential Single-Ended Minimum VCM VREF / 2 VREF Maximum VCM VA − VREF / 2 VA − VREF FIGURE 9. Single-Ended Input Since the design of the ADC122S706 is optimized for a differential input, the performance degrades slightly when driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and dynamic characteristics such as SINAD typically degrades by 2 dB. Note that single-ended operation should only be used if the performance degradation (compared with differential operation) is acceptable. 2.3 Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon the supply and reference voltages used for the ADC122S706. The ranges of VCM are depicted in Figure 10 and Figure 11. Equations for calculating the minimum and maximum common mode voltages for differential and singleended operation are shown in Table 1. 30017161 FIGURE 10. VCM range for Differential Input operation 3.0 SERIAL DIGITAL INTERFACE The ADC122S706 communicates via a synchronous serial interface as shown in the Timing Diagram section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of the serial data. DOUTA and DOUTB are the serial data output pins, where the conversion results of Channel A and Channel B are sent as serial data streams, MSB first. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC122S706's data output pins are in a high impedance state when CS is high and are active when CS is low; thus CS acts as an output enable. A timing diagram for a single conversion is shown in Figure 1. During the first three cycles of SCLK, the ADC122S706 is in acquisition mode (tACQ), tracking the input voltage. For the next twelve SCLK cycles (tCONV), the conversion is accomplished and the data is clocked out. SCLK falling edges one through four clock out leading zeros while falling edges five through sixteen clock out the conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the ADC122S706 will re-enter acquisition mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter the conversion mode on the N*16+4th falling edge of SCLK as shown in Figure 3. "N" is an integer value. The ADC122S706 can enter acquisition mode under three different conditions. The first condition involves CS going low (asserted) with SCLK high. In this case, the ADC122S706 enters acquisition mode on the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the ADC122S706 automatically enters acquisition mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC122S706 enters acquisition mode. While there is no timing restriction with respect to the falling edges of CS and the falling edge of SCLK, see Figure 6 for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. 18 www.national.com ADC122S706 3.1 CS Input The CS (chip select bar) is an active low input that is TTL and CMOS compatible. The ADC122S706 is in conversion mode when CS is low and power-down mode when CS is high. As a result, CS frames the conversion window. The falling edge of CS marks the beginning of a conversion and the rising edge of CS marks the end of a conversion window. Multiple conversions can occur within a given conversion frame with each conversion requiring sixteen SCLK cycles. This is referred to as continuous conversion mode and is shown in Figure 3 of the Timing Diagram section. Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the 5th falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the Timing Specification table. 3.2 SCLK Input The SCLK (serial clock) serves two purposes in the ADC122S706. It is used by the ADC as the conversion clock and it is used as the serial clock to output the conversion results. This SCLK input is CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC122S706 offers guaranteed performance with the clock rates indicated in the electrical table. 3.3 Data Output(s) The ADC122S706 enables system designers two options for receiving converted data from the ADC122S706. Data can be received from separate data output pins (DOUTA and DOUTB) or from a single data output line. These options are controlled by the digital input pin DUAL. With the DUAL pin set to a logic high level, the dual high-speed serial outputs are enabled. Channel A's conversion result is outputted on DOUTA while Channel B's conversion result is outputted on DOUTB. With the DUAL pin set to a logic low level, the conversion result of Channel A and Channel B is outputted on DOUTA, with the result of Channel A being outputted before the result of Channel B. The DOUTB pin is in a high impedance state during this condition. See Figure 1 and Figure 2 in the Timing Diagram section for more details on DUAL and SINGLE DOUT mode. The output data format of the ADC122S706 is two’s complement, as shown in Table 2. This table indicates the ideal output code for the given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data bit is output on the falling edge of SCLK. TABLE 2. Ideal Output Code vs. Input Voltage Analog Input (+IN) − (−IN) 2's 2's 2's Complement Comp. Comp. Binary Output Hex Code Dec Code 7FF 001 000 FFF 800 2047 1 0 −1 −2048 0000 0000 0001 0000 0000 0000 1111 1111 1111 quent rising or falling edge of SCLK. The maximum specification for tDA (DOUT access time after an SCLK falling edge) is provided for two power supply ranges. If the system is operating at the maximum clock frequency of 16MHz and a VD supply voltage of 3V, it would be necessary for the receiver to capture data on the subsequent falling edge of SCLK in order to guarantee performance over the entire temperature range. Operating at a VD supply voltage of 5V or an SCLK frequency less than 10MHz allows data to be captured on either edge of SCLK. If a receiving system is going to capture data on the subsequent falling edge of SCLK, it is important to make sure that the minimum hold time after an SCLK falling edge (tDH) is acceptable. See Figure 5 for DOUT hold and access times. DOUT is enabled on the falling edge of CS and disabled on the rising edge of CS. If CS is raised prior to the 16th falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new conversion will begin when CS is taken LOW. Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC122S706: −40°C ≤ TA ≤ +105°C +4.5V ≤ VA ≤ +5.5V +2.7V ≤ VD ≤ VA 1V ≤ VREF ≤ VA 8 MHz ≤ fSCLK ≤ 16 MHz VCM: See Section 2.3 4.0 POWER CONSUMPTION The architecture, design, and fabrication process allow the ADC122S706 to operate at conversion rates up to 1 MSPS while consuming very little power. The ADC122S706 consumes the least amount of power while operating in power down mode. For applications where power consumption is critical, the ADC122S706 should be operated in power down mode as often as the application will tolerate. To further reduce power consumption, stop the SCLK while CS is high. 4.1 Short Cycling Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can be used to lower the power consumption in those applications that do not need a full 12-bit resolution, or where an analog signal is being monitored until some condition occurs. For example, it may not be necessary to use the full 12-bit resolution of the ADC122S706 as long as the signal being monitored is within certain limits. In some circumstances, the conversion could be terminated after the first few bits. This will lower power consumption in the converter since the ADC122S706 spends more time in power down mode and less time in the conversion mode. Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC122S706 output. This is possible because the ADC122S706 places the latest converted data bit on DOUT as it is generated. If only 8-bits of the conversion result are needed, for example, the conversion can be terminated by pulling CS high after the 8th bit has been clocked out. VREF − 1.5 LSB 0111 1111 1111 + 0.5 LSB − 0.5 LSB 0V − 1.5 LSB −VREF + 0.5 LSB 1000 0000 0000 While data is output on the falling edges of SCLK, receiving systems have the option of capturing the data on the subse19 www.national.com ADC122S706 4.2 Burst Mode Operation Normal operation of the ADC122S706 requires the SCLK frequency to be sixteen times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 500 kSPS, the ADC122S706 should be run with an SCLK frequency of 16 MHz and a CS rate as slow as the system requires. When this is accomplished, the ADC122S706 is operating in burst mode. The ADC122S706 enters into power down mode at the end of each conversion, minimizing power consumption. This causes the converter to spend the longest possible time in power down mode. Since power consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. 4.3 Single DOUT mode With the DUAL pin connected to a logic low level, the ADC122S706 is operating in single DOUT mode. In single DOUT mode, the conversion result of Channel A and Channel B are both output on DOUTA (see Figure 2). Operating in this mode causes the maximum conversion rate to be reduced to 500kSPS while operating with an SCLK frequency of 16MHz. This is a result of the conversion window changing from 16 clock cycles to 32 clock cycles to receive the conversion result of Channel A and Channel B. Since the conversion of Channel A and Channel B are still performed simultaneously, the ADC122S706 still enters a power down state on the 16th falling edge of SCLK. The increased time spent in power down mode causes the power consumption of the ADC122S706 to reduce nearly by a factor of two. See the Power Supply Characteristics Table for more details. 5.0 POWER SUPPLY CONSIDERATIONS AND PCB LAYOUT For best performance, care should be taken with the physical layout of the printed circuit board. This is especially true with a low reference voltage or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out before the conversion begins. 5.1 Analog and Digital Power Supplies Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the ADC122S706 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor should be used to bypass the ADC122S706 supply, with the 0.1 µF capacitor placed as close to the ADC122S706 package as possible. Since the ADC122S706 has both an analog and a digital supply pin, the user has three options. The first option is to tie the analog and digital supply pins together and power them with the same power supply. This is the most cost effective way of powering the ADC122S706 but it is also the least ideal. As stated previously, noise from the digital supply pin can couple into the analog supply pin and adversely affect performance. The other two options involve the user powering the analog and digital supply pins with separate supply voltages. These supply voltages can have the same amplitude or they can be different. The only design constraint is that the digital supply voltage be less than the analog supply voltage. This is not usually a problem since many applications prefer a digital interface of 3V while operating the analog section of the ADC122S706 at 5V. Operating the digital supply pin at 3V as apposed to 5V offers two advantages. It lowers the power consumption of the ADC122S706 and it decreases the noise created by charging and discharging the capacitance of the digital interface pins. 5.2 Voltage Reference The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the ADC122S706 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference input. The reference input of the ADC122S706, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if the reference voltage is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results. The use of an active reference source is recommended. The LM4040 and LM4050 shunt reference families and the LM4132 and LM4140 series reference families are excellent choices for a reference source. 5.3 PCB Layout Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the ADC122S706 due to supply noise, avoid using the same supply for the VA and VREF of the ADC122S706 that is used for digital circuity on the board. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. A single, uniform ground plane and the use of split power planes are recommended. The power planes should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry and I/ O lines should be placed over the digital power plane. Furthermore, the GND pin on the ADC122S706 and all the components in the reference circuitry and input signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device. www.national.com 20 ADC122S706 6.0 APPLICATION CIRCUITS The following figures are examples of the ADC122S706 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. 6.1 Data Acquisition Figure 12 shows a basic low cost, low power data acquisition circuit. The analog and digital supply pins are powered by the system +5V supply and the 2.5V reference voltage is generated by the LM4040-2.5 shunt reference. 6.2 Current Sensing Application Figure 13 shows an example of interfacing a pair of current transducers to the ADC122S706. The current transducers convert an input current into a voltage that is converted by the ADC. Since the output voltage of the current transducers are single-ended and centered around a common-mode voltage of 2.5V, the ADC122S706 is configured with the output of the transducer driving the non-inverting inputs and the commonmode output voltage of the transducer driving the inverting input. The output of the transducer has an output range of ±2V around the common-mode voltage of 2.5V. As a result, a series reference voltage of 2.0V is connected to the ADC122S706. This will allow all of the codes of the ADC122S706 to be available for the application. This configuration of the ADC122S706 is referred to as a single-ended application of a differential ADC. All of the elements in the application are conveniently powered by the same +5V power supply, keeping circuit complexity and cost to a minimum. 30017134 FIGURE 12. Low cost, low power Data Acquisition System 30017138 FIGURE 13. Interfacing the ADC122S706 to a Current Transducer 21 www.national.com ADC122S706 6.3 Bridge Sensor Application Figure 14 shows an example of interfacing the ADC122S706 to a pair of bridge sensors. The application assumes that the bridge sensors require buffering and amplification to fully utilize the dynamic range of the ADC and thus optimize the performance of the entire signal path. The amplification stage for each ADC input consists of a pair of opamps from the LMP7704. The amplification stage offers the benefit of high input impedance and potentially high amplification. On the other hand, it offers no common-mode rejection of noise coming from the bridge sensors. The application circuit assumes the bridge sensors are powered from the same +5V power supply voltage as the analog supply pin on the ADC122S706. This has the benefit of providing the ideal common-mode input voltage for the ADC122S706 while keeping design complexity and cost to a minimum. The LM4132-4.1, a 4.1V series reference, is used as the reference voltage in the application. 30017135 FIGURE 14. Interfacing the ADC122S706 to Bridge Sensors www.national.com 22 ADC122S706 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead TSSOP Order Number ADC122S706CIMM NS Package Number MTC14 23 www.national.com ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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